https://github.com/keryell commented:
Quite interesting! At some point it would be nice to have some design document or documentation somewhere explaining how all these MLIR runners works, including this one. Globally this PR add a SYCL runner, but it is very specific for Intel Level 0. It would be nice to have in the future some generalization, like SYCL using OpenCL interoperability interface to run the SPIR-V kernels or even native kernels. https://github.com/llvm/llvm-project/pull/65539 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
