https://github.com/ecnelises closed
https://github.com/llvm/llvm-project/pull/73750
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ecnelises wrote:
Gentle ping
https://github.com/llvm/llvm-project/pull/73750
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ecnelises wrote:
@llvm/pr-subscribers-backend-powerpc
https://github.com/llvm/llvm-project/pull/68861
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https://github.com/llvm/llvm-project/pull/73750
>From db3bd53b27ee5fcb0572e0a43ca4cd4ed1376e65 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Tue, 10 Sep 2024 15:25:37 +0800
Subject: [PATCH] [PowerPC] Support set_flt_rounds builtin
---
clang/docs/Languag
https://github.com/ecnelises approved this pull request.
Thanks
https://github.com/llvm/llvm-project/pull/106012
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ecnelises wrote:
Could you pick the test change from
https://github.com/ecnelises/llvm-project/commit/9dcb9c96d565f282ca716693b37c65674c3f7edd
into this patch?
https://github.com/llvm/llvm-project/pull/106012
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https://github.com/llvm/llvm-project/pull/94581
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https://github.com/llvm/llvm-project/pull/94581
>From a3d3cf70e2c80683a73db5a93ae4223c2d64f597 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Thu, 6 Jun 2024 14:06:48 +0800
Subject: [PATCH 1/3] [PowerPC] Support -mno-red-zone option
---
clang/lib/Driver/
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/94581
>From a3d3cf70e2c80683a73db5a93ae4223c2d64f597 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Thu, 6 Jun 2024 14:06:48 +0800
Subject: [PATCH 1/3] [PowerPC] Support -mno-red-zone option
---
clang/lib/Driver/
@@ -515,6 +515,16 @@ TARGET_BUILTIN(__builtin_altivec_vctzh, "V8UsV8Us", "",
"power9-vector")
TARGET_BUILTIN(__builtin_altivec_vctzw, "V4UiV4Ui", "", "power9-vector")
TARGET_BUILTIN(__builtin_altivec_vctzd, "V2ULLiV2ULLi", "", "power9-vector")
+// P7 BCD builtins.
+TARGET_BUI
https://github.com/ecnelises closed
https://github.com/llvm/llvm-project/pull/97524
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https://github.com/llvm/llvm-project/pull/97524
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https://github.com/llvm/llvm-project/pull/97524
>From 654cf7753023302c367340872e889856f8738169 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Wed, 3 Jul 2024 14:17:01 +0800
Subject: [PATCH 1/3] [AIX] Add -msave-reg-params to save arguments to stack
In Pow
ecnelises wrote:
Thanks for pointing LTO stuff out. Do you mean the module flags might be
messed up when merging in LTO? I thought a file level codegen option can be
mapped to a module level flag.
https://github.com/llvm/llvm-project/pull/97524
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>From 654cf7753023302c367340872e889856f8738169 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Wed, 3 Jul 2024 14:17:01 +0800
Subject: [PATCH 1/2] [AIX] Add -msave-reg-params to save arguments to stack
In Pow
https://github.com/ecnelises converted_to_draft
https://github.com/llvm/llvm-project/pull/97524
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@@ -0,0 +1,37 @@
+//=== PPCTargetParser - Parser for target features --*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/97524
>From 654cf7753023302c367340872e889856f8738169 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Wed, 3 Jul 2024 14:17:01 +0800
Subject: [PATCH] [AIX] Add -msave-reg-params to save arguments to stack
In PowerPC
https://github.com/ecnelises created
https://github.com/llvm/llvm-project/pull/97524
In PowerPC ABI, a few initial arguments are passed through registers, but their
places in parameter save area are reserved, arguments passed by memory goes
after the reserved location.
For debugging purpose,
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/94581
>From 4e078099d8e15fd984ef38435d6f792bbb3d754c Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Thu, 6 Jun 2024 14:06:48 +0800
Subject: [PATCH 1/2] [PowerPC] Support -mno-red-zone option
---
clang/lib/Driver/
ecnelises wrote:
No. `-disable-red-zone` does nothing but add `noredzone` IR attribute to
functions. We need to add cases to test for `noredzone` behavior on PPC (arm
and x86 have).
https://github.com/llvm/llvm-project/pull/94581
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https://github.com/ecnelises created
https://github.com/llvm/llvm-project/pull/94581
None
>From 4e078099d8e15fd984ef38435d6f792bbb3d754c Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Thu, 6 Jun 2024 14:06:48 +0800
Subject: [PATCH] [PowerPC] Support -mno-red-zone option
---
clang/lib/Drive
https://github.com/ecnelises closed
https://github.com/llvm/llvm-project/pull/86783
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https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/86783
>From b886dcf2da25417d9f8cd75ff4aa58686e35139d Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Wed, 27 Mar 2024 17:11:04 +0800
Subject: [PATCH 1/4] [PowerPC] Implement 32-bit expansion for rldimi
rldimi is 64
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/86783
>From b886dcf2da25417d9f8cd75ff4aa58686e35139d Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Wed, 27 Mar 2024 17:11:04 +0800
Subject: [PATCH 1/3] [PowerPC] Implement 32-bit expansion for rldimi
rldimi is 64
https://github.com/ecnelises edited
https://github.com/llvm/llvm-project/pull/86783
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https://github.com/llvm/llvm-project/pull/86783
>From b886dcf2da25417d9f8cd75ff4aa58686e35139d Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Wed, 27 Mar 2024 17:11:04 +0800
Subject: [PATCH 1/2] [PowerPC] Implement 32-bit expansion for rldimi
rldimi is 64
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/86783
>From b886dcf2da25417d9f8cd75ff4aa58686e35139d Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Wed, 27 Mar 2024 17:11:04 +0800
Subject: [PATCH] [PowerPC] Implement 32-bit expansion for rldimi
rldimi is 64-bit
https://github.com/ecnelises created
https://github.com/llvm/llvm-project/pull/86783
rldimi is 64-bit instruction, due to backward compatibility, it needs to be
expanded into series of rlwimi in 32-bit environment. In the future, we may
improve bit permutation selector and remove such direct c
https://github.com/ecnelises closed
https://github.com/llvm/llvm-project/pull/85040
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>From 4977659b16a7f220e1a738a0b9841102fe9f1d07 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Wed, 13 Mar 2024 15:46:51 +0800
Subject: [PATCH 1/4] [PowerPC] Fix behavior of rldimi/rlwimi/rlwnm builtins
rldim
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/85040
>From 4977659b16a7f220e1a738a0b9841102fe9f1d07 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Wed, 13 Mar 2024 15:46:51 +0800
Subject: [PATCH 1/3] [PowerPC] Fix behavior of rldimi/rlwimi/rlwnm builtins
rldim
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/85040
>From 4977659b16a7f220e1a738a0b9841102fe9f1d07 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Wed, 13 Mar 2024 15:46:51 +0800
Subject: [PATCH 1/2] [PowerPC] Fix behavior of rldimi/rlwimi/rlwnm builtins
rldim
https://github.com/ecnelises edited
https://github.com/llvm/llvm-project/pull/85040
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https://github.com/llvm/llvm-project/pull/85040
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https://github.com/llvm/llvm-project/pull/85040
>From 4977659b16a7f220e1a738a0b9841102fe9f1d07 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Wed, 13 Mar 2024 15:46:51 +0800
Subject: [PATCH] [PowerPC] Fix behavior of rldimi/rlwimi/rlwnm builtins
rldimi is
https://github.com/ecnelises created
https://github.com/llvm/llvm-project/pull/85040
rldimi is 64-bit instruction, so the corresponding builtin should not be
available in 32-bit mode. Also, clang should check if shift amount and mask are
consistent.
>From d5aa72a2d0ed083919b37cc1faacad1f3addc
https://github.com/ecnelises closed
https://github.com/llvm/llvm-project/pull/82968
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https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/82968
>From a06fa5e18313ad50019d50006e34a6b8249d95cd Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Mon, 26 Feb 2024 16:32:28 +0800
Subject: [PATCH 1/4] [PowerPC] Add intrinsics for rldimi/rlwimi/rlwnm
These built
@@ -1,61 +1,111 @@
-; All of these ands and shifts should be folded into rlwimi's
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o %t
-; RUN: not grep and %t
-; RUN: not grep srawi %t
-; RUN: not grep srwi %t
-; RUN: not grep slwi %t
-; RUN: grep rlwinm %t | count 8
+; N
@@ -1,61 +1,111 @@
-; All of these ands and shifts should be folded into rlwimi's
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o %t
-; RUN: not grep and %t
-; RUN: not grep srawi %t
-; RUN: not grep srwi %t
-; RUN: not grep slwi %t
-; RUN: grep rlwinm %t | count 8
+; N
@@ -58,3 +58,18 @@ entry:
%8 = or i64 %6, %7
ret i64 %8
}
+
+define i64 @rldimi_intrinsic(i64 %a) {
+; CHECK-LABEL: rldimi_intrinsic:
+; CHECK: # %bb.0:
+; CHECK-NEXT:rldimi 3, 3, 8, 0
+; CHECK-NEXT:rldimi 3, 3, 16, 0
+; CHECK-NEXT:rldimi 3, 3, 32, 0
+; CH
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/82968
>From a06fa5e18313ad50019d50006e34a6b8249d95cd Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Mon, 26 Feb 2024 16:32:28 +0800
Subject: [PATCH 1/3] [PowerPC] Add intrinsics for rldimi/rlwimi/rlwnm
These built
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/82968
>From a06fa5e18313ad50019d50006e34a6b8249d95cd Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Mon, 26 Feb 2024 16:32:28 +0800
Subject: [PATCH 1/2] [PowerPC] Add intrinsics for rldimi/rlwimi/rlwnm
These built
https://github.com/ecnelises created
https://github.com/llvm/llvm-project/pull/82968
These builtins are already there in Clang, however current codegen may produce
suboptimal results due to their complex behavior. Implement them as intrinsics
to ensure expected instructions are emitted.
>From
https://github.com/ecnelises edited
https://github.com/llvm/llvm-project/pull/66978
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@@ -14428,15 +14431,52 @@ SDValue PPCTargetLowering::combineSetCC(SDNode *N,
// x != 0-y --> x+y != 0
if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
RHS.hasOneUse()) {
- SDLoc DL(N);
- SelectionDAG &DAG = DCI.DAG;
- EVT VT
ecnelises wrote:
The motivating case:
```llvm
define i64 @splatByte(i64 %a) {
entry:
%x0 = shl i64 %a, 8
%x1 = and i64 %a, 255
%x2 = or i64 %x0, %x1
%x3 = shl i64 %x2, 16
%x4 = and i64 %x2, 65535
%x5 = or i64 %x3, %x4
%x6 = shl i64 %x5, 32
%x7 = and i64 %x5, 4294967295
%x8 = or
@@ -442,19 +442,44 @@ void PPCTargetInfo::getTargetDefines(const LangOptions
&Opts,
// _CALL_DARWIN
}
-// Handle explicit options being passed to the compiler here: if we've
-// explicitly turned off vsx and turned on any of:
-// - power8-vector
-// - direct-move
-// - fl
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/76488
>From 7eb909423d49ea19d9978b097ceb8c4a95fc7bac Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Thu, 28 Dec 2023 11:09:07 +0800
Subject: [PATCH 1/5] [PowerPC] Peephole address calculation in TOC memops
---
ll
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/76488
>From 7eb909423d49ea19d9978b097ceb8c4a95fc7bac Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Thu, 28 Dec 2023 11:09:07 +0800
Subject: [PATCH 1/4] [PowerPC] Peephole address calculation in TOC memops
---
ll
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/76488
>From 7eb909423d49ea19d9978b097ceb8c4a95fc7bac Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Thu, 28 Dec 2023 11:09:07 +0800
Subject: [PATCH 1/3] [PowerPC] Peephole address calculation in TOC memops
---
ll
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/66040
>From ebaafdd6d45bb62b1847e60df627dfd96971a22c Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Tue, 12 Sep 2023 10:39:55 +0800
Subject: [PATCH] [PowerPC] Check value uses in ValueBit tracking
---
llvm/lib/Ta
https://github.com/ecnelises closed
https://github.com/llvm/llvm-project/pull/76495
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https://github.com/ecnelises ready_for_review
https://github.com/llvm/llvm-project/pull/76488
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https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/76488
>From 7eb909423d49ea19d9978b097ceb8c4a95fc7bac Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Thu, 28 Dec 2023 11:09:07 +0800
Subject: [PATCH 1/2] [PowerPC] Peephole address calculation in TOC memops
---
ll
@@ -0,0 +1,14 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang -target powerpc64le -c %s -mllvm -stop-after=finalize-isel -o -
| \
+// RUN: FileCheck %s
+// RUN: %clang -target powerpc64 -c %s -mllvm -stop-after=finalize-isel -o - |
\
+// RUN: FileCheck %s
@@ -0,0 +1,14 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang -target powerpc64le -c %s -mllvm -stop-after=finalize-isel -o -
| \
+// RUN: FileCheck %s
+// RUN: %clang -target powerpc64 -c %s -mllvm -stop-after=finalize-isel -o - |
\
+// RUN: FileCheck %s
@@ -782,6 +782,8 @@ ArrayRef PPCTargetInfo::getGCCRegNames()
const {
const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
// While some of these aliases do map to different registers
// they still share the same register name.
+// Strictly speaking, "ca
@@ -0,0 +1,14 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang -target powerpc64le -c %s -mllvm -stop-after=finalize-isel -o -
| \
+// RUN: FileCheck %s
+// RUN: %clang -target powerpc64 -c %s -mllvm -stop-after=finalize-isel -o - |
\
+// RUN: FileCheck %s
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/67302
>From a1567f579531c3abbd1f4e9b7c7edd2f95ead42c Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Mon, 25 Sep 2023 17:10:51 +0800
Subject: [PATCH 1/7] [PowerPC] Implement llvm.set.rounding intrinsic
According to
@@ -8900,6 +8900,82 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
return FP;
}
+SDValue PPCTargetLowering::LowerSET_ROUNDING(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDLoc Dl(Op);
+ MachineFunction &MF = DAG.getMachi
ecnelises wrote:
> Maybe we can do some perf test between this expansion for set rounding mode
> and the system library's version for fesetround().
They are faster than system `fesetround` on both Linux and AIX. Linux glibc
optimizes `fesetround` with faster `mffscrn` on P9, I just exploited t
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/67302
>From a1567f579531c3abbd1f4e9b7c7edd2f95ead42c Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Mon, 25 Sep 2023 17:10:51 +0800
Subject: [PATCH 1/6] [PowerPC] Implement llvm.set.rounding intrinsic
According to
@@ -8900,6 +8900,82 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
return FP;
}
+SDValue PPCTargetLowering::LowerSET_ROUNDING(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDLoc Dl(Op);
+ MachineFunction &MF = DAG.getMachi
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/76495
>From aaa11bc775b9aa3a0398ba2bbca4087e99f04243 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Thu, 28 Dec 2023 16:54:25 +0800
Subject: [PATCH 1/4] [PowerPC] Implement fence builtin
---
clang/include/clang/B
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/77412
>From 87e1d4acdd87d45f265e590ad135e21f352dc5ad Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Tue, 9 Jan 2024 13:33:56 +0800
Subject: [PATCH 1/3] [Legalizer] Soften EXTRACT_ELEMENT on ppcf128
ppc_fp128 value
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/67301
>From 92abb76631594dfc2ca586c46c38031610be0548 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Mon, 25 Sep 2023 17:08:59 +0800
Subject: [PATCH 1/6] [Legalizer] Expand fmaximum and fminimum
According to langre
@@ -8262,6 +8262,64 @@ SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode
*Node,
return SDValue();
}
+SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N,
+SelectionDAG &DAG) const {
+ SDLoc DL(N);
+ SDValue LHS = N-
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/77412
>From 87e1d4acdd87d45f265e590ad135e21f352dc5ad Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Tue, 9 Jan 2024 13:33:56 +0800
Subject: [PATCH 1/2] [Legalizer] Soften EXTRACT_ELEMENT on ppcf128
ppc_fp128 value
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/76495
>From aaa11bc775b9aa3a0398ba2bbca4087e99f04243 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Thu, 28 Dec 2023 16:54:25 +0800
Subject: [PATCH 1/3] [PowerPC] Implement fence builtin
---
clang/include/clang/B
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/76495
>From aaa11bc775b9aa3a0398ba2bbca4087e99f04243 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Thu, 28 Dec 2023 16:54:25 +0800
Subject: [PATCH 1/2] [PowerPC] Implement fence builtin
---
clang/include/clang/B
https://github.com/ecnelises ready_for_review
https://github.com/llvm/llvm-project/pull/76495
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https://github.com/ecnelises created
https://github.com/llvm/llvm-project/pull/76495
This builtin will work as barrier for instruction motion (scheduling, etc.)
>From aaa11bc775b9aa3a0398ba2bbca4087e99f04243 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Thu, 28 Dec 2023 16:54:25 +0800
Subje
ecnelises wrote:
Ping
https://github.com/llvm/llvm-project/pull/71696
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ecnelises wrote:
> Is there any existing vector test coverage?
Yes, there are vector tests in PowerPC's fminimum-fmaximum.ll.
https://github.com/llvm/llvm-project/pull/67301
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@@ -8262,6 +8262,64 @@ SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode
*Node,
return SDValue();
}
+SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N,
+SelectionDAG &DAG) const {
+ SDLoc DL(N);
+ SDValue LHS = N-
@@ -8262,6 +8262,64 @@ SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode
*Node,
return SDValue();
}
+SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N,
+SelectionDAG &DAG) const {
+ SDLoc DL(N);
+ SDValue LHS = N-
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/67301
>From 92abb76631594dfc2ca586c46c38031610be0548 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Mon, 25 Sep 2023 17:08:59 +0800
Subject: [PATCH 1/5] [Legalizer] Expand fmaximum and fminimum
According to langre
ecnelises wrote:
I tested with a number of random floating values. In most of the cases, the
expanded result is exactly the same as libcall result.
But when `fmod(a,b)` is very close to `b` (smaller than `1e-10`, for example,
`fmod(521862.045173469, 31.048432006988875)`), the result would be t
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/71696
>From 1d0109b7f370a3689a92e20ab52597b112669e47 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Thu, 9 Nov 2023 00:00:26 +0800
Subject: [PATCH 1/4] [Clang][Sema] Fix qualifier restriction of overriden
methods
@@ -2399,6 +2405,30 @@ bool PPCFrameLowering::assignCalleeSavedSpillSlots(
return AllSpilledToReg;
}
+static void findContinuousLoadStore(ArrayRef CSI,
+Register &MergeFrom) {
+ CalleeSavedInfo BeginI = CSI[0];
+ unsigned I = 1, E = CSI.
@@ -2607,6 +2658,11 @@ bool PPCFrameLowering::restoreCalleeSavedRegisters(
unsigned CSIIndex = 0;
BitVector Restored(TRI->getNumRegs());
+ Register MergeFrom = PPC::R31;
+ if (EnableLoadStoreMultiple && !Subtarget.isLittleEndian() &&
+ !Subtarget.isPPC64())
+fin
@@ -2513,7 +2548,23 @@ bool PPCFrameLowering::spillCalleeSavedRegisters(
!MF->getFunction().hasFnAttribute(Attribute::NoUnwind))
TII.storeRegToStackSlotNoUpd(MBB, MI, Reg, !IsLiveIn,
I.getFrameIdx(), RC, TRI);
-
@@ -0,0 +1,110 @@
+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs \
+; RUN: -mcpu=pwr4 -mattr=-altivec --ppc-enable-load-store-multiple < %s \
+; RUN: | FileCheck %s
+
+; CHECK: stmw 16, 64(1) # 4-byte Folded Spill
+; CHECK: lmw 16, 64(1)# 4-byte
@@ -1676,6 +1676,10 @@
PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP &&
OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC);
ecnelises wrote:
@@ -2399,6 +2405,30 @@ bool PPCFrameLowering::assignCalleeSavedSpillSlots(
return AllSpilledToReg;
}
+static void findContinuousLoadStore(ArrayRef CSI,
+Register &MergeFrom) {
+ CalleeSavedInfo BeginI = CSI[0];
ecnelises
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/66978
>From 2a7b9be6cd0705590c85c51b35ea99fe053aaf47 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Wed, 6 Sep 2023 16:16:34 +0800
Subject: [PATCH 1/4] [PowerPC] Combine sub within setcc back to sext
---
llvm/lib
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/67642
>From 2ff3a666e4347f9224c1a406126282d98e3c9633 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Thu, 28 Sep 2023 16:09:40 +0800
Subject: [PATCH 1/2] [DAGCombiner] Combine frem into fdiv+ftrunc+fma
---
llvm/li
ecnelises wrote:
> The patch looks good but I am not familiar with PPC instructions enough.
> Could you please run the runtime tests from here:
> https://github.com/llvm/llvm-test-suite/tree/main/MultiSource/UnitTests/Float/rounding?
> You just need to build application from two files: clang r
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/67302
>From a1567f579531c3abbd1f4e9b7c7edd2f95ead42c Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Mon, 25 Sep 2023 17:10:51 +0800
Subject: [PATCH 1/4] [PowerPC] Implement llvm.set.rounding intrinsic
According to
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/67302
>From a1567f579531c3abbd1f4e9b7c7edd2f95ead42c Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Mon, 25 Sep 2023 17:10:51 +0800
Subject: [PATCH 1/3] [PowerPC] Implement llvm.set.rounding intrinsic
According to
@@ -8900,6 +8900,83 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
return FP;
}
+SDValue PPCTargetLowering::LowerSET_ROUNDING(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDLoc Dl(Op);
+ MachineFunction &MF = DAG.getMachi
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/66978
>From 2a7b9be6cd0705590c85c51b35ea99fe053aaf47 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Wed, 6 Sep 2023 16:16:34 +0800
Subject: [PATCH 1/3] [PowerPC] Combine sub within setcc back to sext
---
llvm/lib
https://github.com/ecnelises closed
https://github.com/llvm/llvm-project/pull/67298
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https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/66978
>From 2a7b9be6cd0705590c85c51b35ea99fe053aaf47 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Wed, 6 Sep 2023 16:16:34 +0800
Subject: [PATCH 1/2] [PowerPC] Combine sub within setcc back to sext
---
llvm/lib
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/67302
>From a1567f579531c3abbd1f4e9b7c7edd2f95ead42c Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Mon, 25 Sep 2023 17:10:51 +0800
Subject: [PATCH 1/2] [PowerPC] Implement llvm.set.rounding intrinsic
According to
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/67298
>From 58cd725354eae6aa733c98374a804de0ef595c60 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Mon, 25 Sep 2023 16:57:39 +0800
Subject: [PATCH 1/2] [PowerPC] Disable float128 on AIX in Clang
PowerPC AIX backe
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