[clang] [Clang][AMDGPU] Stop defaulting to `one-as` for all atomic scopes (PR #120095)

Pierre-vh wrote: > > Ah, that makes sense. It's surprising it wasn't like that in the first place > > But can we now get rid of the -one-as sync scopes and replace them with MMRAs? MMRAs are droppable so not currently suited to replace syncscopes like that, but it's a goal. As part of the Vul

[clang] [Clang][AMDGPU] Stop defaulting to `one-as` for all atomic scopes (PR #120095)

https://github.com/Pierre-vh approved this pull request. Ah, that makes sense. It's surprising it wasn't like that in the first place https://github.com/llvm/llvm-project/pull/120095 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists

[clang] [Clang][AMDGPU] Stop defaulting to `one-as` for all atomic scopes (PR #120095)

Pierre-vh wrote: I'm trying to understand this. Is the function being changed a generic util called by multiple builtins, and this change is just to make `one-as` exclusive to the OpenCL variant of those builtins ? Can an identical builtin have different behavior depending on the input languag

[clang] [libc] [llvm] [AMDGPU] Use COV6 by default (PR #118515)

Pierre-vh wrote: @shiltian Please also remove `warn_drv_amdgpu_cov6` - it's a warning I added while v6 was being worked on. Now that it's supported by the stack we can remove it. https://github.com/llvm/llvm-project/pull/118515 ___ cfe-commits mailing

[clang] [libc] [llvm] [AMDGPU] Implement variadic functions by IR lowering (PR #93362)

https://github.com/Pierre-vh approved this pull request. LGTM if a kill switch is added, I would wait a day more before landing in case anyone else has concerns https://github.com/llvm/llvm-project/pull/93362 ___ cfe-commits mailing list cfe-commits@l

[clang] [libc] [llvm] [AMDGPU] Implement variadic functions by IR lowering (PR #93362)

@@ -992,6 +993,8 @@ void AMDGPUPassConfig::addIRPasses() { if (isPassEnabled(EnableImageIntrinsicOptimizer)) addPass(createAMDGPUImageIntrinsicOptimizerPass(&TM)); + addPass(createExpandVariadicsPass(ExpandVariadicsMode::Lowering)); Pierre-vh wrote: Pl

[clang] [libc] [llvm] [AMDGPU] Implement variadic functions by IR lowering (PR #93362)

https://github.com/Pierre-vh edited https://github.com/llvm/llvm-project/pull/93362 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [libc] [llvm] [AMDGPU] Implement variadic functions by IR lowering (PR #93362)

@@ -0,0 +1,1037 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [libc] [llvm] [AMDGPU] Implement variadic functions by IR lowering (PR #93362)

@@ -0,0 +1,1037 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [libc] [llvm] [AMDGPU] Implement variadic functions by IR lowering (PR #93362)

@@ -0,0 +1,1037 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [libc] [llvm] [AMDGPU] Implement variadic functions by IR lowering (PR #93362)

@@ -0,0 +1,1037 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [libc] [llvm] [AMDGPU] Implement variadic functions by IR lowering (PR #93362)

@@ -0,0 +1,1037 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [libc] [llvm] [AMDGPU] Implement variadic functions by IR lowering (PR #93362)

@@ -0,0 +1,1037 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [libc] [llvm] [AMDGPU] Implement variadic functions by IR lowering (PR #93362)

@@ -0,0 +1,1037 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [libc] [llvm] [AMDGPU] Implement variadic functions by IR lowering (PR #93362)

@@ -0,0 +1,1037 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [libc] [llvm] [AMDGPU] Implement variadic functions by IR lowering (PR #93362)

@@ -0,0 +1,1037 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [libc] [llvm] [AMDGPU] Implement variadic functions by IR lowering (PR #93362)

@@ -0,0 +1,1037 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [libc] [llvm] [AMDGPU] Implement variadic functions by IR lowering (PR #93362)

@@ -0,0 +1,1037 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [libc] [llvm] [AMDGPU] Implement variadic functions by IR lowering (PR #93362)

@@ -0,0 +1,1037 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [libc] [llvm] [AMDGPU] Implement variadic functions by IR lowering (PR #93362)

@@ -0,0 +1,1037 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [libc] [llvm] [AMDGPU] Implement variadic functions by IR lowering (PR #93362)

@@ -0,0 +1,1037 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [libc] [llvm] [AMDGPU] Implement variadic functions by IR lowering (PR #93362)

@@ -0,0 +1,1037 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [libc] [llvm] [AMDGPU] Implement variadic functions by IR lowering (PR #93362)

@@ -0,0 +1,1037 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [libc] [llvm] [AMDGPU] Implement variadic functions by IR lowering (PR #93362)

@@ -0,0 +1,1037 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [libc] [llvm] [AMDGPU] Implement variadic functions by IR lowering (PR #93362)

@@ -0,0 +1,1037 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [llvm] AMDGPU: Add gfx12-generic target (PR #93875)

https://github.com/Pierre-vh approved this pull request. https://github.com/llvm/llvm-project/pull/93875 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AMDGPU] Add amdgpu-as MMRA for fences (PR #78572)

https://github.com/Pierre-vh closed https://github.com/llvm/llvm-project/pull/78572 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AMDGPU] Add amdgpu-as MMRA for fences (PR #78572)

Pierre-vh wrote: > > Then I guess the MMRA should just have "global" and "local" for now, we can > > always add more later if needed. What do you think? > > Yes, we don't have specific image counters. They are just vcmnt Diff has been updated with those changes https://github.com/llvm/llvm-pr

[clang] [llvm] [AMDGPU] Add amdgpu-as MMRA for fences (PR #78572)

Pierre-vh wrote: > > I thought image memory = private. It's unclear to me, what AS does OpenCL > > IMAGE memory map to in our backend? (But otherwise, yes, MMRA should just > > have the backend names, the mapping of the OpenCL IMAGE to a backend AS > > should be in the device-lib) > > Images

[clang] [llvm] [AMDGPU] Add amdgpu-as MMRA for fences (PR #78572)

Pierre-vh wrote: > > @arsenm Should we use `image` or `private`? We could allow both in the > > frontend, and only use `private` as the canonical MMRA. > > I don't understand why image would imply private. I would just keep at as > private throughout I thought image memory = private. It's unc

[clang] [llvm] [AMDGPU] Add amdgpu-as MMRA for fences (PR #78572)

Pierre-vh wrote: @arsenm Should we use `image` or `private`? We could allow both in the frontend, and only use `private` as the canonical MMRA. https://github.com/llvm/llvm-project/pull/78572 ___ cfe-commits mailing list cfe-commits@lists.llvm.org htt

[clang] [llvm] [AMDGPU] Add amdgpu-as MMRA for fences (PR #78572)

@@ -678,6 +680,54 @@ class SIMemoryLegalizer final : public MachineFunctionPass { bool runOnMachineFunction(MachineFunction &MF) override; }; +static std::array, 3> ASNames = {{ +{"global", SIAtomicAddrSpace::GLOBAL}, +{"local", SIAtomicAddrSpace::LDS}, +{"image

[clang] [llvm] [AMDGPU] Add amdgpu-as MMRA for fences (PR #78572)

@@ -4408,6 +4409,42 @@ Target-Specific Extensions Clang supports some language features conditionally on some targets. +AMDGPU Language Extensions +-- + +__builtin_amdgcn_fence +^^ + +``__builtin_amdgcn_fence`` emits a fence. + +* `

[clang] [llvm] [AMDGPU] Add amdgpu-as MMRA for fences (PR #78572)

@@ -4408,6 +4409,42 @@ Target-Specific Extensions Clang supports some language features conditionally on some targets. +AMDGPU Language Extensions +-- + +__builtin_amdgcn_fence +^^ + +``__builtin_amdgcn_fence`` emits a fence. + +* `

[clang] [llvm] [AMDGPU] Add amdgpu-as MMRA for fences (PR #78572)

@@ -18365,6 +18366,28 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, return nullptr; } +void CodeGenFunction::AddAMDGCNFenceAddressSpaceMMRA(llvm::Instruction *Inst, + const CallExpr *E) { + constexpr

[clang] [llvm] [AMDGPU] Add amdgpu-as MMRA for fences (PR #78572)

https://github.com/Pierre-vh edited https://github.com/llvm/llvm-project/pull/78572 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AMDGPU] Add amdgpu-as MMRA for fences (PR #78572)

https://github.com/Pierre-vh edited https://github.com/llvm/llvm-project/pull/78572 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AMDGPU] Add OpenCL-specific fence address space masks (PR #78572)

Pierre-vh wrote: I changed it so it's one or more string arguments: ``` __builtin_amdgcn_masked_fence(__ATOMIC_SEQ_CST, "workgroup", "local", "global") ``` I'm now wondering if adding a new builtin is needed at all, or if it should just be part of the original builtin? It's an additive change.

[clang] [llvm] [AMDGPU] Add OpenCL-specific fence address space masks (PR #78572)

@@ -69,6 +69,7 @@ BUILTIN(__builtin_amdgcn_iglp_opt, "vIi", "n") BUILTIN(__builtin_amdgcn_s_dcache_inv, "v", "n") BUILTIN(__builtin_amdgcn_buffer_wbinvl1, "v", "n") BUILTIN(__builtin_amdgcn_fence, "vUicC*", "n") +BUILTIN(__builtin_amdgcn_masked_fence, "vUiUicC*", "n") -

[clang] [llvm] [AMDGPU] Add OpenCL-specific fence address space masks (PR #78572)

@@ -18319,6 +18320,26 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, return nullptr; } +void CodeGenFunction::AddAMDGCNAddressSpaceMMRA(llvm::Instruction *Inst, +llvm::Value *ASMask) { + constexpr const ch

[clang] [llvm] [AMDGPU] Add OpenCL-specific fence address space masks (PR #78572)

https://github.com/Pierre-vh edited https://github.com/llvm/llvm-project/pull/78572 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AMDGPU] Add OpenCL-specific fence address space masks (PR #78572)

https://github.com/Pierre-vh edited https://github.com/llvm/llvm-project/pull/78572 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RFC][AMDGPU] Add OpenCL-specific fence address space masks (PR #78572)

@@ -18319,6 +18320,26 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, return nullptr; } +void CodeGenFunction::AddAMDGCNAddressSpaceMMRA(llvm::Instruction *Inst, +llvm::Value *ASMask) { + constexpr const ch

[clang] [clang][AMDGPU] Don't define feature macros on host code (PR #83558)

https://github.com/Pierre-vh closed https://github.com/llvm/llvm-project/pull/83558 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][AMDGPU] Don't define feature macros on host code (PR #83558)

Pierre-vh wrote: > This was the original behavior of my patch, but I reverted it because it > broke all the HIP headers that were unintentionally relying on this. Has that > been resolved? Was an issue opened for that? How many headers are affected? https://github.com/llvm/llvm-project/pull/8

[clang] [clang][AMDGPU] Don't define feature macros on host code (PR #83558)

https://github.com/Pierre-vh updated https://github.com/llvm/llvm-project/pull/83558 >From 3730631ac58425f559f4bc3cfe3da89e6367c1c5 Mon Sep 17 00:00:00 2001 From: pvanhout Date: Fri, 1 Mar 2024 12:43:55 +0100 Subject: [PATCH 1/2] [clang][AMDGPU] Don't define feature macros on host code Those m

[clang] [clang][AMDGPU] Don't define feature macros on host code (PR #83558)

https://github.com/Pierre-vh created https://github.com/llvm/llvm-project/pull/83558 Those macros are unreliable because our features are mostly uninitialized at that stage, so any macro we define is unreliable. Fixes SWDEV-447308 >From 3730631ac58425f559f4bc3cfe3da89e6367c1c5 Mon Sep 17 00:0

[clang] [llvm] [AMDGPU] Emit a waitcnt instruction after each memory instruction (PR #79236)

@@ -2326,6 +2326,20 @@ bool SIInsertWaitcnts::insertWaitcntInBlock(MachineFunction &MF, } #endif +if (ST->isPreciseMemoryEnabled()) { + AMDGPU::Waitcnt Wait; + if (WCG == &WCGPreGFX12) +Wait = AMDGPU::Waitcnt(0, 0, 0, 0); Pierre-vh w

[clang] [llvm] [AMDGPU] Emit a waitcnt instruction after each memory instruction (PR #79236)

@@ -2326,6 +2326,20 @@ bool SIInsertWaitcnts::insertWaitcntInBlock(MachineFunction &MF, } #endif +if (ST->isPreciseMemoryEnabled()) { + AMDGPU::Waitcnt Wait; + if (WCG == &WCGPreGFX12) Pierre-vh wrote: Use `ST->hasExtendedWaitCounts()` inst

[clang] [llvm] [AMDGPU] Emit a waitcnt instruction after each memory instruction (PR #79236)

@@ -2594,12 +2594,10 @@ bool SIMemoryLegalizer::expandAtomicCmpxchgOrRmw(const SIMemOpInfo &MOI, MOI.getOrdering() == AtomicOrdering::SequentiallyConsistent || MOI.getFailureOrdering() == AtomicOrdering::Acquire || MOI.getFailureOrdering() == AtomicOrde

[clang] [llvm] [AMDGPU] Emit a waitcnt instruction after each memory instruction (PR #79236)

https://github.com/Pierre-vh approved this pull request. LGTM, but wait for @t-tye or @jayfoad to approve as well https://github.com/llvm/llvm-project/pull/79236 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mai

[clang] [llvm] [AMDGPU] Add an option to disable unsafe uses of atomic xor (PR #69229)

Pierre-vh wrote: > Thanks for the comments @arsenm @yxsamliu @b-sumner. > > By approaching a similar solution, do you mean MMRAs (#78569) ? > > If so, should I rebase/adapt my patch to the MMRA PR? Or will this PR be > redundant and needs closing? > > @yxsamliu These concise names look good t

[clang] [llvm] [AMDGPU] Emit a waitcnt instruction after each memory instruction (PR #79236)

@@ -167,6 +167,10 @@ def FeatureCuMode : SubtargetFeature<"cumode", "Enable CU wavefront execution mode" >; +def FeaturePreciseMemory Pierre-vh wrote: Just remove `m_amdgpu_Features_Group` from your option's `SimpleMFlag`, follow the same pattern as `wavef

[clang] [llvm] [AMDGPU] Emit a waitcnt instruction after each memory instruction (PR #79236)

@@ -167,6 +167,10 @@ def FeatureCuMode : SubtargetFeature<"cumode", "Enable CU wavefront execution mode" >; +def FeaturePreciseMemory Pierre-vh wrote: It's only called once per run by the driver, yes We already do this for wavefrontsize64, and pretty much

[clang] [llvm] [AMDGPU] Emit a waitcnt instruction after each memory instruction (PR #79236)

@@ -167,6 +167,10 @@ def FeatureCuMode : SubtargetFeature<"cumode", "Enable CU wavefront execution mode" >; +def FeaturePreciseMemory Pierre-vh wrote: The extra overhead is just 3 lines in `clang/lib/Driver/ToolChains/AMDGPU.cpp`, it's negligible. We don't

[clang] [llvm] [AMDGPU] Emit a waitcnt instruction after each memory instruction (PR #79236)

@@ -355,6 +356,18 @@ class SICacheControl { MachineBasicBlock::iterator &MI) const { return false; } + +public: + // The following is for supporting precise memory mode. When the option + // amdgpu-precise-memory is enabled, an s_waitc

[clang] [llvm] [AMDGPU] Emit a waitcnt instruction after each memory instruction (PR #79236)

https://github.com/Pierre-vh edited https://github.com/llvm/llvm-project/pull/79236 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AMDGPU] Emit a waitcnt instruction after each memory instruction (PR #79236)

https://github.com/Pierre-vh requested changes to this pull request. Did you try to move this to SIInsertWaitCnt, as suggested? https://github.com/llvm/llvm-project/pull/79236 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.o

[clang] [llvm] [AMDGPU] Emit a waitcnt instruction after each memory instruction (PR #79236)

@@ -2378,6 +2456,221 @@ bool SIGfx12CacheControl::enableVolatileAndOrNonTemporal( return Changed; } +bool SIGfx6CacheControl ::handleNonAtomicForPreciseMemory( +MachineBasicBlock::iterator &MI) { + assert(MI->mayLoadOrStore()); + + MachineInstr &Inst = *MI; + AMDGPU:

[clang] [llvm] [AMDGPU] Emit a waitcnt instruction after each memory instruction (PR #79236)

@@ -2378,6 +2456,221 @@ bool SIGfx12CacheControl::enableVolatileAndOrNonTemporal( return Changed; } +bool SIGfx6CacheControl ::handleNonAtomicForPreciseMemory( +MachineBasicBlock::iterator &MI) { + assert(MI->mayLoadOrStore()); + + MachineInstr &Inst = *MI; + AMDGPU:

[clang] [llvm] [AMDGPU] Emit a waitcnt instruction after each memory instruction (PR #79236)

@@ -603,14 +626,69 @@ class SIGfx12CacheControl : public SIGfx11CacheControl { SIAtomicAddrSpace AddrSpace, SIMemOp Op, bool IsVolatile, bool IsNonTemporal) const o

[clang] [llvm] [AMDGPU] Emit a waitcnt instruction after each memory instruction (PR #79236)

@@ -603,14 +626,69 @@ class SIGfx12CacheControl : public SIGfx11CacheControl { SIAtomicAddrSpace AddrSpace, SIMemOp Op, bool IsVolatile, bool IsNonTemporal) const o

[clang] [llvm] [AMDGPU] Emit a waitcnt instruction after each memory instruction (PR #79236)

@@ -603,14 +626,69 @@ class SIGfx12CacheControl : public SIGfx11CacheControl { SIAtomicAddrSpace AddrSpace, SIMemOp Op, bool IsVolatile, bool IsNonTemporal) const o

[clang] [llvm] [AMDGPU] Emit a waitcnt instruction after each memory instruction (PR #79236)

@@ -167,6 +167,10 @@ def FeatureCuMode : SubtargetFeature<"cumode", "Enable CU wavefront execution mode" >; +def FeaturePreciseMemory Pierre-vh wrote: I think you just need to add something like this in `AMDGPU.cpp` in `getAMDGPUTargetFeatures` ``` if (A

[clang] [llvm] [AMDGPU] Emit a waitcnt instruction after each memory instruction (PR #79236)

https://github.com/Pierre-vh commented: I also agree with Jay, can't this go in InsertWaitCnt? Why does it have to go in SIMemoryLegalizer instead? If it has to stay here, fine, but is it possible to merge some code with SIInsertWaitCnt in a common helper somewhere? https://github.com/llvm/ll

[clang] [llvm] [AMDGPU] Emit a waitcnt instruction after each memory instruction (PR #79236)

https://github.com/Pierre-vh edited https://github.com/llvm/llvm-project/pull/79236 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AMDGPU] Replace '.' with '-' in generic target names (PR #81718)

https://github.com/Pierre-vh closed https://github.com/llvm/llvm-project/pull/81718 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][CodeGen] Loose the cast check when emitting builtins (PR #81669)

Pierre-vh wrote: > > Sorry, I should have clearly mentioned that. Yes, it is for my followup > > change #80908. In #80908, we changed the type of LLVM builtin but kept the > > corresponding clang builtin unchanged to avoid breaking existing uses. > > Don't see how that could be related; you ca

[clang] [llvm] [AMDGPU] Replace '.' with '-' in generic target names (PR #81718)

https://github.com/Pierre-vh created https://github.com/llvm/llvm-project/pull/81718 The dot is too confusing for tools. Output temporaries would have '10.3-generic' so tools could parse it as an extension, device libs & the associated clang driver logic are also confused by the dot. After di

[clang] [llvm] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

https://github.com/Pierre-vh closed https://github.com/llvm/llvm-project/pull/76955 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

Pierre-vh wrote: > mad_mix I added run lines to `mad-mix.ll` and it behaves as expected: no fma/mad_mix emitted https://github.com/llvm/llvm-project/pull/76955 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mai

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,698 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,701 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,701 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,701 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,701 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,701 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,698 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,701 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,701 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,701 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,701 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,701 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,701 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,701 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,701 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,701 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,701 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

https://github.com/Pierre-vh commented: My comments are mostly about style, I haven't done a deep dive into the logic of the pass yet https://github.com/llvm/llvm-project/pull/81058 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

https://github.com/Pierre-vh edited https://github.com/llvm/llvm-project/pull/81058 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

Pierre-vh wrote: @t-tye Can you please approve then? Otherwise the diff still shows a red "Changes requested" warning :) Thanks @arsenm Please also approve if there are no more comments https://github.com/llvm/llvm-project/pull/76955 ___ cfe-commits m

[clang] [llvm] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

https://github.com/Pierre-vh updated https://github.com/llvm/llvm-project/pull/76955 >From 616dda8bc9e000e4243ddb8f6b7f4b04f956a620 Mon Sep 17 00:00:00 2001 From: pvanhout Date: Thu, 4 Jan 2024 14:48:05 +0100 Subject: [PATCH 1/6] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets These gener

[clang] [llvm] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

@@ -520,6 +520,102 @@ Every processor supports every OS ABI (see :ref:`amdgpu-os`) with the following === === = = === === == +Generic processors allow execution of a single

[clang] [llvm] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

https://github.com/Pierre-vh updated https://github.com/llvm/llvm-project/pull/76955 >From 616dda8bc9e000e4243ddb8f6b7f4b04f956a620 Mon Sep 17 00:00:00 2001 From: pvanhout Date: Thu, 4 Jan 2024 14:48:05 +0100 Subject: [PATCH 1/5] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets These gener

[clang] [llvm] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

Pierre-vh wrote: For the MD changes, it's just to describe the version increment, nothing else. I think describing is important as the V6 diff already updated the amdhsa.version. If amdhsa.version didn't need to change then i need to fix that first, and then we can remove the V6 MD section ht

[llvm] [clang] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

https://github.com/Pierre-vh updated https://github.com/llvm/llvm-project/pull/76955 >From 616dda8bc9e000e4243ddb8f6b7f4b04f956a620 Mon Sep 17 00:00:00 2001 From: pvanhout Date: Thu, 4 Jan 2024 14:48:05 +0100 Subject: [PATCH 1/4] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets These gener

[llvm] [clang] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

https://github.com/Pierre-vh updated https://github.com/llvm/llvm-project/pull/76955 >From 616dda8bc9e000e4243ddb8f6b7f4b04f956a620 Mon Sep 17 00:00:00 2001 From: pvanhout Date: Thu, 4 Jan 2024 14:48:05 +0100 Subject: [PATCH 1/3] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets These gener

[clang] [llvm] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

https://github.com/Pierre-vh updated https://github.com/llvm/llvm-project/pull/76955 >From 616dda8bc9e000e4243ddb8f6b7f4b04f956a620 Mon Sep 17 00:00:00 2001 From: pvanhout Date: Thu, 4 Jan 2024 14:48:05 +0100 Subject: [PATCH 1/2] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets These gener

[clang] [llvm] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

Pierre-vh wrote: @arsenm do you have any concerns with this change? @t-tye is the documentation good? https://github.com/llvm/llvm-project/pull/76955 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinf

[clang] [llvm] [AMDGPU] Emit a waitcnt instruction after each memory instruction (PR #79236)

@@ -605,12 +606,197 @@ class SIGfx12CacheControl : public SIGfx11CacheControl { bool IsNonTemporal) const override; }; +class SIPreciseMemorySupport { +protected: + const GCNSubtarget &ST; + const SIInstrInfo *TII = nullptr; + + IsaVers

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