https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/149745
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@@ -0,0 +1,11 @@
+// RUN: %clang_cc1 %s -ffreestanding -triple=i686-unknown-unknown
-target-feature +sm3 -fsyntax-only -verify
+
+#include
+
+__m128i test_mm_sm3rnds2_epi32(__m128i __A, __m128i __B, __m128i __C) {
+ return _mm_sm3rnds2_epi32(__A, __B, __C, 256); // expected-er
https://github.com/phoebewang requested changes to this pull request.
Please check test failures.
https://github.com/llvm/llvm-project/pull/149745
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@@ -14,3 +14,7 @@ void test_m_prefetch_it1(void *p) {
// CHECK-LABEL: define{{.*}} void @test_m_prefetch_it1
// CHECK: call void @llvm.prefetch.p0(ptr {{.*}}, i32 0, i32 2, i32 0)
}
+
+void test_invalid_prefetchi(void* p) {
+ return __builtin_ia32_prefetchi(p, 1); // expec
https://github.com/phoebewang edited
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/149745
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phoebewang wrote:
Thanks for the patch! You can add a test case for it like
`clang/test/CodeGen/X86/sm3-error.c`
https://github.com/llvm/llvm-project/pull/149745
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@@ -176,10 +176,10 @@ constexpr FeatureBitset FeaturesArrowlakeS =
FeaturesArrowlake | FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 |
FeatureSM4;
constexpr FeatureBitset FeaturesPantherlake =
-FeaturesArrowlakeS | FeaturePREFETCHI;
+FeaturesArrowlakeS ^ Feat
@@ -1056,4 +1056,62 @@ void SemaX86::handleForceAlignArgPointerAttr(Decl *D,
const ParsedAttr &AL) {
X86ForceAlignArgPointerAttr(getASTContext(), AL));
}
+enum FirstParam { Unsupported, Duplicate, Unknown };
+enum SecondParam { None, CPU, Tune };
+enum ThirdP
phoebewang wrote:
> TBH I'm not sure if we need to add `avx512f,evex512` to intrinsics attributes
> and/or to `.td` as well.
Yes, we need them for now. Otherwise, we cannot allocate ZMM registers.
https://github.com/llvm/llvm-project/pull/148633
___
@@ -16,7 +16,15 @@
#define __DEFAULT_FN_ATTRS_AVX512
\
__attribute__((__always_inline__, __nodebug__,
\
- __target__("amx-avx512,avx10.2-512")))
+ __target__("amx-avx
https://github.com/phoebewang closed
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https://github.com/llvm/llvm-project/pull/148184
According to Intel [SDM088](https://cdrdv2.intel.com/v1/dl/getContent/671200)
Volume 1, Chapter 2.4, Key Locker will be removed from 2025 onwards products.
>From 9a8224c22535912a1fa95caa41f8fc2c3f7a76d0 Mon
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/144833
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>From 8e218d9c4431b021231942e514f175164af35a51 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Thu, 19 Jun 2025 12:14:54 +0800
Subject: [PATCH 1/2] [X86] Remove CLDEMOTE from Arrowlake and later hybrid
p
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/144833
Decouple Arrowlake from Sierraforest because the later has CLDEMOTE feature.
>From 8e218d9c4431b021231942e514f175164af35a51 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Thu, 19 Jun 2025 12:14:54 +0800
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/144662
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SDM doesn't list any hybrid processors in this feature. Besides, physical
machine also reports not supported.
>From 353fbfc93faa2c1bad26261b566d3f797b6d1a72 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Dat
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/141486
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https://github.com/phoebewang commented:
The pre-checkin failures seem related.
https://github.com/llvm/llvm-project/pull/138360
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@@ -138,6 +138,12 @@ let Attributes = [Const, NoThrow,
RequiredVectorWidth<256>], Features = "avx" in
}
}
+// PRFCHW
+let Features = "prfchw", Header = "intrin.h", Attributes = [NoThrow, Const] in
{
phoebewang wrote:
Although they are in the same file, bo
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/138360
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/136660
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@@ -0,0 +1,236 @@
+//===- X86SuppressAPXForReloc.cpp - Suppress APX features for relocations
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,236 @@
+//===- X86SuppressAPXForReloc.cpp - Suppress APX features for relocations
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,236 @@
+//===- X86SuppressAPXForReloc.cpp - Suppress APX features for relocations
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -254,11 +256,20 @@ static bool CompressEVEXImpl(MachineInstr &MI, const
X86Subtarget &ST) {
}
}
+ bool IsWithReloc = false;
+ if (X86EnableAPXForRelocation) {
+int MemOpNo = X86II::getMemoryOperandNo(MI.getDesc().TSFlags) +
+ X86II::getOperandB
phoebewang wrote:
> This solution can not handle post-RA optimizations. Could we implement it in
> MC stage for this workaround?
We cannot change the register after RA. I don't see any problem for now expect
NF optimizations, which we can skip them for now.
https://github.com/llvm/llvm-projec
@@ -127,6 +127,7 @@
; CHECK-NEXT: X86 LEA Optimize
; CHECK-NEXT: X86 Optimize Call Frame
; CHECK-NEXT: X86 Avoid Store Forwarding Block
+; CHECK-NEXT: X86 Suppress APX features for relocation
phoebewang wrote:
Ok, we don't need to move
@@ -242,8 +244,18 @@ static EFLAGSClobber getClobberType(const MachineInstr
&MI) {
MI.findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr);
if (!FlagDef)
return NoClobber;
- if (FlagDef->isDead() && X86::getNFVariant(MI.getOpcode()))
+
+ if (FlagDef->isDead() &&
https://github.com/phoebewang closed
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phoebewang wrote:
> > Any comments?
>
> Still not understand the requirement...
I'm confused by the test cases too. I understood the code as we replace the
EGPR or NDD instructions with non-APX ones, which meets my expection. But the
option and tests are in MC phase, which means instructions
@@ -0,0 +1,173 @@
+//===- X86SuppressAPXForReloc.cpp - Suppress APX features for relocations
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,173 @@
+//===- X86SuppressAPXForReloc.cpp - Suppress APX features for relocations
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,173 @@
+//===- X86SuppressAPXForReloc.cpp - Suppress APX features for relocations
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -1,44 +1,84 @@
// REQUIRES: x86
-// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o
+// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o
-x86-apx-relax-relocations=true
// RUN: ld.lld %t.o -o %t1
// RUN: llvm-readobj -r %t1 | FileCheck -
@@ -912,9 +912,9 @@ void X86_64::relocate(uint8_t *loc, const Relocation &rel,
uint64_t val) const {
case R_X86_64_CODE_4_GOTPC32_TLSDESC:
case R_X86_64_TLSDESC_CALL:
case R_X86_64_TLSGD:
-if (rel.expr == R_RELAX_TLS_GD_TO_LE) {
+if (rel.expr == R_RELAX_TLS_GD_TO
@@ -0,0 +1,173 @@
+//===- X86SuppressAPXForReloc.cpp - Suppress APX features for relocations
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -89,6 +89,7 @@ set(sources
GISel/X86InstructionSelector.cpp
GISel/X86LegalizerInfo.cpp
GISel/X86RegisterBankInfo.cpp
+ X86SuppressAPXForReloc.cpp
phoebewang wrote:
Put it in alphabetic order?
https://github.com/llvm/llvm-project/pull/136660
@@ -912,9 +912,9 @@ void X86_64::relocate(uint8_t *loc, const Relocation &rel,
uint64_t val) const {
case R_X86_64_CODE_4_GOTPC32_TLSDESC:
case R_X86_64_TLSDESC_CALL:
case R_X86_64_TLSGD:
-if (rel.expr == R_RELAX_TLS_GD_TO_LE) {
+if (rel.expr == R_RELAX_TLS_GD_TO
@@ -1,44 +1,84 @@
// REQUIRES: x86
-// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o
+// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o
-x86-apx-relax-relocations=true
// RUN: ld.lld %t.o -o %t1
// RUN: llvm-readobj -r %t1 | FileCheck -
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/135489
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phoebewang wrote:
/cherry-pick
https://github.com/llvm/llvm-project/commit/ebba554a3211b0b98d3ae33ba70f9d6ceaab6ad4
https://github.com/llvm/llvm-project/pull/135489
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https://github.com/llvm/llvm-project/pull/135489
According to SDM, they require both VAES/VPCLMULQDQ and AVX10.1 CPUID bits.
Fixes: #135394
>From f6c06c613a8b862307e643edb8f010cf2f666350 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Sat, 12 Apr 2025
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/134528
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None
>From 04852072c016e6df3c9b6d834ba34c443593aa04 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Sun, 6 Apr 2025 18:22:22 +0800
Subject: [PATCH] [X86][AVX10] Make warning message more informative, NFC
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/131592
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https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/132397
Ref: https://cdrdv2.intel.com/v1/dl/getContent/784343
>From a8353b285f99b57a3d4ce28add512debc8761d5a Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Fri, 21 Mar 2025 20:54:06 +0800
Subject: [PATCH] [X86]
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/132414
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https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/134484
Found by #64779.
>From b04e443d3569ec2ed352e127bf6fbfe0902b1ee1 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Sat, 5 Apr 2025 15:03:17 +0800
Subject: [PATCH] [X86][AMX] Add missing __inline__ for AMXCO
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/132397
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phoebewang wrote:
> are we missing clang codegen tests for these?
No, we don't generate these intrinsics. They will be transformed to llvm.fma
ones.
https://github.com/llvm/llvm-project/pull/134240
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None
>From cf4be7b5e130593f54752066b1ab569da9cc12fa Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Thu, 3 Apr 2025 20:23:08 +0800
Subject: [PATCH] [X86][AVX10.2] Replace nepbh with bf16 to match with ot
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/132542
>From 9a8d9b7d5d3f07685579c3d1336e146755bb7efa Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Sat, 22 Mar 2025 19:15:01 +0800
Subject: [PATCH 1/3] [X86][AVX10] Re-target mavx10.1 and emit warning for
ma
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/132542
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phoebewang wrote:
> LGTM - but we need to add a full explanation to the clang/llvm release notes
> explaining the avx10 changes/deprecations (and future removal).
Good reminder! Done.
https://github.com/llvm/llvm-project/pull/132542
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phoebewang wrote:
Ping?
https://github.com/llvm/llvm-project/pull/132542
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https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/132542
>From 9a8d9b7d5d3f07685579c3d1336e146755bb7efa Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Sat, 22 Mar 2025 19:15:01 +0800
Subject: [PATCH 1/2] [X86][AVX10] Re-target mavx10.1 and emit warning for
ma
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/132542
The 256-bit maximum vector register size control was removed from AVX10
whitepaper, ref: https://cdrdv2.intel.com/v1/dl/getContent/784343
- Re-target m[no-]avx10.1 to enable AVX10.1 with 512-bit maximum vect
phoebewang wrote:
> LGTM. Clang format changes look valid.
I think the `(__mmask8) - 1` doesn't make sense. Seems clang-format takes
`__mmask8` as a variable rather than a type. It appares since some version and
really annoying.
https://github.com/llvm/llvm-project/pull/132426
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https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/132414
Ref: https://cdrdv2.intel.com/v1/dl/getContent/784343
>From 096e0b112724176f3d4893657580588a021d2224 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Fri, 21 Mar 2025 23:53:15 +0800
Subject: [PATCH] [X86]
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/132405
>From 4da792e1397d893b4be997039d24cf933d9702b9 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Fri, 21 Mar 2025 22:42:10 +0800
Subject: [PATCH 1/2] [X86][AVX10.2] Remove YMM rounding from VMINMAXP[H,S,D]
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/132405
Ref: https://cdrdv2.intel.com/v1/dl/getContent/784343
>From 4da792e1397d893b4be997039d24cf933d9702b9 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Fri, 21 Mar 2025 22:42:10 +0800
Subject: [PATCH] [X86]
phoebewang wrote:
> LGTM - do we have to remove avx10-256 as well (and just use prefer vector
> width) or will that remain in some form?
Yes, we will remove avx10-256 and evex512 finally.
https://github.com/llvm/llvm-project/pull/132362
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phoebewang wrote:
> should be cvts_biasph_hf8 :)
Good catch! Proves moving the s ahead is wisdom :)
https://github.com/llvm/llvm-project/pull/131592
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phoebewang wrote:
> > > > Went through the patch with my eyes, I'm not sure how useful it was but
> > > > wasn't able to spot anything.
> > > > > Here is GCC patch:
> > > > > https://gcc.gnu.org/pipermail/gcc-patches/2025-March/678227.html
> > > >
> > > >
> > > > I haven't found any changes r
phoebewang wrote:
> Went through the patch with my eyes, I'm not sure how useful it was but
> wasn't able to spot anything.
>
> > Here is GCC patch:
> > https://gcc.gnu.org/pipermail/gcc-patches/2025-March/678227.html
>
> I haven't found any changes regarding `vcvt2ph2` and no other similar
phoebewang wrote:
Here is GCC patch:
https://gcc.gnu.org/pipermail/gcc-patches/2025-March/678227.html
https://github.com/llvm/llvm-project/pull/131592
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@@ -880,11 +880,11 @@ _mm_sll_si64(__m64 __m, __m64 __count)
///A 32-bit integer value.
/// \returns A 64-bit integer vector containing the left-shifted value. If
/// \a __count is greater or equal to 64, the result is set to 0.
-static __inline__ __m64 __DEFAULT_FN_ATT
@@ -880,11 +880,11 @@ _mm_sll_si64(__m64 __m, __m64 __count)
///A 32-bit integer value.
/// \returns A 64-bit integer vector containing the left-shifted value. If
/// \a __count is greater or equal to 64, the result is set to 0.
-static __inline__ __m64 __DEFAULT_FN_ATT
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/120766
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https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/128284
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https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/128284
>From eef9ec3ca38a2ba1dd12c8a8f8bfcacf38ab7926 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Sat, 22 Feb 2025 12:20:09 +0800
Subject: [PATCH 1/2] [X86] Allow using the lzcnt intrinsics for non-LZCNT
ta
@@ -1,5 +1,5 @@
-// RUN: %clang_cc1 -x c -ffreestanding %s -triple=x86_64-apple-darwin
-target-feature +lzcnt -emit-llvm -o - | FileCheck %s
-// RUN: %clang_cc1 -x c++ -std=c++11 -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +lzcnt -emit-llvm -o - | FileCheck
%s
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/126952
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https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/128284
Similar to D14748, we can relax lzcnt intrinsics too, especially with improved
BSR lowering by #123623
>From eef9ec3ca38a2ba1dd12c8a8f8bfcacf38ab7926 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Sat,
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/127385
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https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/127385
Address the X86 part of #126491
>From 80e85d3a44657df64fd9136156d36b096003b58e Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Sun, 16 Feb 2025 18:17:39 +0800
Subject: [PATCH] [X86] Add missing explicit
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/127331
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phoebewang wrote:
Please update test in clang\test\Headers\cpuid.c
https://github.com/llvm/llvm-project/pull/127331
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https://github.com/phoebewang milestoned
https://github.com/llvm/llvm-project/pull/126627
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phoebewang wrote:
/cherry-pick af522c5dd3a38cc5e11e8e62009d7dbe2cde2d86
https://github.com/llvm/llvm-project/pull/126627
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https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/126627
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https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/126390
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phoebewang wrote:
> ⚠️ C/C++ code formatter, clang-format found issues in your code. ⚠️
>
> You can test this locally with the following command:
> View the diff from clang-format here.
> ```diff
> diff --git a/clang/lib/Headers/avx10_2convertintrin.h
> b/clang/lib/Headers/avx10_2convertintrin.
https://github.com/phoebewang approved this pull request.
Good catch!
https://github.com/llvm/llvm-project/pull/126390
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https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/121070
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phoebewang wrote:
> @lvwr @maurer @rcvalle A gentle reminder to please review this PR.
@scottconstable You don't need explicit approvals from all reviewers. Let's
wait for 24 hours and land it if no objections.
https://github.com/llvm/llvm-project/pull/121070
__
phoebewang wrote:
> I proposed this at one point, and someone from Intel assured me that these
> long repetitive instructions and intrinsics are hand-maintained. It must be
> true at some level.
I believe it's not me, though I don't like the changes at the beginning either.
Anyway, with @chan
@@ -138,6 +142,12 @@ let Attributes = [Const, NoThrow,
RequiredVectorWidth<256>], Features = "avx" in
}
}
+// PRFCHW
+let Features = "prfchw", Header = "x86intrin.h", Attributes = [NoThrow, Const]
in {
+ def _m_prefetch : X86LibBuiltin<"void(void *)">;
ph
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/121070
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