https://github.com/phoebewang updated https://github.com/llvm/llvm-project/pull/132405
>From 4da792e1397d893b4be997039d24cf933d9702b9 Mon Sep 17 00:00:00 2001 From: "Wang, Phoebe" <phoebe.w...@intel.com> Date: Fri, 21 Mar 2025 22:42:10 +0800 Subject: [PATCH 1/2] [X86][AVX10.2] Remove YMM rounding from VMINMAXP[H,S,D] Ref: https://cdrdv2.intel.com/v1/dl/getContent/784343 --- clang/include/clang/Basic/BuiltinsX86.td | 6 +- clang/lib/Headers/avx10_2minmaxintrin.h | 81 +++--------- clang/lib/Sema/SemaX86.cpp | 9 +- .../CodeGen/X86/avx10_2_512minmax-error.c | 11 -- .../test/CodeGen/X86/avx10_2minmax-builtins.c | 72 ++--------- llvm/include/llvm/IR/IntrinsicsX86.td | 16 +-- llvm/lib/Target/X86/X86InstrAVX10.td | 11 +- llvm/lib/Target/X86/X86IntrinsicsInfo.h | 12 +- .../CodeGen/X86/avx10_2minmax-intrinsics.ll | 122 +++--------------- .../MC/Disassembler/X86/avx10.2minmax-32.txt | 24 ---- .../MC/Disassembler/X86/avx10.2minmax-64.txt | 24 ---- llvm/test/MC/X86/avx10.2minmax-32-att.s | 24 ---- llvm/test/MC/X86/avx10.2minmax-32-intel.s | 24 ---- llvm/test/MC/X86/avx10.2minmax-64-att.s | 24 ---- llvm/test/MC/X86/avx10.2minmax-64-intel.s | 24 ---- 15 files changed, 63 insertions(+), 421 deletions(-) diff --git a/clang/include/clang/Basic/BuiltinsX86.td b/clang/include/clang/Basic/BuiltinsX86.td index ea0d6df4a33c2..adb174a9fc62d 100644 --- a/clang/include/clang/Basic/BuiltinsX86.td +++ b/clang/include/clang/Basic/BuiltinsX86.td @@ -4823,7 +4823,7 @@ let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] i } let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { - def vminmaxpd256_round_mask : X86Builtin<"_Vector<4, double>(_Vector<4, double>, _Vector<4, double>, _Constant int, _Vector<4, double>, unsigned char, _Constant int)">; + def vminmaxpd256_mask : X86Builtin<"_Vector<4, double>(_Vector<4, double>, _Vector<4, double>, _Constant int, _Vector<4, double>, unsigned char)">; } let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { @@ -4835,7 +4835,7 @@ let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] i } let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { - def vminmaxph256_round_mask : X86Builtin<"_Vector<16, _Float16>(_Vector<16, _Float16>, _Vector<16, _Float16>, _Constant int, _Vector<16, _Float16>, unsigned short, _Constant int)">; + def vminmaxph256_mask : X86Builtin<"_Vector<16, _Float16>(_Vector<16, _Float16>, _Vector<16, _Float16>, _Constant int, _Vector<16, _Float16>, unsigned short)">; } let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { @@ -4847,7 +4847,7 @@ let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] i } let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { - def vminmaxps256_round_mask : X86Builtin<"_Vector<8, float>(_Vector<8, float>, _Vector<8, float>, _Constant int, _Vector<8, float>, unsigned char, _Constant int)">; + def vminmaxps256_mask : X86Builtin<"_Vector<8, float>(_Vector<8, float>, _Vector<8, float>, _Constant int, _Vector<8, float>, unsigned char)">; } let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { diff --git a/clang/lib/Headers/avx10_2minmaxintrin.h b/clang/lib/Headers/avx10_2minmaxintrin.h index 8164d49d89f1f..809a01b04f13e 100644 --- a/clang/lib/Headers/avx10_2minmaxintrin.h +++ b/clang/lib/Headers/avx10_2minmaxintrin.h @@ -66,34 +66,19 @@ (__v2df)_mm_setzero_pd(), (__mmask8)(U))) #define _mm256_minmax_pd(A, B, C) \ - ((__m256d)__builtin_ia32_vminmaxpd256_round_mask( \ + ((__m256d)__builtin_ia32_vminmaxpd256_mask( \ (__v4df)(__m256d)(A), (__v4df)(__m256d)(B), (int)(C), \ - (__v4df)_mm256_setzero_pd(), (__mmask8)-1, _MM_FROUND_NO_EXC)) + (__v4df)_mm256_setzero_pd(), (__mmask8)-1)) #define _mm256_mask_minmax_pd(W, U, A, B, C) \ - ((__m256d)__builtin_ia32_vminmaxpd256_round_mask( \ + ((__m256d)__builtin_ia32_vminmaxpd256_mask( \ (__v4df)(__m256d)(A), (__v4df)(__m256d)(B), (int)(C), \ - (__v4df)(__m256d)(W), (__mmask8)(U), _MM_FROUND_NO_EXC)) + (__v4df)(__m256d)(W), (__mmask8)(U))) #define _mm256_maskz_minmax_pd(U, A, B, C) \ - ((__m256d)__builtin_ia32_vminmaxpd256_round_mask( \ + ((__m256d)__builtin_ia32_vminmaxpd256_mask( \ (__v4df)(__m256d)(A), (__v4df)(__m256d)(B), (int)(C), \ - (__v4df)_mm256_setzero_pd(), (__mmask8)(U), _MM_FROUND_NO_EXC)) - -#define _mm256_minmax_round_pd(A, B, C, R) \ - ((__m256d)__builtin_ia32_vminmaxpd256_round_mask( \ - (__v4df)(__m256d)(A), (__v4df)(__m256d)(B), (int)(C), \ - (__v4df)_mm256_undefined_pd(), (__mmask8)-1, (int)(R))) - -#define _mm256_mask_minmax_round_pd(W, U, A, B, C, R) \ - ((__m256d)__builtin_ia32_vminmaxpd256_round_mask( \ - (__v4df)(__m256d)(A), (__v4df)(__m256d)(B), (int)(C), \ - (__v4df)(__m256d)(W), (__mmask8)(U), (int)(R))) - -#define _mm256_maskz_minmax_round_pd(U, A, B, C, R) \ - ((__m256d)__builtin_ia32_vminmaxpd256_round_mask( \ - (__v4df)(__m256d)(A), (__v4df)(__m256d)(B), (int)(C), \ - (__v4df)_mm256_setzero_pd(), (__mmask8)(U), (int)(R))) + (__v4df)_mm256_setzero_pd(), (__mmask8)(U))) #define _mm_minmax_ph(A, B, C) \ ((__m128h)__builtin_ia32_vminmaxph128_mask( \ @@ -111,34 +96,19 @@ (__v8hf)_mm_setzero_ph(), (__mmask8)(U))) #define _mm256_minmax_ph(A, B, C) \ - ((__m256h)__builtin_ia32_vminmaxph256_round_mask( \ + ((__m256h)__builtin_ia32_vminmaxph256_mask( \ (__v16hf)(__m256h)(A), (__v16hf)(__m256h)(B), (int)(C), \ - (__v16hf)_mm256_setzero_ph(), (__mmask16)-1, _MM_FROUND_NO_EXC)) + (__v16hf)_mm256_setzero_ph(), (__mmask16)-1)) #define _mm256_mask_minmax_ph(W, U, A, B, C) \ - ((__m256h)__builtin_ia32_vminmaxph256_round_mask( \ + ((__m256h)__builtin_ia32_vminmaxph256_mask( \ (__v16hf)(__m256h)(A), (__v16hf)(__m256h)(B), (int)(C), \ - (__v16hf)(__m256h)(W), (__mmask16)(U), _MM_FROUND_NO_EXC)) + (__v16hf)(__m256h)(W), (__mmask16)(U))) #define _mm256_maskz_minmax_ph(U, A, B, C) \ - ((__m256h)__builtin_ia32_vminmaxph256_round_mask( \ - (__v16hf)(__m256h)(A), (__v16hf)(__m256h)(B), (int)(C), \ - (__v16hf)_mm256_setzero_ph(), (__mmask16)(U), _MM_FROUND_NO_EXC)) - -#define _mm256_minmax_round_ph(A, B, C, R) \ - ((__m256h)__builtin_ia32_vminmaxph256_round_mask( \ + ((__m256h)__builtin_ia32_vminmaxph256_mask( \ (__v16hf)(__m256h)(A), (__v16hf)(__m256h)(B), (int)(C), \ - (__v16hf)_mm256_undefined_ph(), (__mmask16)-1, (int)(R))) - -#define _mm256_mask_minmax_round_ph(W, U, A, B, C, R) \ - ((__m256h)__builtin_ia32_vminmaxph256_round_mask( \ - (__v16hf)(__m256h)(A), (__v16hf)(__m256h)(B), (C), \ - (__v16hf)(__m256h)(W), (__mmask16)(U), (int)(R))) - -#define _mm256_maskz_minmax_round_ph(U, A, B, C, R) \ - ((__m256h)__builtin_ia32_vminmaxph256_round_mask( \ - (__v16hf)(__m256h)(A), (__v16hf)(__m256h)(B), (int)(C), \ - (__v16hf)_mm256_setzero_ph(), (__mmask16)(U), (int)(R))) + (__v16hf)_mm256_setzero_ph(), (__mmask16)(U))) #define _mm_minmax_ps(A, B, C) \ ((__m128)__builtin_ia32_vminmaxps128_mask( \ @@ -156,34 +126,19 @@ (__v4sf)_mm_setzero_ps(), (__mmask8)(U))) #define _mm256_minmax_ps(A, B, C) \ - ((__m256)__builtin_ia32_vminmaxps256_round_mask( \ + ((__m256)__builtin_ia32_vminmaxps256_mask( \ (__v8sf)(__m256)(A), (__v8sf)(__m256)(B), (int)(C), \ - (__v8sf)_mm256_setzero_ps(), (__mmask8)-1, _MM_FROUND_NO_EXC)) + (__v8sf)_mm256_setzero_ps(), (__mmask8)-1)) #define _mm256_mask_minmax_ps(W, U, A, B, C) \ - ((__m256)__builtin_ia32_vminmaxps256_round_mask( \ + ((__m256)__builtin_ia32_vminmaxps256_mask( \ (__v8sf)(__m256)(A), (__v8sf)(__m256)(B), (int)(C), (__v8sf)(__m256)(W), \ - (__mmask8)(U), _MM_FROUND_NO_EXC)) + (__mmask8)(U))) #define _mm256_maskz_minmax_ps(U, A, B, C) \ - ((__m256)__builtin_ia32_vminmaxps256_round_mask( \ - (__v8sf)(__m256)(A), (__v8sf)(__m256)(B), (int)(C), \ - (__v8sf)_mm256_setzero_ps(), (__mmask8)(U), _MM_FROUND_NO_EXC)) - -#define _mm256_minmax_round_ps(A, B, C, R) \ - ((__m256)__builtin_ia32_vminmaxps256_round_mask( \ - (__v8sf)(__m256)(A), (__v8sf)(__m256)(B), (int)(C), \ - (__v8sf)_mm256_undefined_ps(), (__mmask8)-1, (int)(R))) - -#define _mm256_mask_minmax_round_ps(W, U, A, B, C, R) \ - ((__m256)__builtin_ia32_vminmaxps256_round_mask( \ - (__v8sf)(__m256)(A), (__v8sf)(__m256)(B), (int)(C), (__v8sf)(__m256)(W), \ - (__mmask8)(U), (int)(R))) - -#define _mm256_maskz_minmax_round_ps(U, A, B, C, R) \ - ((__m256)__builtin_ia32_vminmaxps256_round_mask( \ + ((__m256)__builtin_ia32_vminmaxps256_mask( \ (__v8sf)(__m256)(A), (__v8sf)(__m256)(B), (int)(C), \ - (__v8sf)_mm256_setzero_ps(), (__mmask8)(U), (int)(R))) + (__v8sf)_mm256_setzero_ps(), (__mmask8)(U))) #define _mm_minmax_sd(A, B, C) \ ((__m128d)__builtin_ia32_vminmaxsd_round_mask( \ diff --git a/clang/lib/Sema/SemaX86.cpp b/clang/lib/Sema/SemaX86.cpp index e54a278225f1c..27454e2f03b5a 100644 --- a/clang/lib/Sema/SemaX86.cpp +++ b/clang/lib/Sema/SemaX86.cpp @@ -147,9 +147,6 @@ bool SemaX86::CheckBuiltinRoundingOrSAE(unsigned BuiltinID, CallExpr *TheCall) { case X86::BI__builtin_ia32_rndscalesd_round_mask: case X86::BI__builtin_ia32_rndscaless_round_mask: case X86::BI__builtin_ia32_rndscalesh_round_mask: - case X86::BI__builtin_ia32_vminmaxpd256_round_mask: - case X86::BI__builtin_ia32_vminmaxps256_round_mask: - case X86::BI__builtin_ia32_vminmaxph256_round_mask: case X86::BI__builtin_ia32_vminmaxpd512_round_mask: case X86::BI__builtin_ia32_vminmaxps512_round_mask: case X86::BI__builtin_ia32_vminmaxph512_round_mask: @@ -910,11 +907,11 @@ bool SemaX86::CheckBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID, case X86::BI__builtin_ia32_vminmaxbf16256: case X86::BI__builtin_ia32_vminmaxbf16512: case X86::BI__builtin_ia32_vminmaxpd128_mask: - case X86::BI__builtin_ia32_vminmaxpd256_round_mask: + case X86::BI__builtin_ia32_vminmaxpd256_mask: case X86::BI__builtin_ia32_vminmaxph128_mask: - case X86::BI__builtin_ia32_vminmaxph256_round_mask: + case X86::BI__builtin_ia32_vminmaxph256_mask: case X86::BI__builtin_ia32_vminmaxps128_mask: - case X86::BI__builtin_ia32_vminmaxps256_round_mask: + case X86::BI__builtin_ia32_vminmaxps256_mask: case X86::BI__builtin_ia32_vminmaxpd512_round_mask: case X86::BI__builtin_ia32_vminmaxps512_round_mask: case X86::BI__builtin_ia32_vminmaxph512_round_mask: diff --git a/clang/test/CodeGen/X86/avx10_2_512minmax-error.c b/clang/test/CodeGen/X86/avx10_2_512minmax-error.c index 6db7801eb0040..2ee496d317a5a 100644 --- a/clang/test/CodeGen/X86/avx10_2_512minmax-error.c +++ b/clang/test/CodeGen/X86/avx10_2_512minmax-error.c @@ -113,17 +113,6 @@ __m512 test_mm512_minmax_round_ps(__m512 __A, __m512 __B) { return _mm512_minmax_round_ps(__A, __B, 127, 11); // expected-error {{invalid rounding argument}} } -__m256d test_mm256_minmax_round_pd(__m256d __A, __m256d __B) { - return _mm256_minmax_round_pd(__A, __B, 127, 11); // expected-error {{invalid rounding argument}} -} - -__m256h test_mm256_minmax_round_ph(__m256h __A, __m256h __B) { - return _mm256_minmax_round_ph(__A, __B, 127, 11); // expected-error {{invalid rounding argument}} -} - -__m256 test_mm256_minmax_round_ps(__m256 __A, __m256 __B) { - return _mm256_minmax_round_ps(__A, __B, 127, 11); // expected-error {{invalid rounding argument}} -} __m128d test_mm_minmax_round_sd(__m128d __A, __m128d __B) { return _mm_minmax_round_sd(__A, __B, 127, 11); // expected-error {{invalid rounding argument}} } diff --git a/clang/test/CodeGen/X86/avx10_2minmax-builtins.c b/clang/test/CodeGen/X86/avx10_2minmax-builtins.c index 7e21858c71834..7dad153a15c37 100644 --- a/clang/test/CodeGen/X86/avx10_2minmax-builtins.c +++ b/clang/test/CodeGen/X86/avx10_2minmax-builtins.c @@ -67,40 +67,22 @@ __m128d test_mm_maskz_minmax_pd(__mmask8 __A, __m128d __B, __m128d __C) { __m256d test_mm256_minmax_pd(__m256d __A, __m256d __B) { // CHECK-LABEL: @test_mm256_minmax_pd( - // CHECK: call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256.round( + // CHECK: call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256( return _mm256_minmax_pd(__A, __B, 127); } __m256d test_mm256_mask_minmax_pd(__m256d __A, __mmask8 __B, __m256d __C, __m256d __D) { // CHECK-LABEL: @test_mm256_mask_minmax_pd( - // CHECK: call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256.round( + // CHECK: call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256( return _mm256_mask_minmax_pd(__A, __B, __C, __D, 127); } __m256d test_mm256_maskz_minmax_pd(__mmask8 __A, __m256d __B, __m256d __C) { // CHECK-LABEL: @test_mm256_maskz_minmax_pd( - // CHECK: call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256.round( + // CHECK: call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256( return _mm256_maskz_minmax_pd(__A, __B, __C, 127); } -__m256d test_mm256_minmax_round_pd(__m256d __A, __m256d __B) { - // CHECK-LABEL: @test_mm256_minmax_round_pd( - // CHECK: call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256.round( - return _mm256_minmax_round_pd(__A, __B, 127, _MM_FROUND_NO_EXC); -} - -__m256d test_mm256_mask_minmax_round_pd(__m256d __A, __mmask8 __B, __m256d __C, __m256d __D) { - // CHECK-LABEL: @test_mm256_mask_minmax_round_pd( - // CHECK: call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256.round( - return _mm256_mask_minmax_round_pd(__A, __B, __C, __D, 127, _MM_FROUND_NO_EXC); -} - -__m256d test_mm256_maskz_minmax_round_pd(__mmask8 __A, __m256d __B, __m256d __C) { - // CHECK-LABEL: @test_mm256_maskz_minmax_round_pd( - // CHECK: call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256.round( - return _mm256_maskz_minmax_round_pd(__A, __B, __C, 127, _MM_FROUND_NO_EXC); -} - __m128h test_mm_minmax_ph(__m128h __A, __m128h __B) { // CHECK-LABEL: @test_mm_minmax_ph( // CHECK: call <8 x half> @llvm.x86.avx10.mask.vminmaxph128( @@ -121,40 +103,22 @@ __m128h test_mm_maskz_minmax_ph(__mmask8 __A, __m128h __B, __m128h __C) { __m256h test_mm256_minmax_ph(__m256h __A, __m256h __B) { // CHECK-LABEL: @test_mm256_minmax_ph( - // CHECK: call <16 x half> @llvm.x86.avx10.mask.vminmaxph256.round( + // CHECK: call <16 x half> @llvm.x86.avx10.mask.vminmaxph256( return _mm256_minmax_ph(__A, __B, 127); } __m256h test_mm256_mask_minmax_ph(__m256h __A, __mmask16 __B, __m256h __C, __m256h __D) { // CHECK-LABEL: @test_mm256_mask_minmax_ph( - // CHECK: call <16 x half> @llvm.x86.avx10.mask.vminmaxph256.round( + // CHECK: call <16 x half> @llvm.x86.avx10.mask.vminmaxph256( return _mm256_mask_minmax_ph(__A, __B, __C, __D, 127); } __m256h test_mm256_maskz_minmax_ph(__mmask16 __A, __m256h __B, __m256h __C) { // CHECK-LABEL: @test_mm256_maskz_minmax_ph( - // CHECK: call <16 x half> @llvm.x86.avx10.mask.vminmaxph256.round( + // CHECK: call <16 x half> @llvm.x86.avx10.mask.vminmaxph256( return _mm256_maskz_minmax_ph(__A, __B, __C, 127); } -__m256h test_mm256_minmax_round_ph(__m256h __A, __m256h __B) { - // CHECK-LABEL: @test_mm256_minmax_round_ph( - // CHECK: call <16 x half> @llvm.x86.avx10.mask.vminmaxph256.round( - return _mm256_minmax_round_ph(__A, __B, 127, _MM_FROUND_NO_EXC); -} - -__m256h test_mm256_mask_minmax_round_ph(__m256h __A, __mmask16 __B, __m256h __C, __m256h __D) { - // CHECK-LABEL: @test_mm256_mask_minmax_round_ph( - // CHECK: call <16 x half> @llvm.x86.avx10.mask.vminmaxph256.round( - return _mm256_mask_minmax_round_ph(__A, __B, __C, __D, 127, _MM_FROUND_NO_EXC); -} - -__m256h test_mm256_maskz_minmax_round_ph(__mmask16 __A, __m256h __B, __m256h __C) { - // CHECK-LABEL: @test_mm256_maskz_minmax_round_ph( - // CHECK: call <16 x half> @llvm.x86.avx10.mask.vminmaxph256.round( - return _mm256_maskz_minmax_round_ph(__A, __B, __C, 127, _MM_FROUND_NO_EXC); -} - __m128 test_mm_minmax_ps(__m128 __A, __m128 __B) { // CHECK-LABEL: @test_mm_minmax_ps( // CHECK: call <4 x float> @llvm.x86.avx10.mask.vminmaxps128( @@ -175,40 +139,22 @@ __m128 test_mm_maskz_minmax_ps(__mmask8 __A, __m128 __B, __m128 __C) { __m256 test_mm256_minmax_ps(__m256 __A, __m256 __B) { // CHECK-LABEL: @test_mm256_minmax_ps( - // CHECK: call <8 x float> @llvm.x86.avx10.mask.vminmaxps256.round( + // CHECK: call <8 x float> @llvm.x86.avx10.mask.vminmaxps256( return _mm256_minmax_ps(__A, __B, 127); } __m256 test_mm256_mask_minmax_ps(__m256 __A, __mmask8 __B, __m256 __C, __m256 __D) { // CHECK-LABEL: @test_mm256_mask_minmax_ps( - // CHECK: call <8 x float> @llvm.x86.avx10.mask.vminmaxps256.round( + // CHECK: call <8 x float> @llvm.x86.avx10.mask.vminmaxps256( return _mm256_mask_minmax_ps(__A, __B, __C, __D, 127); } __m256 test_mm256_maskz_minmax_ps(__mmask8 __A, __m256 __B, __m256 __C) { // CHECK-LABEL: @test_mm256_maskz_minmax_ps( - // CHECK: call <8 x float> @llvm.x86.avx10.mask.vminmaxps256.round( + // CHECK: call <8 x float> @llvm.x86.avx10.mask.vminmaxps256( return _mm256_maskz_minmax_ps(__A, __B, __C, 127); } -__m256 test_mm256_minmax_round_ps(__m256 __A, __m256 __B) { - // CHECK-LABEL: @test_mm256_minmax_round_ps( - // CHECK: call <8 x float> @llvm.x86.avx10.mask.vminmaxps256.round( - return _mm256_minmax_round_ps(__A, __B, 127, _MM_FROUND_NO_EXC); -} - -__m256 test_mm256_mask_minmax_round_ps(__m256 __A, __mmask8 __B, __m256 __C, __m256 __D) { - // CHECK-LABEL: @test_mm256_mask_minmax_round_ps( - // CHECK: call <8 x float> @llvm.x86.avx10.mask.vminmaxps256.round( - return _mm256_mask_minmax_round_ps(__A, __B, __C, __D, 127, _MM_FROUND_NO_EXC); -} - -__m256 test_mm256_maskz_minmax_round_ps(__mmask8 __A, __m256 __B, __m256 __C) { - // CHECK-LABEL: @test_mm256_maskz_minmax_round_ps( - // CHECK: call <8 x float> @llvm.x86.avx10.mask.vminmaxps256.round( - return _mm256_maskz_minmax_round_ps(__A, __B, __C, 127, _MM_FROUND_NO_EXC); -} - __m128d test_mm_minmax_sd(__m128d __A, __m128d __B) { // CHECK-LABEL: @test_mm_minmax_sd( // CHECK: call <2 x double> @llvm.x86.avx10.mask.vminmaxsd.round( diff --git a/llvm/include/llvm/IR/IntrinsicsX86.td b/llvm/include/llvm/IR/IntrinsicsX86.td index 4fcf2ff8f38df..e66d07dd5b628 100644 --- a/llvm/include/llvm/IR/IntrinsicsX86.td +++ b/llvm/include/llvm/IR/IntrinsicsX86.td @@ -6861,9 +6861,9 @@ def int_x86_avx10_mask_vminmaxpd128 : ClangBuiltin<"__builtin_ia32_vminmaxpd128_ def int_x86_avx10_vminmaxpd256 : ClangBuiltin<"__builtin_ia32_vminmaxpd256">, DefaultAttrsIntrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty, llvm_v4f64_ty, llvm_i32_ty], [IntrNoMem, ImmArg<ArgIndex<2>>]>; -def int_x86_avx10_mask_vminmaxpd256_round : ClangBuiltin<"__builtin_ia32_vminmaxpd256_round_mask">, - DefaultAttrsIntrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty, llvm_v4f64_ty, llvm_i32_ty, llvm_v4f64_ty, llvm_i8_ty, llvm_i32_ty], - [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<5>>]>; +def int_x86_avx10_mask_vminmaxpd256 : ClangBuiltin<"__builtin_ia32_vminmaxpd256_mask">, + DefaultAttrsIntrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty, llvm_v4f64_ty, llvm_i32_ty, llvm_v4f64_ty, llvm_i8_ty], + [IntrNoMem, ImmArg<ArgIndex<2>>]>; def int_x86_avx10_mask_vminmaxpd_round : ClangBuiltin<"__builtin_ia32_vminmaxpd512_round_mask">, DefaultAttrsIntrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty, llvm_v8f64_ty, llvm_i32_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty], [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<5>>]>; @@ -6876,8 +6876,8 @@ def int_x86_avx10_mask_vminmaxph128 : ClangBuiltin<"__builtin_ia32_vminmaxph128_ def int_x86_avx10_vminmaxph256 : ClangBuiltin<"__builtin_ia32_vminmaxph256">, DefaultAttrsIntrinsic<[llvm_v16f16_ty], [llvm_v16f16_ty, llvm_v16f16_ty, llvm_i32_ty], [IntrNoMem, ImmArg<ArgIndex<2>>]>; -def int_x86_avx10_mask_vminmaxph256_round : ClangBuiltin<"__builtin_ia32_vminmaxph256_round_mask">, - DefaultAttrsIntrinsic<[llvm_v16f16_ty], [llvm_v16f16_ty, llvm_v16f16_ty, llvm_i32_ty, llvm_v16f16_ty, llvm_i16_ty, llvm_i32_ty], +def int_x86_avx10_mask_vminmaxph256 : ClangBuiltin<"__builtin_ia32_vminmaxph256_mask">, + DefaultAttrsIntrinsic<[llvm_v16f16_ty], [llvm_v16f16_ty, llvm_v16f16_ty, llvm_i32_ty, llvm_v16f16_ty, llvm_i16_ty], [IntrNoMem, ImmArg<ArgIndex<2>>]>; def int_x86_avx10_mask_vminmaxph_round : ClangBuiltin<"__builtin_ia32_vminmaxph512_round_mask">, DefaultAttrsIntrinsic<[llvm_v32f16_ty], [llvm_v32f16_ty, llvm_v32f16_ty, llvm_i32_ty, llvm_v32f16_ty, llvm_i32_ty, llvm_i32_ty], @@ -6891,9 +6891,9 @@ def int_x86_avx10_mask_vminmaxps128 : ClangBuiltin<"__builtin_ia32_vminmaxps128_ def int_x86_avx10_vminmaxps256 : ClangBuiltin<"__builtin_ia32_vminmaxps256">, DefaultAttrsIntrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty, llvm_v8f32_ty, llvm_i32_ty], [IntrNoMem, ImmArg<ArgIndex<2>>]>; -def int_x86_avx10_mask_vminmaxps256_round : ClangBuiltin<"__builtin_ia32_vminmaxps256_round_mask">, - DefaultAttrsIntrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty, llvm_v8f32_ty, llvm_i32_ty, llvm_v8f32_ty, llvm_i8_ty, llvm_i32_ty], - [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<5>>]>; +def int_x86_avx10_mask_vminmaxps256 : ClangBuiltin<"__builtin_ia32_vminmaxps256_mask">, + DefaultAttrsIntrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty, llvm_v8f32_ty, llvm_i32_ty, llvm_v8f32_ty, llvm_i8_ty], + [IntrNoMem, ImmArg<ArgIndex<2>>]>; def int_x86_avx10_mask_vminmaxps_round : ClangBuiltin<"__builtin_ia32_vminmaxps512_round_mask">, DefaultAttrsIntrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty, llvm_v16f32_ty, llvm_i32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty], [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<5>>]>; diff --git a/llvm/lib/Target/X86/X86InstrAVX10.td b/llvm/lib/Target/X86/X86InstrAVX10.td index b368a5299f907..625f98107e818 100644 --- a/llvm/lib/Target/X86/X86InstrAVX10.td +++ b/llvm/lib/Target/X86/X86InstrAVX10.td @@ -83,7 +83,7 @@ multiclass avx10_minmax_packed_base<string OpStr, X86VectorVTInfo VTI, SDNode Op } multiclass avx10_minmax_packed_sae<string OpStr, AVX512VLVectorVTInfo VTI, SDNode OpNode> { - let Uses = []<Register>, mayRaiseFPException = 0 in { + let Uses = []<Register>, mayRaiseFPException = 0 in defm Zrrib : AVX512_maskable<0x52, MRMSrcReg, VTI.info512, (outs VTI.info512.RC:$dst), (ins VTI.info512.RC:$src1, VTI.info512.RC:$src2, i32u8imm:$src3), OpStr, "$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3", @@ -91,15 +91,6 @@ multiclass avx10_minmax_packed_sae<string OpStr, AVX512VLVectorVTInfo VTI, SDNod (VTI.info512.VT VTI.info512.RC:$src2), (i32 timm:$src3)))>, EVEX, VVVV, EVEX_B, EVEX_V512, Sched<[WriteFMAX]>; - let hasEVEX_U = 1 in - defm Z256rrib : AVX512_maskable<0x52, MRMSrcReg, VTI.info256, (outs VTI.info256.RC:$dst), - (ins VTI.info256.RC:$src1, VTI.info256.RC:$src2, i32u8imm:$src3), OpStr, - "$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3", - (VTI.info256.VT (OpNode (VTI.info256.VT VTI.info256.RC:$src1), - (VTI.info256.VT VTI.info256.RC:$src2), - (i32 timm:$src3)))>, - EVEX, VVVV, EVEX_B, EVEX_V256, Sched<[WriteFMAX]>; - } } multiclass avx10_minmax_packed<string OpStr, AVX512VLVectorVTInfo VTI, SDNode OpNode> { diff --git a/llvm/lib/Target/X86/X86IntrinsicsInfo.h b/llvm/lib/Target/X86/X86IntrinsicsInfo.h index 31c2bfb8f71c2..f1a0623acf760 100644 --- a/llvm/lib/Target/X86/X86IntrinsicsInfo.h +++ b/llvm/lib/Target/X86/X86IntrinsicsInfo.h @@ -597,20 +597,20 @@ static const IntrinsicData IntrinsicsWithoutChain[] = { X86ISD::VMINMAX, X86ISD::VMINMAX_SAE), X86_INTRINSIC_DATA(avx10_mask_vminmaxpd128, INTR_TYPE_3OP_MASK_SAE, X86ISD::VMINMAX, 0), - X86_INTRINSIC_DATA(avx10_mask_vminmaxpd256_round, INTR_TYPE_3OP_MASK_SAE, - X86ISD::VMINMAX, X86ISD::VMINMAX_SAE), + X86_INTRINSIC_DATA(avx10_mask_vminmaxpd256, INTR_TYPE_3OP_MASK_SAE, + X86ISD::VMINMAX, 0), X86_INTRINSIC_DATA(avx10_mask_vminmaxph_round, INTR_TYPE_3OP_MASK_SAE, X86ISD::VMINMAX, X86ISD::VMINMAX_SAE), X86_INTRINSIC_DATA(avx10_mask_vminmaxph128, INTR_TYPE_3OP_MASK_SAE, X86ISD::VMINMAX, 0), - X86_INTRINSIC_DATA(avx10_mask_vminmaxph256_round, INTR_TYPE_3OP_MASK_SAE, - X86ISD::VMINMAX, X86ISD::VMINMAX_SAE), + X86_INTRINSIC_DATA(avx10_mask_vminmaxph256, INTR_TYPE_3OP_MASK_SAE, + X86ISD::VMINMAX, 0), X86_INTRINSIC_DATA(avx10_mask_vminmaxps_round, INTR_TYPE_3OP_MASK_SAE, X86ISD::VMINMAX, X86ISD::VMINMAX_SAE), X86_INTRINSIC_DATA(avx10_mask_vminmaxps128, INTR_TYPE_3OP_MASK_SAE, X86ISD::VMINMAX, 0), - X86_INTRINSIC_DATA(avx10_mask_vminmaxps256_round, INTR_TYPE_3OP_MASK_SAE, - X86ISD::VMINMAX, X86ISD::VMINMAX_SAE), + X86_INTRINSIC_DATA(avx10_mask_vminmaxps256, INTR_TYPE_3OP_MASK_SAE, + X86ISD::VMINMAX, 0), X86_INTRINSIC_DATA(avx10_mask_vminmaxsd_round, INTR_TYPE_3OP_MASK_SAE, X86ISD::VMINMAXS, X86ISD::VMINMAXS_SAE), X86_INTRINSIC_DATA(avx10_mask_vminmaxsh_round, INTR_TYPE_3OP_MASK_SAE, diff --git a/llvm/test/CodeGen/X86/avx10_2minmax-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2minmax-intrinsics.ll index 5dc6ec12b3f60..8ee5c03ca56f1 100644 --- a/llvm/test/CodeGen/X86/avx10_2minmax-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx10_2minmax-intrinsics.ll @@ -175,7 +175,7 @@ define <4 x double> @test_int_x86_avx10_vminmaxpd256(<4 x double> %A, <4 x doubl ; X86: # %bb.0: ; X86-NEXT: vminmaxpd $127, %ymm1, %ymm0, %ymm0 # encoding: [0x62,0xf3,0xfd,0x28,0x52,0xc1,0x7f] ; X86-NEXT: retl # encoding: [0xc3] - %ret = call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256.round(<4 x double> %A, <4 x double> %B, i32 127, <4 x double> zeroinitializer, i8 -1, i32 4) + %ret = call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256(<4 x double> %A, <4 x double> %B, i32 127, <4 x double> zeroinitializer, i8 -1) ret <4 x double> %ret } @@ -193,11 +193,11 @@ define <4 x double> @test_int_x86_avx10_mask_vminmaxpd256(<4 x double> %A, <4 x ; X86-NEXT: vminmaxpd $127, %ymm1, %ymm0, %ymm2 {%k1} # encoding: [0x62,0xf3,0xfd,0x29,0x52,0xd1,0x7f] ; X86-NEXT: vmovapd %ymm2, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x28,0xc2] ; X86-NEXT: retl # encoding: [0xc3] - %ret = call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256.round(<4 x double> %A, <4 x double> %B, i32 127, <4 x double> %C, i8 %D, i32 4) + %ret = call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256(<4 x double> %A, <4 x double> %B, i32 127, <4 x double> %C, i8 %D) ret <4 x double> %ret } -declare <4 x double> @llvm.x86.avx10.mask.vminmaxpd256.round(<4 x double> %A, <4 x double> %B, i32 %C, <4 x double> %D, i8 %E, i32 %F) +declare <4 x double> @llvm.x86.avx10.mask.vminmaxpd256(<4 x double> %A, <4 x double> %B, i32 %C, <4 x double> %D, i8 %E) define <4 x double> @test_int_x86_avx10_maskz_vminmaxpd256(<4 x double> %A, <4 x double> %B, i8 %C) nounwind { ; X64-LABEL: test_int_x86_avx10_maskz_vminmaxpd256: @@ -211,53 +211,7 @@ define <4 x double> @test_int_x86_avx10_maskz_vminmaxpd256(<4 x double> %A, <4 x ; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04] ; X86-NEXT: vminmaxpd $127, %ymm1, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf3,0xfd,0xa9,0x52,0xc1,0x7f] ; X86-NEXT: retl # encoding: [0xc3] - %ret = call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256.round(<4 x double> %A, <4 x double> %B, i32 127, <4 x double> zeroinitializer, i8 %C, i32 4) - ret <4 x double> %ret -} - -define <4 x double>@test_int_x86_vminmaxpd256_round(<4 x double> %A, <4 x double> %B) nounwind { -; X64-LABEL: test_int_x86_vminmaxpd256_round: -; X64: # %bb.0: -; X64-NEXT: vminmaxpd $127, {sae}, %ymm1, %ymm0, %ymm0 # encoding: [0x62,0xf3,0xf9,0x18,0x52,0xc1,0x7f] -; X64-NEXT: retq # encoding: [0xc3] -; -; X86-LABEL: test_int_x86_vminmaxpd256_round: -; X86: # %bb.0: -; X86-NEXT: vminmaxpd $127, {sae}, %ymm1, %ymm0, %ymm0 # encoding: [0x62,0xf3,0xf9,0x18,0x52,0xc1,0x7f] -; X86-NEXT: retl # encoding: [0xc3] - %ret = call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256.round(<4 x double> %A, <4 x double> %B, i32 127, <4 x double> undef, i8 -1, i32 8) - ret <4 x double> %ret -} - -define <4 x double>@test_int_x86_mask_vminmaxpd256_round(<4 x double> %C, <4 x double> %A, <4 x double> %B, i8 %D) nounwind { -; X64-LABEL: test_int_x86_mask_vminmaxpd256_round: -; X64: # %bb.0: -; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf] -; X64-NEXT: vminmaxpd $127, {sae}, %ymm2, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf3,0xf1,0x19,0x52,0xc2,0x7f] -; X64-NEXT: retq # encoding: [0xc3] -; -; X86-LABEL: test_int_x86_mask_vminmaxpd256_round: -; X86: # %bb.0: -; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04] -; X86-NEXT: vminmaxpd $127, {sae}, %ymm2, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf3,0xf1,0x19,0x52,0xc2,0x7f] -; X86-NEXT: retl # encoding: [0xc3] - %ret = call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256.round(<4 x double> %A, <4 x double> %B, i32 127, <4 x double> %C, i8 %D, i32 8) - ret <4 x double> %ret -} - -define <4 x double>@test_int_x86_maskz_vminmaxpd256_round(<4 x double> %A, <4 x double> %B, i8 %C) nounwind { -; X64-LABEL: test_int_x86_maskz_vminmaxpd256_round: -; X64: # %bb.0: -; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf] -; X64-NEXT: vminmaxpd $127, {sae}, %ymm1, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf3,0xf9,0x99,0x52,0xc1,0x7f] -; X64-NEXT: retq # encoding: [0xc3] -; -; X86-LABEL: test_int_x86_maskz_vminmaxpd256_round: -; X86: # %bb.0: -; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04] -; X86-NEXT: vminmaxpd $127, {sae}, %ymm1, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf3,0xf9,0x99,0x52,0xc1,0x7f] -; X86-NEXT: retl # encoding: [0xc3] - %ret = call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256.round(<4 x double> %A, <4 x double> %B, i32 127, <4 x double> zeroinitializer, i8 %C, i32 8) + %ret = call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256(<4 x double> %A, <4 x double> %B, i32 127, <4 x double> zeroinitializer, i8 %C) ret <4 x double> %ret } @@ -322,7 +276,7 @@ define <16 x half> @test_int_x86_avx10_vminmaxph256(<16 x half> %A, <16 x half> ; X86: # %bb.0: ; X86-NEXT: vminmaxph $127, %ymm1, %ymm0, %ymm0 # encoding: [0x62,0xf3,0x7c,0x28,0x52,0xc1,0x7f] ; X86-NEXT: retl # encoding: [0xc3] - %ret = call <16 x half> @llvm.x86.avx10.mask.vminmaxph256.round(<16 x half> %A, <16 x half> %B, i32 127, <16 x half> zeroinitializer, i16 -1, i32 4) + %ret = call <16 x half> @llvm.x86.avx10.mask.vminmaxph256(<16 x half> %A, <16 x half> %B, i32 127, <16 x half> zeroinitializer, i16 -1) ret <16 x half> %ret } @@ -342,11 +296,11 @@ define <16 x half> @test_int_x86_avx10_mask_vminmaxph256(<16 x half> %A, <16 x h ; X86-NEXT: vminmaxph $127, %ymm1, %ymm0, %ymm2 {%k1} # encoding: [0x62,0xf3,0x7c,0x29,0x52,0xd1,0x7f] ; X86-NEXT: vmovaps %ymm2, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0xc2] ; X86-NEXT: retl # encoding: [0xc3] - %ret = call <16 x half> @llvm.x86.avx10.mask.vminmaxph256.round(<16 x half> %A, <16 x half> %B, i32 127, <16 x half> %C, i16 %D, i32 4) + %ret = call <16 x half> @llvm.x86.avx10.mask.vminmaxph256(<16 x half> %A, <16 x half> %B, i32 127, <16 x half> %C, i16 %D) ret <16 x half> %ret } -declare <16 x half> @llvm.x86.avx10.mask.vminmaxph256.round(<16 x half> %A, <16 x half> %B, i32 %C, <16 x half> %D, i16 %E, i32 %F) +declare <16 x half> @llvm.x86.avx10.mask.vminmaxph256(<16 x half> %A, <16 x half> %B, i32 %C, <16 x half> %D, i16 %E) define <16 x half> @test_int_x86_avx10_maskz_vminmaxph256(<16 x half> %A, <16 x half> %B, i16 %C) nounwind { ; X64-LABEL: test_int_x86_avx10_maskz_vminmaxph256: @@ -360,53 +314,7 @@ define <16 x half> @test_int_x86_avx10_maskz_vminmaxph256(<16 x half> %A, <16 x ; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04] ; X86-NEXT: vminmaxph $127, %ymm1, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf3,0x7c,0xa9,0x52,0xc1,0x7f] ; X86-NEXT: retl # encoding: [0xc3] - %ret = call <16 x half> @llvm.x86.avx10.mask.vminmaxph256.round(<16 x half> %A, <16 x half> %B, i32 127, <16 x half> zeroinitializer, i16 %C, i32 4) - ret <16 x half> %ret -} - -define <16 x half> @test_int_x86_vminmaxph256_round(<16 x half> %A, <16 x half> %B) nounwind { -; X64-LABEL: test_int_x86_vminmaxph256_round: -; X64: # %bb.0: -; X64-NEXT: vminmaxph $127, {sae}, %ymm1, %ymm0, %ymm0 # encoding: [0x62,0xf3,0x78,0x18,0x52,0xc1,0x7f] -; X64-NEXT: retq # encoding: [0xc3] -; -; X86-LABEL: test_int_x86_vminmaxph256_round: -; X86: # %bb.0: -; X86-NEXT: vminmaxph $127, {sae}, %ymm1, %ymm0, %ymm0 # encoding: [0x62,0xf3,0x78,0x18,0x52,0xc1,0x7f] -; X86-NEXT: retl # encoding: [0xc3] - %ret = call <16 x half> @llvm.x86.avx10.mask.vminmaxph256.round(<16 x half> %A, <16 x half> %B, i32 127, <16 x half> undef, i16 -1, i32 8) - ret <16 x half> %ret -} - -define <16 x half> @test_int_x86_mask_vminmaxph256_round(<16 x half> %C, <16 x half> %A, <16 x half> %B, i16 %D) nounwind { -; X64-LABEL: test_int_x86_mask_vminmaxph256_round: -; X64: # %bb.0: -; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf] -; X64-NEXT: vminmaxph $127, {sae}, %ymm2, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf3,0x70,0x19,0x52,0xc2,0x7f] -; X64-NEXT: retq # encoding: [0xc3] -; -; X86-LABEL: test_int_x86_mask_vminmaxph256_round: -; X86: # %bb.0: -; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04] -; X86-NEXT: vminmaxph $127, {sae}, %ymm2, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf3,0x70,0x19,0x52,0xc2,0x7f] -; X86-NEXT: retl # encoding: [0xc3] - %ret = call <16 x half> @llvm.x86.avx10.mask.vminmaxph256.round(<16 x half> %A, <16 x half> %B, i32 127, <16 x half> %C, i16 %D, i32 8) - ret <16 x half> %ret -} - -define <16 x half> @test_int_x86_maskz_vminmaxph256_round(<16 x half> %A, <16 x half> %B, i16 %C) nounwind { -; X64-LABEL: test_int_x86_maskz_vminmaxph256_round: -; X64: # %bb.0: -; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf] -; X64-NEXT: vminmaxph $127, {sae}, %ymm1, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf3,0x78,0x99,0x52,0xc1,0x7f] -; X64-NEXT: retq # encoding: [0xc3] -; -; X86-LABEL: test_int_x86_maskz_vminmaxph256_round: -; X86: # %bb.0: -; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04] -; X86-NEXT: vminmaxph $127, {sae}, %ymm1, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf3,0x78,0x99,0x52,0xc1,0x7f] -; X86-NEXT: retl # encoding: [0xc3] - %ret = call <16 x half> @llvm.x86.avx10.mask.vminmaxph256.round(<16 x half> %A, <16 x half> %B, i32 127, <16 x half> zeroinitializer, i16 %C, i32 8) + %ret = call <16 x half> @llvm.x86.avx10.mask.vminmaxph256(<16 x half> %A, <16 x half> %B, i32 127, <16 x half> zeroinitializer, i16 %C) ret <16 x half> %ret } @@ -471,7 +379,7 @@ define <8 x float> @test_int_x86_avx10_vminmaxps256(<8 x float> %A, <8 x float> ; X86: # %bb.0: ; X86-NEXT: vminmaxps $127, %ymm1, %ymm0, %ymm0 # encoding: [0x62,0xf3,0x7d,0x28,0x52,0xc1,0x7f] ; X86-NEXT: retl # encoding: [0xc3] - %ret = call <8 x float> @llvm.x86.avx10.mask.vminmaxps256.round(<8 x float> %A, <8 x float> %B, i32 127, <8 x float> zeroinitializer, i8 -1, i32 4) + %ret = call <8 x float> @llvm.x86.avx10.mask.vminmaxps256(<8 x float> %A, <8 x float> %B, i32 127, <8 x float> zeroinitializer, i8 -1) ret <8 x float> %ret } @@ -489,11 +397,11 @@ define <8 x float> @test_int_x86_avx10_mask_vminmaxps256(<8 x float> %A, <8 x fl ; X86-NEXT: vminmaxps $127, %ymm1, %ymm0, %ymm2 {%k1} # encoding: [0x62,0xf3,0x7d,0x29,0x52,0xd1,0x7f] ; X86-NEXT: vmovapd %ymm2, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x28,0xc2] ; X86-NEXT: retl # encoding: [0xc3] - %ret = call <8 x float> @llvm.x86.avx10.mask.vminmaxps256.round(<8 x float> %A, <8 x float> %B, i32 127, <8 x float> %C, i8 %D, i32 4) + %ret = call <8 x float> @llvm.x86.avx10.mask.vminmaxps256(<8 x float> %A, <8 x float> %B, i32 127, <8 x float> %C, i8 %D) ret <8 x float> %ret } -declare <8 x float> @llvm.x86.avx10.mask.vminmaxps256.round(<8 x float> %A, <8 x float> %B, i32 %C, <8 x float> %D, i8 %E, i32 %F) +declare <8 x float> @llvm.x86.avx10.mask.vminmaxps256(<8 x float> %A, <8 x float> %B, i32 %C, <8 x float> %D, i8 %E) define <8 x float> @test_int_x86_avx10_maskz_vminmaxps256(<8 x float> %A, <8 x float> %B, i8 %C) nounwind { ; X64-LABEL: test_int_x86_avx10_maskz_vminmaxps256: @@ -507,7 +415,7 @@ define <8 x float> @test_int_x86_avx10_maskz_vminmaxps256(<8 x float> %A, <8 x f ; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04] ; X86-NEXT: vminmaxps $127, %ymm1, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf3,0x7d,0xa9,0x52,0xc1,0x7f] ; X86-NEXT: retl # encoding: [0xc3] - %ret = call <8 x float> @llvm.x86.avx10.mask.vminmaxps256.round(<8 x float> %A, <8 x float> %B, i32 127, <8 x float> zeroinitializer, i8 %C, i32 4) + %ret = call <8 x float> @llvm.x86.avx10.mask.vminmaxps256(<8 x float> %A, <8 x float> %B, i32 127, <8 x float> zeroinitializer, i8 %C) ret <8 x float> %ret } @@ -521,7 +429,7 @@ define <8 x float >@test_int_x86_vminmaxps256(<8 x float> %A, <8 x float> %B) no ; X86: # %bb.0: ; X86-NEXT: vminmaxps $127, %ymm1, %ymm0, %ymm0 # encoding: [0x62,0xf3,0x7d,0x28,0x52,0xc1,0x7f] ; X86-NEXT: retl # encoding: [0xc3] - %ret = call <8 x float> @llvm.x86.avx10.mask.vminmaxps256.round(<8 x float> %A, <8 x float> %B, i32 127, <8 x float> undef, i8 -1, i32 4) + %ret = call <8 x float> @llvm.x86.avx10.mask.vminmaxps256(<8 x float> %A, <8 x float> %B, i32 127, <8 x float> undef, i8 -1) ret <8 x float> %ret } @@ -537,7 +445,7 @@ define <8 x float> @test_int_x86_mask_vminmaxps256(<8 x float> %C, <8 x float> % ; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04] ; X86-NEXT: vminmaxps $127, %ymm2, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf3,0x75,0x29,0x52,0xc2,0x7f] ; X86-NEXT: retl # encoding: [0xc3] - %ret = call <8 x float> @llvm.x86.avx10.mask.vminmaxps256.round(<8 x float> %A, <8 x float> %B, i32 127, <8 x float> %C, i8 %D, i32 4) + %ret = call <8 x float> @llvm.x86.avx10.mask.vminmaxps256(<8 x float> %A, <8 x float> %B, i32 127, <8 x float> %C, i8 %D) ret <8 x float> %ret } @@ -553,7 +461,7 @@ define <8 x float> @test_int_x86_maskz_vminmaxps256(<8 x float> %A, <8 x float> ; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04] ; X86-NEXT: vminmaxps $127, %ymm1, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf3,0x7d,0xa9,0x52,0xc1,0x7f] ; X86-NEXT: retl # encoding: [0xc3] - %ret = call <8 x float> @llvm.x86.avx10.mask.vminmaxps256.round(<8 x float> %A, <8 x float> %B, i32 127, <8 x float> zeroinitializer, i8 %C, i32 4) + %ret = call <8 x float> @llvm.x86.avx10.mask.vminmaxps256(<8 x float> %A, <8 x float> %B, i32 127, <8 x float> zeroinitializer, i8 %C) ret <8 x float> %ret } diff --git a/llvm/test/MC/Disassembler/X86/avx10.2minmax-32.txt b/llvm/test/MC/Disassembler/X86/avx10.2minmax-32.txt index 96f9bdccbde19..cf2cae9304907 100644 --- a/llvm/test/MC/Disassembler/X86/avx10.2minmax-32.txt +++ b/llvm/test/MC/Disassembler/X86/avx10.2minmax-32.txt @@ -141,18 +141,10 @@ # INTEL: vminmaxpd ymm2, ymm3, ymm4, 123 0x62,0xf3,0xe5,0x28,0x52,0xd4,0x7b -# ATT: vminmaxpd $123, {sae}, %ymm4, %ymm3, %ymm2 -# INTEL: vminmaxpd ymm2, ymm3, ymm4, {sae}, 123 -0x62,0xf3,0xe1,0x18,0x52,0xd4,0x7b - # ATT: vminmaxpd $123, %ymm4, %ymm3, %ymm2 {%k7} # INTEL: vminmaxpd ymm2 {k7}, ymm3, ymm4, 123 0x62,0xf3,0xe5,0x2f,0x52,0xd4,0x7b -# ATT: vminmaxpd $123, {sae}, %ymm4, %ymm3, %ymm2 {%k7} {z} -# INTEL: vminmaxpd ymm2 {k7} {z}, ymm3, ymm4, {sae}, 123 -0x62,0xf3,0xe1,0x9f,0x52,0xd4,0x7b - # ATT: vminmaxpd $123, 268435456(%esp,%esi,8), %ymm3, %ymm2 # INTEL: vminmaxpd ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456], 123 0x62,0xf3,0xe5,0x28,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b @@ -257,18 +249,10 @@ # INTEL: vminmaxph ymm2, ymm3, ymm4, 123 0x62,0xf3,0x64,0x28,0x52,0xd4,0x7b -# ATT: vminmaxph $123, {sae}, %ymm4, %ymm3, %ymm2 -# INTEL: vminmaxph ymm2, ymm3, ymm4, {sae}, 123 -0x62,0xf3,0x60,0x18,0x52,0xd4,0x7b - # ATT: vminmaxph $123, %ymm4, %ymm3, %ymm2 {%k7} # INTEL: vminmaxph ymm2 {k7}, ymm3, ymm4, 123 0x62,0xf3,0x64,0x2f,0x52,0xd4,0x7b -# ATT: vminmaxph $123, {sae}, %ymm4, %ymm3, %ymm2 {%k7} {z} -# INTEL: vminmaxph ymm2 {k7} {z}, ymm3, ymm4, {sae}, 123 -0x62,0xf3,0x60,0x9f,0x52,0xd4,0x7b - # ATT: vminmaxph $123, 268435456(%esp,%esi,8), %ymm3, %ymm2 # INTEL: vminmaxph ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456], 123 0x62,0xf3,0x64,0x28,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b @@ -373,18 +357,10 @@ # INTEL: vminmaxps ymm2, ymm3, ymm4, 123 0x62,0xf3,0x65,0x28,0x52,0xd4,0x7b -# ATT: vminmaxps $123, {sae}, %ymm4, %ymm3, %ymm2 -# INTEL: vminmaxps ymm2, ymm3, ymm4, {sae}, 123 -0x62,0xf3,0x61,0x18,0x52,0xd4,0x7b - # ATT: vminmaxps $123, %ymm4, %ymm3, %ymm2 {%k7} # INTEL: vminmaxps ymm2 {k7}, ymm3, ymm4, 123 0x62,0xf3,0x65,0x2f,0x52,0xd4,0x7b -# ATT: vminmaxps $123, {sae}, %ymm4, %ymm3, %ymm2 {%k7} {z} -# INTEL: vminmaxps ymm2 {k7} {z}, ymm3, ymm4, {sae}, 123 -0x62,0xf3,0x61,0x9f,0x52,0xd4,0x7b - # ATT: vminmaxps $123, 268435456(%esp,%esi,8), %ymm3, %ymm2 # INTEL: vminmaxps ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456], 123 0x62,0xf3,0x65,0x28,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b diff --git a/llvm/test/MC/Disassembler/X86/avx10.2minmax-64.txt b/llvm/test/MC/Disassembler/X86/avx10.2minmax-64.txt index af80fb1a3f48c..e17e6032212e8 100644 --- a/llvm/test/MC/Disassembler/X86/avx10.2minmax-64.txt +++ b/llvm/test/MC/Disassembler/X86/avx10.2minmax-64.txt @@ -141,18 +141,10 @@ # INTEL: vminmaxpd ymm22, ymm23, ymm24, 123 0x62,0x83,0xc5,0x20,0x52,0xf0,0x7b -# ATT: vminmaxpd $123, {sae}, %ymm24, %ymm23, %ymm22 -# INTEL: vminmaxpd ymm22, ymm23, ymm24, {sae}, 123 -0x62,0x83,0xc1,0x10,0x52,0xf0,0x7b - # ATT: vminmaxpd $123, %ymm24, %ymm23, %ymm22 {%k7} # INTEL: vminmaxpd ymm22 {k7}, ymm23, ymm24, 123 0x62,0x83,0xc5,0x27,0x52,0xf0,0x7b -# ATT: vminmaxpd $123, {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z} -# INTEL: vminmaxpd ymm22 {k7} {z}, ymm23, ymm24, {sae}, 123 -0x62,0x83,0xc1,0x97,0x52,0xf0,0x7b - # ATT: vminmaxpd $123, 268435456(%rbp,%r14,8), %ymm23, %ymm22 # INTEL: vminmaxpd ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456], 123 0x62,0xa3,0xc5,0x20,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b @@ -257,18 +249,10 @@ # INTEL: vminmaxph ymm22, ymm23, ymm24, 123 0x62,0x83,0x44,0x20,0x52,0xf0,0x7b -# ATT: vminmaxph $123, {sae}, %ymm24, %ymm23, %ymm22 -# INTEL: vminmaxph ymm22, ymm23, ymm24, {sae}, 123 -0x62,0x83,0x40,0x10,0x52,0xf0,0x7b - # ATT: vminmaxph $123, %ymm24, %ymm23, %ymm22 {%k7} # INTEL: vminmaxph ymm22 {k7}, ymm23, ymm24, 123 0x62,0x83,0x44,0x27,0x52,0xf0,0x7b -# ATT: vminmaxph $123, {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z} -# INTEL: vminmaxph ymm22 {k7} {z}, ymm23, ymm24, {sae}, 123 -0x62,0x83,0x40,0x97,0x52,0xf0,0x7b - # ATT: vminmaxph $123, 268435456(%rbp,%r14,8), %ymm23, %ymm22 # INTEL: vminmaxph ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456], 123 0x62,0xa3,0x44,0x20,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b @@ -373,18 +357,10 @@ # INTEL: vminmaxps ymm22, ymm23, ymm24, 123 0x62,0x83,0x45,0x20,0x52,0xf0,0x7b -# ATT: vminmaxps $123, {sae}, %ymm24, %ymm23, %ymm22 -# INTEL: vminmaxps ymm22, ymm23, ymm24, {sae}, 123 -0x62,0x83,0x41,0x10,0x52,0xf0,0x7b - # ATT: vminmaxps $123, %ymm24, %ymm23, %ymm22 {%k7} # INTEL: vminmaxps ymm22 {k7}, ymm23, ymm24, 123 0x62,0x83,0x45,0x27,0x52,0xf0,0x7b -# ATT: vminmaxps $123, {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z} -# INTEL: vminmaxps ymm22 {k7} {z}, ymm23, ymm24, {sae}, 123 -0x62,0x83,0x41,0x97,0x52,0xf0,0x7b - # ATT: vminmaxps $123, 268435456(%rbp,%r14,8), %ymm23, %ymm22 # INTEL: vminmaxps ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456], 123 0x62,0xa3,0x45,0x20,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b diff --git a/llvm/test/MC/X86/avx10.2minmax-32-att.s b/llvm/test/MC/X86/avx10.2minmax-32-att.s index 5e3b687543c42..bf1ab4b884393 100644 --- a/llvm/test/MC/X86/avx10.2minmax-32-att.s +++ b/llvm/test/MC/X86/avx10.2minmax-32-att.s @@ -140,18 +140,10 @@ // CHECK: encoding: [0x62,0xf3,0xe5,0x28,0x52,0xd4,0x7b] vminmaxpd $123, %ymm4, %ymm3, %ymm2 -// CHECK: vminmaxpd $123, {sae}, %ymm4, %ymm3, %ymm2 -// CHECK: encoding: [0x62,0xf3,0xe1,0x18,0x52,0xd4,0x7b] - vminmaxpd $123, {sae}, %ymm4, %ymm3, %ymm2 - // CHECK: vminmaxpd $123, %ymm4, %ymm3, %ymm2 {%k7} // CHECK: encoding: [0x62,0xf3,0xe5,0x2f,0x52,0xd4,0x7b] vminmaxpd $123, %ymm4, %ymm3, %ymm2 {%k7} -// CHECK: vminmaxpd $123, {sae}, %ymm4, %ymm3, %ymm2 {%k7} {z} -// CHECK: encoding: [0x62,0xf3,0xe1,0x9f,0x52,0xd4,0x7b] - vminmaxpd $123, {sae}, %ymm4, %ymm3, %ymm2 {%k7} {z} - // CHECK: vminmaxpd $123, 268435456(%esp,%esi,8), %ymm3, %ymm2 // CHECK: encoding: [0x62,0xf3,0xe5,0x28,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b] vminmaxpd $123, 268435456(%esp,%esi,8), %ymm3, %ymm2 @@ -256,18 +248,10 @@ // CHECK: encoding: [0x62,0xf3,0x64,0x28,0x52,0xd4,0x7b] vminmaxph $123, %ymm4, %ymm3, %ymm2 -// CHECK: vminmaxph $123, {sae}, %ymm4, %ymm3, %ymm2 -// CHECK: encoding: [0x62,0xf3,0x60,0x18,0x52,0xd4,0x7b] - vminmaxph $123, {sae}, %ymm4, %ymm3, %ymm2 - // CHECK: vminmaxph $123, %ymm4, %ymm3, %ymm2 {%k7} // CHECK: encoding: [0x62,0xf3,0x64,0x2f,0x52,0xd4,0x7b] vminmaxph $123, %ymm4, %ymm3, %ymm2 {%k7} -// CHECK: vminmaxph $123, {sae}, %ymm4, %ymm3, %ymm2 {%k7} {z} -// CHECK: encoding: [0x62,0xf3,0x60,0x9f,0x52,0xd4,0x7b] - vminmaxph $123, {sae}, %ymm4, %ymm3, %ymm2 {%k7} {z} - // CHECK: vminmaxph $123, 268435456(%esp,%esi,8), %ymm3, %ymm2 // CHECK: encoding: [0x62,0xf3,0x64,0x28,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b] vminmaxph $123, 268435456(%esp,%esi,8), %ymm3, %ymm2 @@ -372,18 +356,10 @@ // CHECK: encoding: [0x62,0xf3,0x65,0x28,0x52,0xd4,0x7b] vminmaxps $123, %ymm4, %ymm3, %ymm2 -// CHECK: vminmaxps $123, {sae}, %ymm4, %ymm3, %ymm2 -// CHECK: encoding: [0x62,0xf3,0x61,0x18,0x52,0xd4,0x7b] - vminmaxps $123, {sae}, %ymm4, %ymm3, %ymm2 - // CHECK: vminmaxps $123, %ymm4, %ymm3, %ymm2 {%k7} // CHECK: encoding: [0x62,0xf3,0x65,0x2f,0x52,0xd4,0x7b] vminmaxps $123, %ymm4, %ymm3, %ymm2 {%k7} -// CHECK: vminmaxps $123, {sae}, %ymm4, %ymm3, %ymm2 {%k7} {z} -// CHECK: encoding: [0x62,0xf3,0x61,0x9f,0x52,0xd4,0x7b] - vminmaxps $123, {sae}, %ymm4, %ymm3, %ymm2 {%k7} {z} - // CHECK: vminmaxps $123, 268435456(%esp,%esi,8), %ymm3, %ymm2 // CHECK: encoding: [0x62,0xf3,0x65,0x28,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b] vminmaxps $123, 268435456(%esp,%esi,8), %ymm3, %ymm2 diff --git a/llvm/test/MC/X86/avx10.2minmax-32-intel.s b/llvm/test/MC/X86/avx10.2minmax-32-intel.s index c237b09e15954..66e3b53226b02 100644 --- a/llvm/test/MC/X86/avx10.2minmax-32-intel.s +++ b/llvm/test/MC/X86/avx10.2minmax-32-intel.s @@ -140,18 +140,10 @@ // CHECK: encoding: [0x62,0xf3,0xe5,0x28,0x52,0xd4,0x7b] vminmaxpd ymm2, ymm3, ymm4, 123 -// CHECK: vminmaxpd ymm2, ymm3, ymm4, {sae}, 123 -// CHECK: encoding: [0x62,0xf3,0xe1,0x18,0x52,0xd4,0x7b] - vminmaxpd ymm2, ymm3, ymm4, {sae}, 123 - // CHECK: vminmaxpd ymm2 {k7}, ymm3, ymm4, 123 // CHECK: encoding: [0x62,0xf3,0xe5,0x2f,0x52,0xd4,0x7b] vminmaxpd ymm2 {k7}, ymm3, ymm4, 123 -// CHECK: vminmaxpd ymm2 {k7} {z}, ymm3, ymm4, {sae}, 123 -// CHECK: encoding: [0x62,0xf3,0xe1,0x9f,0x52,0xd4,0x7b] - vminmaxpd ymm2 {k7} {z}, ymm3, ymm4, {sae}, 123 - // CHECK: vminmaxpd ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456], 123 // CHECK: encoding: [0x62,0xf3,0xe5,0x28,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b] vminmaxpd ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456], 123 @@ -256,18 +248,10 @@ // CHECK: encoding: [0x62,0xf3,0x64,0x28,0x52,0xd4,0x7b] vminmaxph ymm2, ymm3, ymm4, 123 -// CHECK: vminmaxph ymm2, ymm3, ymm4, {sae}, 123 -// CHECK: encoding: [0x62,0xf3,0x60,0x18,0x52,0xd4,0x7b] - vminmaxph ymm2, ymm3, ymm4, {sae}, 123 - // CHECK: vminmaxph ymm2 {k7}, ymm3, ymm4, 123 // CHECK: encoding: [0x62,0xf3,0x64,0x2f,0x52,0xd4,0x7b] vminmaxph ymm2 {k7}, ymm3, ymm4, 123 -// CHECK: vminmaxph ymm2 {k7} {z}, ymm3, ymm4, {sae}, 123 -// CHECK: encoding: [0x62,0xf3,0x60,0x9f,0x52,0xd4,0x7b] - vminmaxph ymm2 {k7} {z}, ymm3, ymm4, {sae}, 123 - // CHECK: vminmaxph ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456], 123 // CHECK: encoding: [0x62,0xf3,0x64,0x28,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b] vminmaxph ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456], 123 @@ -372,18 +356,10 @@ // CHECK: encoding: [0x62,0xf3,0x65,0x28,0x52,0xd4,0x7b] vminmaxps ymm2, ymm3, ymm4, 123 -// CHECK: vminmaxps ymm2, ymm3, ymm4, {sae}, 123 -// CHECK: encoding: [0x62,0xf3,0x61,0x18,0x52,0xd4,0x7b] - vminmaxps ymm2, ymm3, ymm4, {sae}, 123 - // CHECK: vminmaxps ymm2 {k7}, ymm3, ymm4, 123 // CHECK: encoding: [0x62,0xf3,0x65,0x2f,0x52,0xd4,0x7b] vminmaxps ymm2 {k7}, ymm3, ymm4, 123 -// CHECK: vminmaxps ymm2 {k7} {z}, ymm3, ymm4, {sae}, 123 -// CHECK: encoding: [0x62,0xf3,0x61,0x9f,0x52,0xd4,0x7b] - vminmaxps ymm2 {k7} {z}, ymm3, ymm4, {sae}, 123 - // CHECK: vminmaxps ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456], 123 // CHECK: encoding: [0x62,0xf3,0x65,0x28,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b] vminmaxps ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456], 123 diff --git a/llvm/test/MC/X86/avx10.2minmax-64-att.s b/llvm/test/MC/X86/avx10.2minmax-64-att.s index ad237d1fb2596..00d9f348ddbe7 100644 --- a/llvm/test/MC/X86/avx10.2minmax-64-att.s +++ b/llvm/test/MC/X86/avx10.2minmax-64-att.s @@ -140,18 +140,10 @@ // CHECK: encoding: [0x62,0x83,0xc5,0x20,0x52,0xf0,0x7b] vminmaxpd $123, %ymm24, %ymm23, %ymm22 -// CHECK: vminmaxpd $123, {sae}, %ymm24, %ymm23, %ymm22 -// CHECK: encoding: [0x62,0x83,0xc1,0x10,0x52,0xf0,0x7b] - vminmaxpd $123, {sae}, %ymm24, %ymm23, %ymm22 - // CHECK: vminmaxpd $123, %ymm24, %ymm23, %ymm22 {%k7} // CHECK: encoding: [0x62,0x83,0xc5,0x27,0x52,0xf0,0x7b] vminmaxpd $123, %ymm24, %ymm23, %ymm22 {%k7} -// CHECK: vminmaxpd $123, {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z} -// CHECK: encoding: [0x62,0x83,0xc1,0x97,0x52,0xf0,0x7b] - vminmaxpd $123, {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z} - // CHECK: vminmaxpd $123, 268435456(%rbp,%r14,8), %ymm23, %ymm22 // CHECK: encoding: [0x62,0xa3,0xc5,0x20,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b] vminmaxpd $123, 268435456(%rbp,%r14,8), %ymm23, %ymm22 @@ -256,18 +248,10 @@ // CHECK: encoding: [0x62,0x83,0x44,0x20,0x52,0xf0,0x7b] vminmaxph $123, %ymm24, %ymm23, %ymm22 -// CHECK: vminmaxph $123, {sae}, %ymm24, %ymm23, %ymm22 -// CHECK: encoding: [0x62,0x83,0x40,0x10,0x52,0xf0,0x7b] - vminmaxph $123, {sae}, %ymm24, %ymm23, %ymm22 - // CHECK: vminmaxph $123, %ymm24, %ymm23, %ymm22 {%k7} // CHECK: encoding: [0x62,0x83,0x44,0x27,0x52,0xf0,0x7b] vminmaxph $123, %ymm24, %ymm23, %ymm22 {%k7} -// CHECK: vminmaxph $123, {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z} -// CHECK: encoding: [0x62,0x83,0x40,0x97,0x52,0xf0,0x7b] - vminmaxph $123, {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z} - // CHECK: vminmaxph $123, 268435456(%rbp,%r14,8), %ymm23, %ymm22 // CHECK: encoding: [0x62,0xa3,0x44,0x20,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b] vminmaxph $123, 268435456(%rbp,%r14,8), %ymm23, %ymm22 @@ -372,18 +356,10 @@ // CHECK: encoding: [0x62,0x83,0x45,0x20,0x52,0xf0,0x7b] vminmaxps $123, %ymm24, %ymm23, %ymm22 -// CHECK: vminmaxps $123, {sae}, %ymm24, %ymm23, %ymm22 -// CHECK: encoding: [0x62,0x83,0x41,0x10,0x52,0xf0,0x7b] - vminmaxps $123, {sae}, %ymm24, %ymm23, %ymm22 - // CHECK: vminmaxps $123, %ymm24, %ymm23, %ymm22 {%k7} // CHECK: encoding: [0x62,0x83,0x45,0x27,0x52,0xf0,0x7b] vminmaxps $123, %ymm24, %ymm23, %ymm22 {%k7} -// CHECK: vminmaxps $123, {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z} -// CHECK: encoding: [0x62,0x83,0x41,0x97,0x52,0xf0,0x7b] - vminmaxps $123, {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z} - // CHECK: vminmaxps $123, 268435456(%rbp,%r14,8), %ymm23, %ymm22 // CHECK: encoding: [0x62,0xa3,0x45,0x20,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b] vminmaxps $123, 268435456(%rbp,%r14,8), %ymm23, %ymm22 diff --git a/llvm/test/MC/X86/avx10.2minmax-64-intel.s b/llvm/test/MC/X86/avx10.2minmax-64-intel.s index 81c59332fac84..5f189aa3d7787 100644 --- a/llvm/test/MC/X86/avx10.2minmax-64-intel.s +++ b/llvm/test/MC/X86/avx10.2minmax-64-intel.s @@ -140,18 +140,10 @@ // CHECK: encoding: [0x62,0x83,0xc5,0x20,0x52,0xf0,0x7b] vminmaxpd ymm22, ymm23, ymm24, 123 -// CHECK: vminmaxpd ymm22, ymm23, ymm24, {sae}, 123 -// CHECK: encoding: [0x62,0x83,0xc1,0x10,0x52,0xf0,0x7b] - vminmaxpd ymm22, ymm23, ymm24, {sae}, 123 - // CHECK: vminmaxpd ymm22 {k7}, ymm23, ymm24, 123 // CHECK: encoding: [0x62,0x83,0xc5,0x27,0x52,0xf0,0x7b] vminmaxpd ymm22 {k7}, ymm23, ymm24, 123 -// CHECK: vminmaxpd ymm22 {k7} {z}, ymm23, ymm24, {sae}, 123 -// CHECK: encoding: [0x62,0x83,0xc1,0x97,0x52,0xf0,0x7b] - vminmaxpd ymm22 {k7} {z}, ymm23, ymm24, {sae}, 123 - // CHECK: vminmaxpd ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456], 123 // CHECK: encoding: [0x62,0xa3,0xc5,0x20,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b] vminmaxpd ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456], 123 @@ -256,18 +248,10 @@ // CHECK: encoding: [0x62,0x83,0x44,0x20,0x52,0xf0,0x7b] vminmaxph ymm22, ymm23, ymm24, 123 -// CHECK: vminmaxph ymm22, ymm23, ymm24, {sae}, 123 -// CHECK: encoding: [0x62,0x83,0x40,0x10,0x52,0xf0,0x7b] - vminmaxph ymm22, ymm23, ymm24, {sae}, 123 - // CHECK: vminmaxph ymm22 {k7}, ymm23, ymm24, 123 // CHECK: encoding: [0x62,0x83,0x44,0x27,0x52,0xf0,0x7b] vminmaxph ymm22 {k7}, ymm23, ymm24, 123 -// CHECK: vminmaxph ymm22 {k7} {z}, ymm23, ymm24, {sae}, 123 -// CHECK: encoding: [0x62,0x83,0x40,0x97,0x52,0xf0,0x7b] - vminmaxph ymm22 {k7} {z}, ymm23, ymm24, {sae}, 123 - // CHECK: vminmaxph ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456], 123 // CHECK: encoding: [0x62,0xa3,0x44,0x20,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b] vminmaxph ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456], 123 @@ -372,18 +356,10 @@ // CHECK: encoding: [0x62,0x83,0x45,0x20,0x52,0xf0,0x7b] vminmaxps ymm22, ymm23, ymm24, 123 -// CHECK: vminmaxps ymm22, ymm23, ymm24, {sae}, 123 -// CHECK: encoding: [0x62,0x83,0x41,0x10,0x52,0xf0,0x7b] - vminmaxps ymm22, ymm23, ymm24, {sae}, 123 - // CHECK: vminmaxps ymm22 {k7}, ymm23, ymm24, 123 // CHECK: encoding: [0x62,0x83,0x45,0x27,0x52,0xf0,0x7b] vminmaxps ymm22 {k7}, ymm23, ymm24, 123 -// CHECK: vminmaxps ymm22 {k7} {z}, ymm23, ymm24, {sae}, 123 -// CHECK: encoding: [0x62,0x83,0x41,0x97,0x52,0xf0,0x7b] - vminmaxps ymm22 {k7} {z}, ymm23, ymm24, {sae}, 123 - // CHECK: vminmaxps ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456], 123 // CHECK: encoding: [0x62,0xa3,0x45,0x20,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b] vminmaxps ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456], 123 >From 45cafe1b3f82e418d8043deae32eb164f7138654 Mon Sep 17 00:00:00 2001 From: "Wang, Phoebe" <phoebe.w...@intel.com> Date: Fri, 21 Mar 2025 22:50:59 +0800 Subject: [PATCH 2/2] replace undef with poison --- llvm/test/CodeGen/X86/avx10_2minmax-intrinsics.ll | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/llvm/test/CodeGen/X86/avx10_2minmax-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2minmax-intrinsics.ll index 8ee5c03ca56f1..916d439ab77f0 100644 --- a/llvm/test/CodeGen/X86/avx10_2minmax-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx10_2minmax-intrinsics.ll @@ -429,7 +429,7 @@ define <8 x float >@test_int_x86_vminmaxps256(<8 x float> %A, <8 x float> %B) no ; X86: # %bb.0: ; X86-NEXT: vminmaxps $127, %ymm1, %ymm0, %ymm0 # encoding: [0x62,0xf3,0x7d,0x28,0x52,0xc1,0x7f] ; X86-NEXT: retl # encoding: [0xc3] - %ret = call <8 x float> @llvm.x86.avx10.mask.vminmaxps256(<8 x float> %A, <8 x float> %B, i32 127, <8 x float> undef, i8 -1) + %ret = call <8 x float> @llvm.x86.avx10.mask.vminmaxps256(<8 x float> %A, <8 x float> %B, i32 127, <8 x float> poison, i8 -1) ret <8 x float> %ret } @@ -475,7 +475,7 @@ define <2 x double>@test_int_x86_vminmaxsd(<2 x double> %A, <2 x double> %B) nou ; X86: # %bb.0: ; X86-NEXT: vminmaxsd $127, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0xfd,0x08,0x53,0xc1,0x7f] ; X86-NEXT: retl # encoding: [0xc3] - %ret = call <2 x double> @llvm.x86.avx10.mask.vminmaxsd.round(<2 x double> %A, <2 x double> %B, i32 127, <2 x double> undef, i8 -1, i32 4) + %ret = call <2 x double> @llvm.x86.avx10.mask.vminmaxsd.round(<2 x double> %A, <2 x double> %B, i32 127, <2 x double> poison, i8 -1, i32 4) ret <2 x double> %ret } @@ -523,7 +523,7 @@ define <2 x double>@test_int_x86_vminmaxsd_round(<2 x double> %A, <2 x double> % ; X86: # %bb.0: ; X86-NEXT: vminmaxsd $127, {sae}, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0xfd,0x18,0x53,0xc1,0x7f] ; X86-NEXT: retl # encoding: [0xc3] - %ret = call <2 x double> @llvm.x86.avx10.mask.vminmaxsd.round(<2 x double> %A, <2 x double> %B, i32 127, <2 x double> undef, i8 -1, i32 8) + %ret = call <2 x double> @llvm.x86.avx10.mask.vminmaxsd.round(<2 x double> %A, <2 x double> %B, i32 127, <2 x double> poison, i8 -1, i32 8) ret <2 x double> %ret } @@ -573,7 +573,7 @@ define <8 x half>@test_int_x86_vminmaxsh(<8 x half> %A, <8 x half> %B) nounwind ; X86: # %bb.0: ; X86-NEXT: vminmaxsh $127, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0x7c,0x08,0x53,0xc1,0x7f] ; X86-NEXT: retl # encoding: [0xc3] - %ret = call <8 x half> @llvm.x86.avx10.mask.vminmaxsh.round(<8 x half> %A, <8 x half> %B, i32 127, <8 x half> undef, i8 -1, i32 4) + %ret = call <8 x half> @llvm.x86.avx10.mask.vminmaxsh.round(<8 x half> %A, <8 x half> %B, i32 127, <8 x half> poison, i8 -1, i32 4) ret <8 x half> %ret } @@ -621,7 +621,7 @@ define <8 x half>@test_int_x86_vminmaxsh_round(<8 x half> %A, <8 x half> %B) nou ; X86: # %bb.0: ; X86-NEXT: vminmaxsh $127, {sae}, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0x7c,0x18,0x53,0xc1,0x7f] ; X86-NEXT: retl # encoding: [0xc3] - %ret = call <8 x half> @llvm.x86.avx10.mask.vminmaxsh.round(<8 x half> %A, <8 x half> %B, i32 127, <8 x half> undef, i8 -1, i32 8) + %ret = call <8 x half> @llvm.x86.avx10.mask.vminmaxsh.round(<8 x half> %A, <8 x half> %B, i32 127, <8 x half> poison, i8 -1, i32 8) ret <8 x half> %ret } @@ -671,7 +671,7 @@ define <4 x float>@test_int_x86_vminmaxss(<4 x float> %A, <4 x float> %B) nounwi ; X86: # %bb.0: ; X86-NEXT: vminmaxss $127, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0x7d,0x08,0x53,0xc1,0x7f] ; X86-NEXT: retl # encoding: [0xc3] - %ret = call <4 x float> @llvm.x86.avx10.mask.vminmaxss.round(<4 x float> %A, <4 x float> %B, i32 127, <4 x float> undef, i8 -1, i32 4) + %ret = call <4 x float> @llvm.x86.avx10.mask.vminmaxss.round(<4 x float> %A, <4 x float> %B, i32 127, <4 x float> poison, i8 -1, i32 4) ret <4 x float> %ret } @@ -719,7 +719,7 @@ define <4 x float>@test_int_x86_vminmaxss_round(<4 x float> %A, <4 x float> %B) ; X86: # %bb.0: ; X86-NEXT: vminmaxss $127, {sae}, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0x7d,0x18,0x53,0xc1,0x7f] ; X86-NEXT: retl # encoding: [0xc3] - %ret = call <4 x float> @llvm.x86.avx10.mask.vminmaxss.round(<4 x float> %A, <4 x float> %B, i32 127, <4 x float> undef, i8 -1, i32 8) + %ret = call <4 x float> @llvm.x86.avx10.mask.vminmaxss.round(<4 x float> %A, <4 x float> %B, i32 127, <4 x float> poison, i8 -1, i32 8) ret <4 x float> %ret } _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
