[clang] [llvm] [mlir] [TableGen] Only store direct superclasses in Record (PR #123072)

@@ -3415,10 +3419,11 @@ namespace { AttrClass *findSuperClass(const Record *R) const { // TableGen flattens the superclass list, so we just need to walk it // in reverse. - auto SuperClasses = R->getSuperClasses(); - for (signed i = 0, e = SuperClasses

[clang] [llvm] [mlir] [TableGen] Only store direct superclasses in Record (PR #123072)

@@ -1718,15 +1719,30 @@ class Record { ArrayRef getAssertions() const { return Assertions; } ArrayRef getDumps() const { return Dumps; } - ArrayRef> getSuperClasses() const { -return SuperClasses; + /// Append all superclasses in post-order to \p Classes. + void get

[clang] [llvm] [mlir] [TableGen] Only store direct superclasses in Record (PR #123072)

@@ -1630,9 +1630,9 @@ class Record { SmallVector Assertions; SmallVector Dumps; - // All superclasses in the inheritance forest in post-order (yes, it + // Direct superclasses, which are roots of the inheritance forest (yes, it // must be a forest; diamond-shaped inhe

[clang] [llvm] [IR][AsmParser] Revamp how floating-point literals in LLVM IR. (PR #121838)

@@ -1017,11 +1018,13 @@ lltok::Kind LLLexer::LexIdentifier() { } // Check for [us]0x[0-9A-Fa-f]+ which are Hexadecimal constant generated by - // the CFE to avoid forcing it to deal with 64-bit numbers. - if ((TokStart[0] == 'u' || TokStart[0] == 's') && + // the CFE to

[clang] [llvm] [IR][AsmParser] Revamp how floating-point literals in LLVM IR. (PR #121838)

@@ -3829,10 +3829,40 @@ bool LLParser::parseValID(ValID &ID, PerFunctionState *PFS, Type *ExpectedTy) { ID.APSIntVal = Lex.getAPSIntVal(); ID.Kind = ValID::t_APSInt; break; - case lltok::APFloat: + case lltok::APFloat: { +assert(ExpectedTy && "Need type to pa

[clang] [llvm] [RISCV] Add a generic OOO CPU (PR #120712)

https://github.com/mshockwave edited https://github.com/llvm/llvm-project/pull/120712 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add a generic OOO CPU (PR #120712)

@@ -0,0 +1,494 @@ +//===-- RISCVSchedGenericOOO.td - Generic O3 Processor -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Add a generic OOO CPU (PR #120712)

@@ -0,0 +1,601 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=riscv64 -mattr=+rva23u64,+zabha -mcpu=generic-ooo --all-stats -iterations=1 < %s | FileCheck %s mshockwave wrote: nit: `--all-stats` shows

[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

@@ -0,0 +1,290 @@ +//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

@@ -0,0 +1,290 @@ +//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

@@ -0,0 +1,290 @@ +//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

@@ -0,0 +1,290 @@ +//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

@@ -0,0 +1,290 @@ +//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

@@ -0,0 +1,290 @@ +//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

https://github.com/mshockwave closed https://github.com/llvm/llvm-project/pull/117368 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -0,0 +1,266 @@ +//===-- xray_riscv.cpp *- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -1575,6 +1575,26 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { // No patch bytes means at most a PseudoCall is emitted return std::max(NumBytes, 8U); } + case TargetOpcode::PATCHABLE_FUNCTION_ENTER: + case TargetOpcode::PATCHABLE

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -0,0 +1,266 @@ +//===-- xray_riscv.cpp *- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/117368 >From 599370a06008092f6aa883bf11600d0b66707bc0 Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Wed, 20 Nov 2024 14:37:57 -0800 Subject: [PATCH 1/8] [XRay][RISCV] RISCV support for XRay Add RISC-V support fo

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/117368 >From 599370a06008092f6aa883bf11600d0b66707bc0 Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Wed, 20 Nov 2024 14:37:57 -0800 Subject: [PATCH 1/6] [XRay][RISCV] RISCV support for XRay Add RISC-V support fo

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -0,0 +1,266 @@ +//===-- xray_riscv.cpp *- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -453,11 +475,71 @@ bool RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) { SetupMachineFunction(MF); emitFunctionBody(); + // Emit the XRay table + emitXRayTable(); + if (EmittedOptionArch) RTS.emitDirectiveOptionPop(); return false; } +void R

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/117368 >From 599370a06008092f6aa883bf11600d0b66707bc0 Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Wed, 20 Nov 2024 14:37:57 -0800 Subject: [PATCH 1/4] [XRay][RISCV] RISCV support for XRay Add RISC-V support fo

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -0,0 +1,87 @@ +//===-- xray_trampoline_riscv32.s --*- ASM -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier:

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/117368 >From 599370a06008092f6aa883bf11600d0b66707bc0 Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Wed, 20 Nov 2024 14:37:57 -0800 Subject: [PATCH 1/5] [XRay][RISCV] RISCV support for XRay Add RISC-V support fo

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -57,6 +57,10 @@ static const int16_t cSledLength = 64; static const int16_t cSledLength = 8; #elif defined(__hexagon__) static const int16_t cSledLength = 20; +#elif SANITIZER_RISCV64 +static const int16_t cSledLength = 76; +#elif defined(__riscv) && (__riscv_xlen == 32) ---

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/117368 >From 599370a06008092f6aa883bf11600d0b66707bc0 Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Wed, 20 Nov 2024 14:37:57 -0800 Subject: [PATCH 1/3] [XRay][RISCV] RISCV support for XRay Add RISC-V support fo

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

https://github.com/mshockwave edited https://github.com/llvm/llvm-project/pull/117368 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -57,6 +57,10 @@ static const int16_t cSledLength = 64; static const int16_t cSledLength = 8; #elif defined(__hexagon__) static const int16_t cSledLength = 20; +#elif SANITIZER_RISCV64 +static const int16_t cSledLength = 76; +#elif defined(__riscv) && (__riscv_xlen == 32) ---

[clang] [compiler-rt] [llvm] [XRay] Add `-fxray-default-options` to pass build-time defined XRay options (PR #116878)

mshockwave wrote: Close this PR in favor of #117921 https://github.com/llvm/llvm-project/pull/116878 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [compiler-rt] [llvm] [XRay] Add `-fxray-default-options` to pass build-time defined XRay options (PR #116878)

https://github.com/mshockwave closed https://github.com/llvm/llvm-project/pull/116878 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [compiler-rt] [llvm] [XRay] Add `-fxray-default-options` to pass build-time defined XRay options (PR #116878)

mshockwave wrote: > Perhaps `__xray_default_options()` like `__asan_default_options()`? The user > would need to provide a `.o` that defines the function, but there is more > flexibility (e.g. the function can inspect a config file). I think this will be a better idea. It simplifies the design

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

@@ -22,6 +22,7 @@ def WriteIMul32 : SchedWrite;// 32-bit multiply on RV64I def WriteJmp: SchedWrite;// Jump def WriteJal: SchedWrite;// Jump and link def WriteJalr : SchedWrite;// Jump and link register +def WriteJmpReg : SchedWrit

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

@@ -0,0 +1,279 @@ +//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

@@ -0,0 +1,279 @@ +//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

https://github.com/mshockwave edited https://github.com/llvm/llvm-project/pull/117368 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -0,0 +1,83 @@ +//===-- xray_trampoline_riscv32.s --*- ASM -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier:

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -0,0 +1,296 @@ +//===-- xray_riscv.cpp *- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -453,11 +475,71 @@ bool RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) { SetupMachineFunction(MF); emitFunctionBody(); + // Emit the XRay table + emitXRayTable(); + if (EmittedOptionArch) RTS.emitDirectiveOptionPop(); return false; } +void R

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -0,0 +1,296 @@ +//===-- xray_riscv.cpp *- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -0,0 +1,97 @@ +//===-- xray_trampoline_riscv_common.s --*- ASM -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apa

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -0,0 +1,83 @@ +//===-- xray_trampoline_riscv64.s --*- ASM -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier:

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -0,0 +1,296 @@ +//===-- xray_riscv.cpp *- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -0,0 +1,296 @@ +//===-- xray_riscv.cpp *- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -0,0 +1,296 @@ +//===-- xray_riscv.cpp *- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -0,0 +1,296 @@ +//===-- xray_riscv.cpp *- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -0,0 +1,296 @@ +//===-- xray_riscv.cpp *- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -0,0 +1,296 @@ +//===-- xray_riscv.cpp *- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -0,0 +1,296 @@ +//===-- xray_riscv.cpp *- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -0,0 +1,296 @@ +//===-- xray_riscv.cpp *- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -0,0 +1,296 @@ +//===-- xray_riscv.cpp *- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -0,0 +1,296 @@ +//===-- xray_riscv.cpp *- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -0,0 +1,296 @@ +//===-- xray_riscv.cpp *- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -0,0 +1,296 @@ +//===-- xray_riscv.cpp *- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -57,6 +57,10 @@ static const int16_t cSledLength = 64; static const int16_t cSledLength = 8; #elif defined(__hexagon__) static const int16_t cSledLength = 20; +#elif SANITIZER_RISCV64 +static const int16_t cSledLength = 76; +#elif defined(__riscv) && (__riscv_xlen == 32) ---

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/117368 >From 599370a06008092f6aa883bf11600d0b66707bc0 Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Wed, 20 Nov 2024 14:37:57 -0800 Subject: [PATCH 1/2] [XRay][RISCV] RISCV support for XRay Add RISC-V support fo

[clang] [compiler-rt] [llvm] [XRay] Add `-fxray-default-options` to pass build-time defined XRay options (PR #116878)

mshockwave wrote: ping https://github.com/llvm/llvm-project/pull/116878 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

https://github.com/mshockwave edited https://github.com/llvm/llvm-project/pull/117368 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

https://github.com/mshockwave created https://github.com/llvm/llvm-project/pull/117368 Add RISC-V support for XRay. The RV64 implementation has been tested in both QEMU and in our production environment. Currently this requires D and C extensions, but since both RV64GC and RVA22/RVA23 are bec

[clang] [compiler-rt] [llvm] [XRay] Add `-fxray-default-options` to pass build-time defined XRay options (PR #116878)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/116878 >From 95ee4bd09aa48d4f0c2c4f5fc1e81e20cd57c7e2 Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Mon, 11 Nov 2024 11:40:43 -0800 Subject: [PATCH 1/2] [XRay] Add `-fxray-default-options` to pass build-time def

[clang] [compiler-rt] [llvm] [XRay] Add `-fxray-default-options` to pass build-time defined XRay options (PR #116878)

https://github.com/mshockwave created https://github.com/llvm/llvm-project/pull/116878 This flag specifies XRay options that will automatically be applied to the instrumented binaries during run-time even without setting `XRAY_OPTIONS`. This is useful in cases where setting the `XRAY_OPTIONS`

[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

https://github.com/mshockwave closed https://github.com/llvm/llvm-project/pull/115100 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

https://github.com/mshockwave approved this pull request. LGTM. I don't have any strong opinion on the CPU name https://github.com/llvm/llvm-project/pull/115100 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mail

[clang] [llvm] [mlir] [TableGen] Add const variants of accessors for backend (PR #106658)

https://github.com/mshockwave approved this pull request. > I propose the following next steps (once this is committed): this timeline looks fine, do you also want to add `[[deprecated]]` once the PSA is out? Also, I can help on other LLVM TableGen backends if they haven't been updated. https:

[clang] [llvm] [RISCV] Add Hazard3 CPU (PR #102452)

mshockwave wrote: > So for this particular PR, we just need a name people are happy with (perhaps > check if the vendor has a preference?). Something like `-mcpu=rp2350-hazard3` > perhaps? +1 on `-mcpu=rp2350-hazard3` over `-mcpu=raspberrypi-rp2350` because the former is more specific to the

[clang] [clang-tools-extra] [flang] [llvm] [mlir] [polly] [test]: fix filecheck annotation typos (PR #91854)

@@ -335,7 +335,7 @@ define void @cannot_sink_reduction(i32 %x, ptr %ptr, i64 %tc) { -; CHECK-NET: ret void +; CHECK-NEXT:ret void mshockwave wrote: please remove this line as it has been covered by line 333 (which was probably generated by UTC).

[clang] [clang-tools-extra] [flang] [llvm] [mlir] [polly] [test]: fix filecheck annotation typos (PR #91854)

@@ -96,7 +96,7 @@ for.end: ; preds = %for.end.loopexit, % ; Specify a smaller minimum VF (via `-epilogue-vectorization-minimum-VF=4`) and ; make sure the epilogue gets vectorized in that case. -; CHECK-MIN-D-LABLE: @f3 +; CHECK-MIN-D-L

[clang] [M68k] Change gcc register name from a7 to sp. (PR #87095)

https://github.com/mshockwave approved this pull request. Thank you! LGTM https://github.com/llvm/llvm-project/pull/87095 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [M68k] Change gcc register name from a7 to sp. (PR #87095)

mshockwave wrote: Is it possible use `TargetInfo::getGCCRegAliases` to model the aliasing between a7 and sp? Also, could you add a simple test? https://github.com/llvm/llvm-project/pull/87095 ___ cfe-commits mailing list cfe-commits@lists.llvm.org htt

[llvm] [clang] [RISCV] Add support for Smepmp 1.0 (PR #78489)

https://github.com/mshockwave closed https://github.com/llvm/llvm-project/pull/78489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Add support for Smepmp 1.0 (PR #78489)

@@ -116,6 +116,7 @@ // CHECK-NOT: __riscv_smaia {{.*$}} // CHECK-NOT: __riscv_ssaia {{.*$}} +// CHECK-NOT: __riscv_smepmp {{.*$}} mshockwave wrote: It's fixed now. https://github.com/llvm/llvm-project/pull/78489 __

[clang] [llvm] [RISCV] Add support for Smepmp 1.0 (PR #78489)

@@ -1047,6 +1048,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-SSAIA-EXT %s // CHECK-SSAIA-EXT: __riscv_ssaia 100{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32ismepmp1p0 -x c -E -dM %s \ +// RUN: -o - | FileCheck --che

[clang] [llvm] [RISCV] Add support for Smepmp 1.0 (PR #78489)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/78489 >From ab316ea2c76320ec2f044c43bb9f6ed82f6802c3 Mon Sep 17 00:00:00 2001 From: Min Hsu Date: Wed, 17 Jan 2024 10:28:14 -0800 Subject: [PATCH 1/4] [RISCV] Add support for Smepmp 1.0 Smepmp is a supervisor exten

[llvm] [clang] [RISCV] Add support for Smepmp 1.0 (PR #78489)

@@ -722,6 +722,11 @@ def FeatureStdExtSsaia "'Ssaia' (Advanced Interrupt Architecture Supervisor " "Level)", []>; +def FeatureStdExtSmepmp +: SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true", + "'Smepm

[llvm] [clang] [RISCV] Add support for Smepmp 1.0 (PR #78489)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/78489 >From a69c187716153c90f50b2859212a0e5af9102fd1 Mon Sep 17 00:00:00 2001 From: Min Hsu Date: Wed, 17 Jan 2024 10:28:14 -0800 Subject: [PATCH 1/3] [RISCV] Add support for Smepmp 1.0 Smepmp is a supervisor exten

[llvm] [clang] [RISCV] Add support for Smepmp 1.0 (PR #78489)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/78489 >From b4e14471727c59634daeec58ff60b8c32c5f2961 Mon Sep 17 00:00:00 2001 From: Min Hsu Date: Wed, 17 Jan 2024 10:28:14 -0800 Subject: [PATCH 1/3] [RISCV] Add support for Smepmp 1.0 Smepmp is a supervisor exten

[clang] [llvm] [RISCV] Add support for Smepmp 1.0 (PR #78489)

@@ -92,6 +92,7 @@ on support follow. ``M``Supported ``Smaia``Supported ``Ssaia``Supported + ``Smepmp`` Supported mshockwave wrote: Done. https://github.com/llvm/llvm-project/pull/78489 _

[clang] [llvm] [RISCV] Add support for Smepmp 1.0 (PR #78489)

@@ -56,6 +56,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = { {"smaia", {1, 0}}, {"ssaia", {1, 0}}, +{"smepmp", {1, 0}}, mshockwave wrote: Done. https://github.com/llvm/llvm-project/pull/78489 __

[clang] [llvm] [RISCV] Add support for Smepmp 1.0 (PR #78489)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/78489 >From b4e14471727c59634daeec58ff60b8c32c5f2961 Mon Sep 17 00:00:00 2001 From: Min Hsu Date: Wed, 17 Jan 2024 10:28:14 -0800 Subject: [PATCH 1/2] [RISCV] Add support for Smepmp 1.0 Smepmp is a supervisor exten

[llvm] [clang] [RISCV] Add support for Smepmp 1.0 (PR #78489)

@@ -716,6 +716,13 @@ def FeatureStdExtSmaia "AIA specifies for a hart, over all privilege levels.)", []>; +def FeatureStdExtSmepmp mshockwave wrote: > Can we keep smaia and ssaia together since they come from the

[llvm] [clang] [RISCV] Add support for Smepmp 1.0 (PR #78489)

mshockwave wrote: > Needs to be added to RISCVUsage.rst, and probably a note in the release docs > as well. It's done now. https://github.com/llvm/llvm-project/pull/78489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/

[clang] [llvm] [RISCV] Add support for Smepmp 1.0 (PR #78489)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/78489 >From 84783b38744bc2bb46cb8d62db206864709a5e22 Mon Sep 17 00:00:00 2001 From: Min Hsu Date: Wed, 17 Jan 2024 10:28:14 -0800 Subject: [PATCH 1/2] [RISCV] Add support for Smepmp 1.0 Smepmp is a supervisor exten

[compiler-rt] [flang] [clang-tools-extra] [clang] [llvm] [Legalizer] Expand fmaximum and fminimum (PR #67301)

@@ -523,9 +523,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom); setOperationAction(ISD::FP16_TO_FP, MVT::f32, Custom); -if (Subtarget.hasStdExtZfa()) +if (Subtarget.hasStdExtZfa()) {

[flang] [clang-tools-extra] [compiler-rt] [llvm] [clang] [Legalizer] Expand fmaximum and fminimum (PR #67301)

https://github.com/mshockwave edited https://github.com/llvm/llvm-project/pull/67301 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang-tools-extra] [llvm] [clang] [flang] [compiler-rt] [Legalizer] Expand fmaximum and fminimum (PR #67301)

https://github.com/mshockwave approved this pull request. LGTM. It will be great if you could add RISCV test too, but please don't let this block you. https://github.com/llvm/llvm-project/pull/67301 ___ cfe-commits mailing list cfe-commits@lists.llvm.

[clang] [Clang][Driver][LTO] Fix empty stats filename when in LTO mode (PR #71197)

https://github.com/mshockwave closed https://github.com/llvm/llvm-project/pull/71197 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][Driver][LTO] Fix empty stats filename when in LTO mode (PR #71197)

@@ -535,7 +535,15 @@ void tools::gnutools::Linker::ConstructJob(Compilation &C, const JobAction &JA, if (D.isUsingLTO()) { assert(!Inputs.empty() && "Must have at least one input."); -addLTOOptions(ToolChain, Args, CmdArgs, Output, Inputs[0], +// Find the first

[clang] [Clang][Driver][LTO] Fix empty stats filename when in LTO mode (PR #71197)

@@ -20,6 +20,8 @@ // CHECK-INVALID: invalid value 'bla' in '-save-stats=bla' // RUN: %clang -target x86_64-linux-unknown -save-stats -flto -o obj/dir/save-stats.exe %s -### 2>&1 | FileCheck %s -check-prefix=CHECK-LTO +// Previously `-plugin-opt=stats-file` would use empty fil

[clang] [Clang][Driver][LTO] Fix empty stats filename when in LTO mode (PR #71197)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/71197 >From 8d5acb56b364648d1abd6bfff6815af71e131d6e Mon Sep 17 00:00:00 2001 From: Min Hsu Date: Thu, 2 Nov 2023 17:26:17 -0700 Subject: [PATCH 1/2] [Clang][Driver][LTO] Fix empty stats filename when in LTO mode

[clang] [Clang][Driver][LTO] Change the filename format for LTO'd stats file (PR #70242)

mshockwave wrote: > I can understand the rationale, but adding this special case feels stranger > to me.. I'm fine with not having a special file extension for LTO'd stats file, hence closing this PR. That said, it would be really helpful if you could help me to review a related PR #71197 .

[clang] [Clang][Driver][LTO] Change the filename format for LTO'd stats file (PR #70242)

https://github.com/mshockwave closed https://github.com/llvm/llvm-project/pull/70242 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][Driver][LTO] Fix empty stats filename when in LTO mode (PR #71197)

https://github.com/mshockwave created https://github.com/llvm/llvm-project/pull/71197 Previously, if a linker flag (i.e. -Wl) is presented before any input filenames, Gnu driver would use the InputInfo object of that flag to generate stats filename for LTO backend, causing an empty filename. T

[clang] [Clang][Driver][LTO] Change the filename format for LTO'd stats file (PR #70242)

https://github.com/mshockwave created https://github.com/llvm/llvm-project/pull/70242 Use ".ld.stats" instead of ".stats" for stats file generated by LTO backend. The new extension makes it easier to search for LTO'd stats file and be consistent with LTO'd optimization remarks files' naming c

[clang] [Clang][LTO][GISel] Propagate `-fglobal-siel` to LTO (PR #69747)

https://github.com/mshockwave closed https://github.com/llvm/llvm-project/pull/69747 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][LTO][GISel] Propagate `-fglobal-siel` to LTO (PR #69747)

@@ -694,6 +694,16 @@ void tools::addLTOOptions(const ToolChain &ToolChain, const ArgList &Args, CmdArgs.push_back(Args.MakeArgString(Twine(PluginOptPrefix) + ParallelismOpt + Parallelism)); + // Pass down GlobalISel options. + if

[clang] [Clang][LTO][GISel] Propagate `-fglobal-siel` to LTO (PR #69747)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/69747 >From 8abc9204d4148f1b224623ac54d5f58e2ab04e6b Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Fri, 20 Oct 2023 11:03:30 -0700 Subject: [PATCH 1/2] [Clang][LTO][GISel] Propagate `-fglobal-siel` to LTO Transl

[clang] [Clang][LTO][GISel] Propagate `-fglobal-siel` to LTO (PR #69747)

https://github.com/mshockwave created https://github.com/llvm/llvm-project/pull/69747 Translate `-fglobal-isel` to `-plugin-opt=-global-isel=1`. >From 8abc9204d4148f1b224623ac54d5f58e2ab04e6b Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Fri, 20 Oct 2023 11:03:30 -0700 Subject: [PATCH] [Cla

[clang] [RISCV][GISel] Add ISel supports for SHXADD from Zba extension (PR #67863)

https://github.com/mshockwave closed https://github.com/llvm/llvm-project/pull/67863 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang-tools-extra] [RISCV][GISel] Add ISel supports for SHXADD from Zba extension (PR #67863)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/67863 >From 08f77d6a53dadd4c136b92fcb60700fd7389eeb3 Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Fri, 29 Sep 2023 15:17:43 -0700 Subject: [PATCH 1/8] [RISCV][GISel] Add ISel supports for SHXADD from Zba extens

[clang] [RISCV][GISel] Add ISel supports for SHXADD from Zba extension (PR #67863)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/67863 >From 08f77d6a53dadd4c136b92fcb60700fd7389eeb3 Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Fri, 29 Sep 2023 15:17:43 -0700 Subject: [PATCH 1/8] [RISCV][GISel] Add ISel supports for SHXADD from Zba extens

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