@@ -0,0 +1,22 @@
+; RUN: not llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s
-o /dev/null 2>&1 | FileCheck %s
+; RUN: not llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s
-o /dev/null 2>&1 | FileCheck %s
+; RUN: not %if spirv-tools %{ llc -O0 -
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@@ -0,0 +1,22 @@
+; RUN: not llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s
-o /dev/null 2>&1 | FileCheck %s
+; RUN: not llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s
-o /dev/null 2>&1 | FileCheck %s
+; RUN: not %if spirv-tools %{ llc -O0 -
@@ -3030,6 +3031,15 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
return selectExtInst(ResVReg, ResType, I, CL::fract, GL::Fract);
case Intrinsic::spv_normalize:
return selectExtInst(ResVReg, ResType, I, CL::normalize, GL::Normalize);
+ case In
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farzonl wrote:
> Will a follow-up issue be created to move the useful `Sema` helpers into a
> common file?
I'm fine if you want to do this as a follow up.
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farzonl wrote:
> This pr LGTM once the graceful exit comment is handled.
>
> With respect to [this
> comment](https://github.com/llvm/llvm-project/pull/122992#discussion_r1917127000).
> Is the final solution to just gracefully exit or is this an intermediate
> step and an issue will be used t
@@ -0,0 +1,32 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+
+// RUN: %clang_cc1 -O1 -triple spirv-pc-vulkan-compute %s -emit-llvm -o - |
FileCheck %s
farzonl wrote:
The clang codgen tests should be suf
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/122839
>From fb1c27ea34d42b9c141fe9a2d1a5ad8584dfa0a0 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 9 Jan 2025 19:19:27 -0500
Subject: [PATCH 1/7] [SPIRV] add pre legalization instruction combine - Add
the bo
farzonl wrote:
> @farzonl Was enabled GISelCSEAnalysisWrapperPass a reason of problems with
> inline_asm?
It was CSE and The combiner pass does dead code elimination. I removed one and
turned the other off. Their is a bug in the SPIRVPreLegalizer where its
expecting a matching number of inlin
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/122839
>From fb1c27ea34d42b9c141fe9a2d1a5ad8584dfa0a0 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 9 Jan 2025 19:19:27 -0500
Subject: [PATCH 1/6] [SPIRV] add pre legalization instruction combine - Add
the bo
https://github.com/farzonl ready_for_review
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>From fb1c27ea34d42b9c141fe9a2d1a5ad8584dfa0a0 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 9 Jan 2025 19:19:27 -0500
Subject: [PATCH 1/5] [SPIRV] add pre legalization instruction combine - Add
the bo
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/122839
>From fb1c27ea34d42b9c141fe9a2d1a5ad8584dfa0a0 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 9 Jan 2025 19:19:27 -0500
Subject: [PATCH 1/5] [SPIRV] add pre legalization instruction combine - Add
the bo
@@ -0,0 +1,140 @@
+; RUN: llc -mtriple=spirv-unknown-unknown -debug-pass=Structure < %s -o
/dev/null 2>&1 | \
farzonl wrote:
I'm using this test case to help me figure out why I'm seeing an assert fire in
`SPV_INTEL_inline_assembly/inline_asm.ll`. I can remove
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>From fb1c27ea34d42b9c141fe9a2d1a5ad8584dfa0a0 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 9 Jan 2025 19:19:27 -0500
Subject: [PATCH 1/4] [SPIRV] add pre legalization instruction combine - Add
the bo
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@@ -2944,6 +2944,10 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
return selectExtInst(ResVReg, ResType, I, CL::fract, GL::Fract);
case Intrinsic::spv_normalize:
return selectExtInst(ResVReg, ResType, I, CL::normalize, GL::Normalize);
+ case In
@@ -0,0 +1,260 @@
+
+//===-- SPIRVPreLegalizerCombiner.cpp - combine legalization *- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
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https://github.com/llvm/llvm-project/pull/122839
>From fb1c27ea34d42b9c141fe9a2d1a5ad8584dfa0a0 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 9 Jan 2025 19:19:27 -0500
Subject: [PATCH 1/4] [SPIRV] add pre legalization instruction combine - Add
the bo
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@@ -1688,13 +1688,21 @@ static bool CheckVectorElementCallArgs(Sema *S,
CallExpr *TheCall) {
auto *VecTyA = ArgTyA->getAs();
SourceLocation BuiltinLoc = TheCall->getBeginLoc();
+ bool AllBArgAreVectors = true;
for (unsigned i = 1; i < TheCall->getNumArgs(); ++i) {
farzonl wrote:
> > > > I see also some problems in test cases
> > >
> > >
> > > @VyacheslavLevytskyy the SPIRV test case failures are not related to my
> > > change. They are also failing on main.
> >
> >
> > I will check now. For one the reason is clear, #123191
>
> I can't reproduce two o
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/122839
>From 67d9c51dbd0cf78f4cf622f655adb76d519b774b Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 9 Jan 2025 19:19:27 -0500
Subject: [PATCH 1/3] [SPIRV] add pre legalization instruction combine - Add
the bo
farzonl wrote:
> I see also some problems in test cases
@VyacheslavLevytskyy the SPIRV test case failures are not related to my change.
They are also failing on main.
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>From 7ac4da8f3a80225300f178eb9aec75d46cc4110d Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Mon, 13 Jan 2025 14:26:23 -0500
Subject: [PATCH 1/2] [NFC] Fixed Diagnostics that assumed only two arguments
---
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>From ae1a274f856518d710cffba324c603d9e95adf54 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 9 Jan 2025 19:19:27 -0500
Subject: [PATCH 1/2] [SPIRV] add pre legalization instruction combine - Add
the bo
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@@ -0,0 +1,33 @@
+; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
farzonl wrote:
This won't be a problem for opencl because they don't have a reflect api to
trigger this crash. This could be a problem if folks try to target
spirv32/spirv64
@@ -51,6 +51,38 @@ bool SemaSPIRV::CheckSPIRVBuiltinFunctionCall(unsigned
BuiltinID,
TheCall->setType(RetTy);
break;
}
+ case SPIRV::BI__builtin_spirv_reflect: {
+if (SemaRef.checkArgCount(TheCall, 2))
+ return true;
+
+ExprResult A = TheCall->getArg(0)
@@ -0,0 +1,195 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// RUN: %clang_cc1 -finclude-default-header -triple \
+// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \
+// RUN: -emit-llvm -O1 -o - | FileChe
@@ -0,0 +1,33 @@
+// RUN: %clang_cc1 -finclude-default-header -triple
dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only
-disable-llvm-passes -verify
+
+float test_no_second_arg(float2 p0) {
+ return reflect(p0);
+ // expected-error@-1 {{no matching function
@@ -0,0 +1,195 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// RUN: %clang_cc1 -finclude-default-header -triple \
+// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \
+// RUN: -emit-llvm -O1 -o - | FileChe
@@ -0,0 +1,195 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// RUN: %clang_cc1 -finclude-default-header -triple \
+// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \
+// RUN: -emit-llvm -O1 -o - | FileChe
@@ -0,0 +1,195 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// RUN: %clang_cc1 -finclude-default-header -triple \
+// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \
+// RUN: -emit-llvm -O1 -o - | FileChe
@@ -0,0 +1,195 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// RUN: %clang_cc1 -finclude-default-header -triple \
+// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \
+// RUN: -emit-llvm -O1 -o - | FileChe
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>From ae1a274f856518d710cffba324c603d9e95adf54 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 9 Jan 2025 19:19:27 -0500
Subject: [PATCH] [SPIRV] add pre legalization instruction combine - Add the
boiler
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@@ -1,33 +1,44 @@
-; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
farzonl wrote:
changed line endings from crlf to lf.
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https://github.com/farzonl created
https://github.com/llvm/llvm-project/pull/122772
In the below code B varies over the arg list via a loop. However, the
diagnostics do not vary with the loop.
Fix so that diagnostics can vary with B.
>From 9df164c835e7df5bf4ea863bd9735bb0e456cb6c Mon Sep 17 0
https://github.com/farzonl approved this pull request.
https://github.com/llvm/llvm-project/pull/122202
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>From 9a2315c356fa0d1c22b5a9dfeb9d1608baf6a93d Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 9 Jan 2025 14:55:40 -0500
Subject: [PATCH 1/2] [HLSL] Implement the HLSL distance intrinsic - Hook of
SPIRV
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farzonl wrote:
Ok going to try to merge again. no more test failure for length.hlsl in
buildkite. only failing test was:
`Clang.SemaSYCL/sycl-kernel-entry-point-attr-appertainment.cpp`
https://github.com/llvm/llvm-project/pull/122337
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https://github.com/llvm/llvm-project/pull/122337
>From a7323e97f09db476e622bee9800e1b3e15441beb Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 9 Jan 2025 13:11:52 -0500
Subject: [PATCH 1/3] [HLSL] Move length support out of the DirectX Backend
(#1216
farzonl wrote:
> @llvm-beanz I'm really confused what is going on here The length test case
> passes in the github action:
> https://github.com/llvm/llvm-project/actions/runs/12699150463?pr=122337 It
> passes locally on:
>
> 1. MacOS Intel (Intel(R) Core(TM) i9-8950HK CPU @ 2.90GHz)
> 2. MacO
farzonl wrote:
@llvm-beanz I'm really confused what is going on here
The length test case passes in the github action:
https://github.com/llvm/llvm-project/actions/runs/12699150463?pr=122337
It passes locally on:
1. MacOS Intel (Intel(R) Core(TM) i9-8950HK CPU @ 2.90GHz)
2. MacOS Apple M3 Max
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@@ -871,6 +871,34 @@ float3 degrees(float3);
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_degrees)
float4 degrees(float4);
+//===--===//
+// distance builtins
+//===--
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/122337
>From a7323e97f09db476e622bee9800e1b3e15441beb Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 9 Jan 2025 13:11:52 -0500
Subject: [PATCH 1/2] [HLSL] Move length support out of the DirectX Backend
(#1216
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/122357
>From 88e0035ca1c5b326a1579bc777c926c3c48c5c89 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 9 Jan 2025 14:55:40 -0500
Subject: [PATCH] [HLSL] Implement the HLSL distance intrinsic - Hook of SPIRV
buil
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@@ -871,6 +871,34 @@ float3 degrees(float3);
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_degrees)
float4 degrees(float4);
+//===--===//
+// distance builtins
+//===--
@@ -871,6 +871,34 @@ float3 degrees(float3);
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_degrees)
float4 degrees(float4);
+//===--===//
+// distance builtins
+//===--
https://github.com/farzonl created
https://github.com/llvm/llvm-project/pull/122357
- Hook of SPIRV builtin
- Implement Distance as length(X - Y)
>From 73e0203dafcd3d237b02e6a3bce0448df92231b7 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 9 Jan 2025 14:55:40 -0500
Subject: [PATCH] [HL
farzonl wrote:
> Does this fix a test failure?
No failures. We would need to have tests for all intrinsics that if its not SM
6.2 or greater uses of half would error, but we never did that for any of the
other intrinsics so we should probably discuss what the test coverage should be
and appl
https://github.com/farzonl created
https://github.com/llvm/llvm-project/pull/122337
- attribute keeps getting deleted on bad rebases
>From 0f0b75dffaefc3460ae8aad7effa75e844ab29ee Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 9 Jan 2025 13:55:33 -0500
Subject: [PATCH] [HLSL] Add 6.2 S
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/117240
>From c6a696373a2a6a51b8e74f5bed549328c21b0155 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 21 Nov 2024 14:46:31 -0500
Subject: [PATCH] [HLSL] Implement a header only distance intrinsic
Addressing RFC
https://github.com/farzonl closed
https://github.com/llvm/llvm-project/pull/121611
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>From a2ba98f57f015e612d3a9df5b2b50a468f21b55d Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Tue, 17 Dec 2024 18:30:23 -0500
Subject: [PATCH] [HLSL] Move length intrinsic to the header
---
clang/include/cl
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/117240
>From 271141588db106f888dd6abb3ad7da41732a4f52 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 21 Nov 2024 14:46:31 -0500
Subject: [PATCH] [HLSL] Implement a header only distance intrinsic
Addressing RFC
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/117240
>From 89507233b8b7ac859e1abbedb97e69574e54dfc8 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 21 Nov 2024 14:46:31 -0500
Subject: [PATCH] [HLSL] Implement a header only distance intrinsic
Addressing RFC
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https://github.com/llvm/llvm-project/pull/121842
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https://github.com/farzonl created
https://github.com/llvm/llvm-project/pull/121842
Fix Tablegen typo to indicate SPIRV and not HLSL
Fix miscellaneous test case typos.
>From 269b25fae5ea78c3c851bd041966d2eff4c01eb1 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Mon, 6 Jan 2025 16:45:14 -050
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/120367
>From e46ef6592aec6a1a0b3f7509eb260bb1e9bda692 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Wed, 18 Dec 2024 01:44:42 -0500
Subject: [PATCH 1/3] [Clang] Add float type support to __builtin_reduce_add
and _
farzonl wrote:
> I'd definitely suggest you reduce the scope - maybe always expand the
> reduction serially in the frontend and not create the llvm intrinsic at all?
Between @Il-Capitano and @RKSimon comments I think it makes the most sense to
do a sequential reduction in the frontend. Thats
farzonl wrote:
> Thanks for the description. I would find some justification useful even if it
> just repeats the reasoning we've established for all such changes.
@pow2clk added a justification.
https://github.com/llvm/llvm-project/pull/121611
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https://github.com/llvm/llvm-project/pull/121611
>From 7044e856bcd89de7318f7f4970c53beb0fc4 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Tue, 17 Dec 2024 18:30:23 -0500
Subject: [PATCH 1/3] [HLSL] Move length intrinsic to the header
---
clang/includ
@@ -1,32 +1,53 @@
-// RUN: %clang_cc1 -finclude-default-header -triple
dxil-pc-shadermodel6.6-library %s -fnative-half-type -disable-llvm-passes
-verify -verify-ignore-unexpected
-
+// RUN: %clang_cc1 -finclude-default-header -triple
dxil-pc-shadermodel6.6-library %s -fnative-h
@@ -1,73 +1,151 @@
-// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \
-// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \
-// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s \
-// RUN: --check-prefixes=CHECK,NATIVE_HALF
-// RUN: %clang_cc1 -
@@ -1297,27 +1297,16 @@ float4 lerp(float4, float4, float4);
///
/// Length is based on the following formula: sqrt(x[0]^2 + x[1]^2 + ...).
-_HLSL_16BIT_AVAILABILITY(shadermodel, 6.2)
-_HLSL_BUILTIN_ALIAS(__builtin_hlsl_length)
-half length(half);
-_HLSL_16BIT_AVAILABILITY(sha
@@ -33,6 +41,21 @@ constexpr enable_if_t bit_cast(T
F) {
return __builtin_bit_cast(U, F);
}
+template
+constexpr enable_if_t::value || is_same::value, T>
+length_impl(T X) {
+ return __builtin_elementwise_abs(X);
+}
+
+template
+enable_if_t::value || is_same::value, T>
+
https://github.com/farzonl edited
https://github.com/llvm/llvm-project/pull/121611
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@@ -33,6 +41,21 @@ constexpr enable_if_t bit_cast(T
F) {
return __builtin_bit_cast(U, F);
}
+template
+constexpr enable_if_t::value || is_same::value, T>
+length_impl(T X) {
+ return __builtin_elementwise_abs(X);
+}
+
+template
+enable_if_t::value || is_same::value, T>
+
https://github.com/farzonl edited
https://github.com/llvm/llvm-project/pull/121611
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@@ -33,6 +41,23 @@ constexpr enable_if_t bit_cast(T
F) {
return __builtin_bit_cast(U, F);
}
+template
+constexpr enable_if_t::value || is_same::value, T>
+length_impl(T X) {
+ return __builtin_elementwise_abs(X);
+}
+
+template
+enable_if_t::value || is_same::value, T>
+
https://github.com/farzonl closed
https://github.com/llvm/llvm-project/pull/121598
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https://github.com/farzonl edited
https://github.com/llvm/llvm-project/pull/121598
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farzonl wrote:
@Endilll It looks like you are the code owner for
`/clang/include/clang/Sema/Sema.h` Are you happy with these changes?
https://github.com/llvm/llvm-project/pull/121598
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https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/121598
>From 74f86806bbdf1397973f70043ce0856bc6a4a4a7 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Fri, 3 Jan 2025 14:52:31 -0500
Subject: [PATCH 1/2] [SPIRV] Add Target Builtins using Distance ext as an
example
@@ -20440,6 +20442,26 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
}
}
+Value *CodeGenFunction::EmitSPIRVBuiltinExpr(unsigned BuiltinID,
+ const CallExpr *E) {
+ switch (BuiltinID) {
+ case SPIRV::BI__bui
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/121611
>From 2de0c4911dfbc67b9492eb4f13bcd162e79c3d37 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Tue, 17 Dec 2024 18:30:23 -0500
Subject: [PATCH 1/2] [HLSL] Move length intrinsic to the header
---
clang/includ
https://github.com/farzonl edited
https://github.com/llvm/llvm-project/pull/121611
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@@ -1,73 +1,151 @@
-// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \
-// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \
-// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s \
-// RUN: --check-prefixes=CHECK,NATIVE_HALF
-// RUN: %clang_cc1 -
@@ -33,6 +41,23 @@ constexpr enable_if_t bit_cast(T
F) {
return __builtin_bit_cast(U, F);
}
+template
+constexpr enable_if_t::value || is_same::value, T>
+length_impl(T X) {
+ return __builtin_elementwise_abs(X);
+}
+
+template
+enable_if_t::value || is_same::value, T>
+
https://github.com/farzonl created
https://github.com/llvm/llvm-project/pull/121611
None
>From 2de0c4911dfbc67b9492eb4f13bcd162e79c3d37 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Tue, 17 Dec 2024 18:30:23 -0500
Subject: [PATCH 1/2] [HLSL] Move length intrinsic to the header
---
clang/
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