[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -111,9 +115,51 @@ void RISCVABIInfo::appendAttributeMangling(StringRef AttrStr, } void RISCVABIInfo::computeInfo(CGFunctionInfo &FI) const { + unsigned ABIVLen; + switch (FI.getExtInfo().getCC()) { + default: +ABIVLen = 1; 4vtomat wrote: I see, ori

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -1953,7 +1953,7 @@ class alignas(TypeAlignment) Type : public ExtQualsTypeCommonBase { /// Extra information which affects how the function is called, like /// regparm and the calling convention. LLVM_PREFERRED_TYPE(CallingConv) -unsigned ExtInfo : 13; +

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -3013,6 +3013,7 @@ enum CXCallingConv { CXCallingConv_M68kRTD = 19, CXCallingConv_PreserveNone = 20, CXCallingConv_RISCVVectorCall = 21, + CXCallingConv_RISCVVLSCall = 22, 4vtomat wrote: Let me clarify this, do you mean using different calling conven

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -3013,6 +3013,7 @@ enum CXCallingConv { CXCallingConv_M68kRTD = 19, CXCallingConv_PreserveNone = 20, CXCallingConv_RISCVVectorCall = 21, + CXCallingConv_RISCVVLSCall = 22, 4vtomat wrote: I see, let me change it to this approach~ https://github.com/l

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/100346 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

4vtomat wrote: Update: 1. Handle struct of fixed-length vectors 2. Remove `-mriscv-abi-vlen=N` option https://github.com/llvm/llvm-project/pull/100346 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listin

[clang] [clang][RISCV] Remove unneeded RISCV tuple code (PR #121024)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/121024 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Remove unneeded RISCV tuple code (PR #121024)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/121024 These code are no longer needed because we've modeled tuple type using target extension type rather than structure of scalable vectors. >From 72401387483dd5839d09f508c1bc988325c5e456 Mon Sep 17 00:00:00 2001 Fr

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

4vtomat wrote: > Is there a downside if we just recommend people > `__attribute__((riscv_vls_cc(MY_LIBRARY_VLEN)))`, then put > `-DMY_LIBRARY_VLEN=128` on the command-line? It's about the same complexity > as -mriscv-abi-vlen, and it's much more obvious that what you're doing is > fragile. A

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/100346 >From 1c8201daa6925cac510ff8751ffd79a6b95f2315 Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Sun, 21 Jul 2024 09:49:11 -0700 Subject: [PATCH 1/4] [RISCV][VLS] Support RISCV VLS calling convention This patch a

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -8031,6 +8034,28 @@ static bool handleFunctionTypeAttr(TypeProcessingState &state, ParsedAttr &attr, CallingConv CCOld = fn->getCallConv(); Attr *CCAttr = getCCTypeAttr(S.Context, attr); + if (attr.getKind() == ParsedAttr::AT_RISCVVLSCC) { +// If the riscv_abi_vle

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

4vtomat wrote: > Is there discussion somewhere of why you need a command-line flag? > ABI-modifying flags tend to be dangerous to work with. It's hard to ensure > that all code is compiled with the same flags, and if the user messes up, the > compiler silently generates broken code. Yeah, it'

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -32,3 +36,39 @@ vint32m1_t test_no_vector_cc_attr(vint32m1_t input, int32_t *base, size_t vl) { __riscv_vse32_v_i32m1(base, val, vl); return ret; } + +// CHECK-LLVM: define dso_local void @test_vls_no_cc(i128 noundef %arg.coerce) +// CHECK-LLVM-ABI-VLEN: define dso_loca

[clang] [llvm] [RISCV] Support `svukte` extension (PR #115657)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/115657 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support `svukte` extension (PR #115657)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/115657 >From 0c95051b617be8fd242e317c442a1881d5f28034 Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Mon, 5 Aug 2024 11:59:52 +0800 Subject: [PATCH 1/4] [RISCV] Support `svukte` extension This is the extension for "A

[clang] [clang][RISCV] __riscv_v_intrinsic macro doesn't need zve32x (PR #117356)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/117356 This macro is used to check if compiler supports RVV intrinsics, so it should be defined no matter vector is enabled or not. Resolved https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/376 >From a29150c5

[clang] [clang][RISCV] Bump RVV intrinsic to version 1.0 (PR #116597)

4vtomat wrote: > Considering the define is guarded behind `if > (ISAInfo->hasExtension("zve32x"))`, this doesn't seem to implement: > [riscv-non-isa/rvv-intrinsic-doc#382](https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/382) I'll post another patch for this, thanks! https://github.com

[clang] [clang][RISCV] Bump RVV intrinsic to version 1.0 (PR #116597)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/116597 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support `svukte` extension (PR #115657)

@@ -330,6 +329,9 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-smctr``, ``experimental-ssctr`` LLVM implements the `1.0-rc3 specification `__.

[clang] [llvm] [RISCV] Support `svukte` extension (PR #115657)

@@ -158,6 +158,7 @@ on support follow. ``Svinval`` Assembly Support ``Svnapot`` Assembly Support ``Svpbmt``Supported + ``Svukte``Supported 4vtomat wrote: I thought it's frozen, hasn't it? https://github.com/llvm/

[clang] [clang][RISCV] Bump RVV intrinsic to version 1.0 (PR #116597)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/116597 >From 5addb1d33fc195b084a4869217d763abb1eef1af Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Mon, 18 Nov 2024 02:02:34 -0800 Subject: [PATCH 1/2] [clang][RISCV] Bump RVV intrinsic to version 1.0 The spec: ht

[clang] [llvm] [RISCV] Support `svukte` extension (PR #115657)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/115657 >From 0c95051b617be8fd242e317c442a1881d5f28034 Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Mon, 5 Aug 2024 11:59:52 +0800 Subject: [PATCH 1/2] [RISCV] Support `svukte` extension This is the extension for "A

[clang] [llvm] [RISCV] Support `svukte` extension (PR #115657)

4vtomat wrote: > RISCVUsage.rst Updated! https://github.com/llvm/llvm-project/pull/115657 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Bump RVV intrinsic to version 1.0 (PR #116597)

4vtomat wrote: > Add ReleaseNote to Clang? Updated! https://github.com/llvm/llvm-project/pull/116597 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Bump RVV intrinsic to version 1.0 (PR #116597)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/116597 The spec: https://github.com/riscv-non-isa/rvv-intrinsic-doc/releases/tag/v1.0.0-rc4 Also remove __riscv_v_intrinsic_overloading since it's no longer in spec, the overloading intrinsics should be also enabled wh

[clang] [llvm] [RISCV] Support `svukte` extension (PR #115657)

https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/115657 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support `svukte` extension (PR #115657)

4vtomat wrote: The spec is frozen, but the PR is still version 0.3, I'll follow the spec to update the version. https://github.com/llvm/llvm-project/pull/115657 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mai

[clang] [llvm] [RISCV] Support `svukte` extension (PR #115657)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/115657 This is the extension for "Address-Independent Latency of User-Mode Faults to Supervisor Addresses". Spec: https://github.com/riscv/riscv-isa-manual/pull/1564 The spec states that the `svukte` depends on `sv39`,

[clang] [RISCV][Clang] Add RequiredFeatures to zvfh intrinsics (PR #115436)

https://github.com/4vtomat approved this pull request. Somehow I missed [this](https://github.com/llvm/llvm-project/issues/94306) issue, thanks for fixing this! https://github.com/llvm/llvm-project/pull/115436 ___ cfe-commits mailing list cfe-commits@

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/100346 >From 1c8201daa6925cac510ff8751ffd79a6b95f2315 Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Sun, 21 Jul 2024 09:49:11 -0700 Subject: [PATCH 1/2] [RISCV][VLS] Support RISCV VLS calling convention This patch a

[clang] [RISCV][Clang] Reuse RVVOutBuiltinSet multiclass for builtin vfrsqrt7. NFC (PR #115269)

https://github.com/4vtomat approved this pull request. LGTM, thanks! https://github.com/llvm/llvm-project/pull/115269 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -317,38 +323,60 @@ ABIArgInfo RISCVABIInfo::coerceAndExpandFPCCEligibleStruct( // Fixed-length RVV vectors are represented as scalable vectors in function // args/return and must be coerced from fixed vectors. -ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty) const {

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -317,38 +323,60 @@ ABIArgInfo RISCVABIInfo::coerceAndExpandFPCCEligibleStruct( // Fixed-length RVV vectors are represented as scalable vectors in function // args/return and must be coerced from fixed vectors. -ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty) const {

[clang] [clang][RISCV] Extend intrinsic size check variable from 16 -> 32 bits. NFC (PR #111481)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/111481 >From 832a7576ad864aeaf8f183b631d1d805497aebf5 Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Mon, 7 Oct 2024 22:03:43 -0700 Subject: [PATCH 1/2] [clang][RISCV] Extend intrinsic size check variable from 16 ->

[clang] [clang][RISCV] Extend intrinsic size check variable from 16 -> 32 bits. NFC (PR #111481)

4vtomat wrote: > I think we need to change > > ``` > struct RVVOverloadIntrinsicDef { > // Indexes of RISCVIntrinsicManagerImpl::IntrinsicList. > SmallVector Indexes; > }; > ``` > > and > > ``` > // Mapping function name to index of IntrinsicList. > StringMap Intrinsics; > ``` > > Tho

[clang] [clang][RISCV] Correct the SEW operand of indexed/fault only first segment intrinsics (PR #111476)

4vtomat wrote: > Make sense to me. It was wrong since when? It's from the tuple interface change patches, https://github.com/llvm/llvm-project/pull/97992. https://github.com/llvm/llvm-project/pull/111476 ___ cfe-commits mailing list cfe-commits@lists

[clang] [clang][RISCV] Extend intrinsic size check variable from 16 -> 32 bits. NFC (PR #111481)

4vtomat wrote: > > > Why don’t any of our lit tests that use every intrinsic catch it? > > > > > > Somehow if we add more "target-feature" the intrinsics increase, I'm not > > sure why. For example: > > > > > > ``` > > > test.c > > > > > > #include "riscv_vector.h" > > > vfloat16mf4

[clang] [clang][RISCV] Extend intrinsic size check variable from 16 -> 32 bits. NFC (PR #111481)

4vtomat wrote: > Why don’t any of our lit tests that use every intrinsic catch it? Somehow if we add more "target-feature" the intrinsics increase, I'm not sure why. For example: ``` test.c #include "riscv_vector.h" vfloat16mf4x7_t test_vlseg7e16ff_v_f16mf4x7(const _Float16 *base, size_t *n

[clang] [clang][RISCV] Make the index of riscv_tuple_extract and riscv_tuple_insert be truncated rather than zero extended (PR #111466)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/111466 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Extend intrinsic size check variable from 16 -> 32 bits. NFC (PR #111481)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/111481 We currently have over 67000 intrinsics, uint16_t will overflow. >From f6a27f7de2459e22961555054b92a61a0e7ededf Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Mon, 7 Oct 2024 22:03:43 -0700 Subject: [PATCH] [

[clang] [clang][RISCV] Make the index of riscv_tuple_extract and riscv_tuple_insert be truncated rather than zero extended (PR #111466)

4vtomat wrote: > test? Added! https://github.com/llvm/llvm-project/pull/111466 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Make the index of riscv_tuple_extract and riscv_tuple_insert be truncated rather than zero extended (PR #111466)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/111466 >From cd79ab5782175de38adfa6b171270766d2544204 Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Mon, 7 Oct 2024 19:33:41 -0700 Subject: [PATCH] [clang][RISCV] Make the index of riscv_tuple_extract and riscv_tupl

[clang] [clang][RISCV] Make the index of riscv_tuple_extract and riscv_tuple_insert be truncated rather than zero extended (PR #111466)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/111466 It's illegal if the index is 64 bits and is zero-extend to 32 bits. >From 6e11ffa9585cf189382501d44915f211abd4be46 Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Mon, 7 Oct 2024 19:33:41 -0700 Subject: [PATCH

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/100346 >From 15161b0b7637d52b6285624a4bf9f52a6664082c Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Sun, 21 Jul 2024 09:49:11 -0700 Subject: [PATCH 1/7] [RISCV][VLS] Support RISCV VLS calling convention This patch a

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/106914 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/106914 >From aff3876f0d983413d5538929e11885111079e566 Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Sun, 1 Sep 2024 09:35:34 -0700 Subject: [PATCH] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set R

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/106914 >From be771da74a7663d56cdf850c10b4daa47c087bcc Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Sun, 1 Sep 2024 09:35:34 -0700 Subject: [PATCH 1/2] [RISCV][VCIX] Precommit test --- llvm/test/CodeGen/RISCV/inlin

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

4vtomat wrote: > Thanks everyone! 😄 Is there anything still blocking us from merging this? Actually no, let me merge it later today, thanks! https://github.com/llvm/llvm-project/pull/106914 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/106914 >From be771da74a7663d56cdf850c10b4daa47c087bcc Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Sun, 1 Sep 2024 09:35:34 -0700 Subject: [PATCH 1/3] [RISCV][VCIX] Precommit test --- llvm/test/CodeGen/RISCV/inlin

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

@@ -44,7 +44,7 @@ ArrayRef RISCVTargetInfo::getGCCRegNames() const { "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", // CSRs - "fflags", "frm", "vtype", "vl", "vxsat", "vxrm" + "fflags", "frm", "vtype", "vl", "vxsat", "vxrm", "sf_vcix_state"

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/106914 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/106914 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

@@ -44,7 +44,7 @@ ArrayRef RISCVTargetInfo::getGCCRegNames() const { "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", // CSRs - "fflags", "frm", "vtype", "vl", "vxsat", "vxrm" + "fflags", "frm", "vtype", "vl", "vxsat", "vxrm", "sf_vcix_state"

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

@@ -44,7 +44,7 @@ ArrayRef RISCVTargetInfo::getGCCRegNames() const { "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", // CSRs - "fflags", "frm", "vtype", "vl", "vxsat", "vxrm" + "fflags", "frm", "vtype", "vl", "vxsat", "vxrm", "sf_vcix_state"

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -317,38 +323,45 @@ ABIArgInfo RISCVABIInfo::coerceAndExpandFPCCEligibleStruct( // Fixed-length RVV vectors are represented as scalable vectors in function // args/return and must be coerced from fixed vectors. -ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty) const {

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

@@ -44,7 +44,7 @@ ArrayRef RISCVTargetInfo::getGCCRegNames() const { "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", // CSRs - "fflags", "frm", "vtype", "vl", "vxsat", "vxrm" + "fflags", "frm", "vtype", "vl", "vxsat", "vxrm", "sf_vcix_state"

[clang] [clang][RISCV] Fix typo of vector crypto in SemaRISCV.cpp. NFC (PR #106485)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/106485 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/106914 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/106914 >From 32126871d3dae79edaaa03bd1760790ca8a42e84 Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Sun, 1 Sep 2024 09:35:34 -0700 Subject: [PATCH 1/2] [RISCV][VCIX] Precommit test --- llvm/test/CodeGen/RISCV/inlin

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

4vtomat wrote: > > Do you mean change the current vcix_state register to sf.vcix_state? > > Yes, because it's SiFive specific register, other vendor may add other status > register like VCIX in future, so I would like to add prefix to make sure all > further similar stuff will follow same rule

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

4vtomat wrote: > I would suggest it should prefix with a vendor prefix, either `sf.vcix_state` > or `sifive.vcix_state`, also go `riscv-c-api-doc` or > `riscv-toolchain-conventions` :) Do you mean change the current `vcix_state` register to `sf.vcix_state`? https://github.com/llvm/llvm-projec

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

@@ -664,5 +664,9 @@ def FRM: RISCVReg<0, "frm">; // Shadow Stack register def SSP: RISCVReg<0, "ssp">; -// Dummy VCIX state register +// Dummy VCIX state register and its register class def VCIX_STATE : RISCVReg<0, "vcix_state">; +def : RISCVRegisterClass<[XLenVT], 32

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/106914 [RISCV][VCIX] Add vcix_state to GNU inline assembly register set Resolved https://github.com/llvm/llvm-project/issues/106700. This enables inline asm to have vcix_state to be a clobbered register thus disable

[clang] [clang][RISCV] Remove `experimental` for vector crypto intrinsics (PR #106359)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/106359 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Fix typo of vector crypto in SemaRISCV.cpp. NFC (PR #106485)

@@ -733,7 +733,7 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI, if (ElemSize == 64 && !TI.hasFeature("zvknhb")) return Diag(TheCall->getBeginLoc(), diag::err_riscv_builtin_requires_extension) - << /* IsExtension */ tru

[clang] [clang][RISCV] Fix typo of vector crypto in SemaRISCV.cpp. NFC (PR #106485)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/106485 None >From 71c66235e06faa0a793f829276991832ce5e487c Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Wed, 28 Aug 2024 20:21:59 -0700 Subject: [PATCH] [clang][RISCV] Fix typo of vector crypto in SemaRISCV.cpp. N

[clang] [clang][RISCV] Remove `experimental` for vector crypto intrinsics (PR #106359)

4vtomat wrote: > Do we still need this? > > ``` > def Experimental >: SubtargetFeature<"experimental", "HasExperimental", > "true", "Experimental intrinsics">; > ``` I guess we do in case there is any other extension that encounter the same situation lol~ https://git

[clang] [clang][RISCV] Remove `experimental` for vector crypto intrinsics (PR #106359)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/106359 The C intrinsic spec is ratified: https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/234. >From 59157100eac32981821eb15bce55d58f5f964bac Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Wed, 28 Aug 2024 0

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/100346 >From 15161b0b7637d52b6285624a4bf9f52a6664082c Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Sun, 21 Jul 2024 09:49:11 -0700 Subject: [PATCH 1/6] [RISCV][VLS] Support RISCV VLS calling convention This patch a

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -2206,6 +2206,21 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args, << A->getSpelling() << Val; } } + + if (Arg *A = Args.getLastArg(options::OPT_mriscv_abi_vlen_EQ)) { +StringRef ABIVLenStr = A->getValue(); +unsigned ABIVLen; +const Driver &

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

@@ -754,6 +754,17 @@ def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">, AssemblerPredicate<(all_of FeatureStdExtZvbc), "'Zvbc' (Vector Carryless Multiplication)">; +def FeatureStdExtZvbc32e +: RISCVExperimentalExtensio

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

@@ -150,6 +150,14 @@ let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in { SchedBinaryMC<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV">; } // Predicates = [HasStdExtZvkg] +let Predicates = [HasStdExtZvkgs], RVVConstraint = NoConstraint in {

[clang] [RISCV][clang] Remove bfloat base type in non-zvfbfmin vcreate (PR #102146)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/102146 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][clang] Add missing `zvfbfmin` to `vget_v` intrinsic (PR #102149)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/102149 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][clang] Add missing `zvfbfmin` to `vget_v` intrinsic (PR #102149)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/102149 It's missing in the patch supporting `zvfbfmin` intrinsics. >From 17cbf0b868699a04639c49acf4bbf383e70e85ca Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Tue, 6 Aug 2024 07:06:13 -0700 Subject: [PATCH] [RISCV

[clang] [RISCV][clang] Remove bfloat base type in non-zvfbfmin vcreate (PR #102146)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/102146 None >From 9ca5156a494d7f88ea80a960e2515142ae867ba8 Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Tue, 6 Aug 2024 06:56:48 -0700 Subject: [PATCH] [RISCV][clang] Remove bfloat base type in non-zvfbfmin vcreat

[clang] [RISCV][sema] Correct the requirement of `vf[n|w]cvt.x[|u].f` intrinsics (PR #101811)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/101811 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support `vrgather` and `vcompress` for `zvfhmin` and `zvfbfmin` (PR #101633)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/101633 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support bf16 vmv.v.v and vmerge.vvm intrinsics with `zvfbfmin` (PR #101611)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/101611 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][sema] Correct the requirement of `vf[n|w]cvt.x[|u].f` intrinsics (PR #101811)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/101811 Fix https://github.com/llvm/llvm-project/issues/101526 `vf[n|w]cvt.x[|u].f` for f16 needs `zvfh` instead of `zvfhmin`, current approach is not able to detect this. Ultimately we need to add `zvfh` to RequiredFea

[clang] [RISCV][sema] Correct the requirement of `vf[|n|w]cvt.f.*` intrinsics (PR #101608)

4vtomat wrote: This has been resolved by: https://github.com/llvm/llvm-project/pull/101733 https://github.com/llvm/llvm-project/pull/101608 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-comm

[clang] [RISCV][sema] Correct the requirement of `vf[|n|w]cvt.f.*` intrinsics (PR #101608)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/101608 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Use FP type as the base type for some int->f conversions. (PR #101733)

https://github.com/4vtomat approved this pull request. LGTM~ https://github.com/llvm/llvm-project/pull/101733 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][NFC] Remove unneeded defining name of `vundefined` (PR #101643)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/101643 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][NFC] Remove unneeded defining name of `vundefined` (PR #101643)

4vtomat wrote: > I don't think this will be better. We may keep these names so that these code > can be self-explanatory. Yeah, it's reasonable to me. https://github.com/llvm/llvm-project/pull/101643 ___ cfe-commits mailing list cfe-commits@lists.llv

[clang] [RISCV][clang] Remove unused base type in `vfncvt` (PR #101646)

4vtomat wrote: > Make sense to me. > (Do we have a way to test these generated builtins?) I think we don't since the intrinsics are generated on demand during runtime. https://github.com/llvm/llvm-project/pull/101646 ___ cfe-commits mailing list cfe-c

[clang] [RISCV][clang] Remove unused base type in `vfncvt` (PR #101646)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/101646 We don't have `fp8` type supported yet. >From ff5083431d41d22c50725638b084bfb2532dad74 Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Fri, 2 Aug 2024 03:04:18 -0700 Subject: [PATCH] [RISCV][clang] Remove unus

[clang] [RISCV][NFC] Remove unneeded defining name of `vundefined` (PR #101643)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/101643 `vundefined` doesn't have corresponding named IR, instead it generates `poison` value, we already define the `Name` for C intrinsics, so we don't need the defining name at all. >From df6b40a85ca89259751583b6642

[clang] [llvm] [RISCV] Support `vrgather` and `vcompress` for `zvfhmin` and `zvfbfmin` (PR #101633)

https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/101633 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][sema] Correct the requirement of `vf[|n|w]cvt.f.*` intrinsics (PR #101608)

https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/101608 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][sema] Correct the requirement of `vf[|n|w]cvt.f.*` intrinsics (PR #101608)

@@ -2011,9 +2021,15 @@ let ManualCodegen = [{ RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFwu"]]>; let OverloadedName = "vfncvt_f" in { defm : - RVVConvBuiltinSet<"vfncvt_f_x_w", "csi", [["Fv", "Fvwu"]]>; + RVVConvBuiltinSet<"v

[clang] [RISCV][sema] Correct the requirement of `vf[|n|w]cvt.f.*` intrinsics (PR #101608)

https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/101608 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][sema] Correct the requirement of `vf[|n|w]cvt.f.*` intrinsics (PR #101608)

@@ -2011,9 +2021,15 @@ let ManualCodegen = [{ RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFwu"]]>; let OverloadedName = "vfncvt_f" in { defm : - RVVConvBuiltinSet<"vfncvt_f_x_w", "csi", [["Fv", "Fvwu"]]>; + RVVConvBuiltinSet<"v

[clang] [RISCV][sema] Correct the requirement of `vf[|n|w]cvt.f.*` intrinsics (PR #101608)

@@ -2011,9 +2021,15 @@ let ManualCodegen = [{ RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFwu"]]>; let OverloadedName = "vfncvt_f" in { defm : - RVVConvBuiltinSet<"vfncvt_f_x_w", "csi", [["Fv", "Fvwu"]]>; + RVVConvBuiltinSet<"v

[clang] [RISCV][sema] Correct the requirement of `vf[|n|w]cvt.f.*` intrinsics (PR #101608)

@@ -1912,8 +1912,12 @@ def vfcvt_rtz_x_f_v : RVVConvToSignedBuiltin<"vfcvt_rtz_x">; let Log2LMUL = [-3, -2, -1, 0, 1, 2] in { def vfwcvt_rtz_xu_f_v : RVVConvToWidenUnsignedBuiltin<"vfwcvt_rtz_xu">; def vfwcvt_rtz_x_f_v : RVVConvToWidenSignedBuiltin<"vfwcvt_rtz_x">; - def

[clang] [RISCV][sema] Correct the requirement of `vf[|n|w]cvt.f.*` intrinsics (PR #101608)

@@ -2011,9 +2021,15 @@ let ManualCodegen = [{ RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFwu"]]>; let OverloadedName = "vfncvt_f" in { defm : - RVVConvBuiltinSet<"vfncvt_f_x_w", "csi", [["Fv", "Fvwu"]]>; + RVVConvBuiltinSet<"v

[clang] [RISCV][sema] Correct the requirement of `vf[|n|w]cvt.f.*` intrinsics (PR #101608)

@@ -2011,9 +2021,15 @@ let ManualCodegen = [{ RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFwu"]]>; let OverloadedName = "vfncvt_f" in { defm : - RVVConvBuiltinSet<"vfncvt_f_x_w", "csi", [["Fv", "Fvwu"]]>; + RVVConvBuiltinSet<"v

[clang] [RISCV][sema] Correct the requirement of `vf[|n|w]cvt.f.*` intrinsics (PR #101608)

4vtomat wrote: > What about vfncvt and vfwcvt? Added! https://github.com/llvm/llvm-project/pull/101608 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][sema] Correct the requirement of `vf[|n|w]cvt.f.*` intrinsics (PR #101608)

https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/101608 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][sema] Correct the requirement of `vfcvt.f.*` intrinsics (PR #101608)

https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/101608 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

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