Pn Thu, Jun 13, 2024 at 11:57 AM Paul Koning via cctalk <
cctalk@classiccmp.org> wrote:
> MIPS, perhaps? It has "delay slots".
MIPS has delay slots for branches (two for Standord MIPS, one for
commercial MIPS), but no delay slots for ALU operations. All MIPS
implementations either interlocked t
On Thu, Jun 13, 2024 at 10:15 AM CAREY SCHUG via cctalk <
cctalk@classiccmp.org> wrote:
> I think I recall an early processor that did out of order execution,
> without checking, meaning you could have
>
> add xxx to accumulator
> store accumulator in zzz
>
The Intel i860 (unrelated to x86, i960,
On 2024-06-21 05:17, Eric Smith via cctalk wrote:
A pipelined FP operation immediately followed by a store will
not store the result of that operation. Needless to say, programming in
pipelined FP mode is challenging, but it's the way to get the highest FP
performance out of the i960. Math librar
