On 02/21/2021 03:33 AM, Josh Dersch via cctalk wrote:
"0" here selects DR (Destination Register) input to the mux and is
incorrect; it should be 1 (PCB). During a single-instruction-step run,
this value reads out OK on the analyzer. I noted a few other discrepancies
in the capture (all of which
On Wed, Feb 17, 2021 at 12:45 AM Josh Dersch wrote:
>
>
> I hooked the LA up to the two PROM bits that select the AMX input (RACC
> UAMX00 H and RACC UAMX01 H), on the ROM & Address Control board. These
> come from the PROM at U101 and go through a 74S174 at E97 before heading
> over to the DAP
On 02/17/2021 02:45 AM, Josh Dersch via cctalk wrote:
"0" here selects DR (Destination Register) input to the
mux and is incorrect; it should be 1 (PCB). During a
single-instruction-step run, this value reads out OK on
the analyzer. I noted a few other discrepancies in the
capture (all of whic
On Tue, Feb 16, 2021 at 5:08 PM Fritz Mueller via cctalk <
cctalk@classiccmp.org> wrote:
> > On Tue, Feb 16, 2021 at 2:36 AM Fritz Mueller via cctalk <
> cctalk@classiccmp.org> wrote:
> > So you could set up on t4 or t5 of that microinstruction with the KM11...
>
> > On Feb 16, 2021, at 11:08 AM,
> On Tue, Feb 16, 2021 at 2:36 AM Fritz Mueller via cctalk
> wrote:
> So you could set up on t4 or t5 of that microinstruction with the KM11...
> On Feb 16, 2021, at 11:08 AM, Josh Dersch wrote:
> I can't, though -- all of this stuff works fine when running slowly :)
Oh right -- I keep forgett
On Tue, Feb 16, 2021 at 2:36 AM Fritz Mueller via cctalk <
cctalk@classiccmp.org> wrote:
>
>
> > On Feb 16, 2021, at 1:13 AM, Josh Dersch wrote:
> > My money's on t5 going wrong -- an ALU input mux or operation being
> selected incorrectly, possibly. This also somewhat explains why execution
> d
> On Feb 16, 2021, at 1:13 AM, Josh Dersch wrote:
> My money's on t5 going wrong -- an ALU input mux or operation being selected
> incorrectly, possibly. This also somewhat explains why execution doesn't
> trap due to executing a HALT from an odd address -- it isn't actually
> executing fro
On Mon, Feb 15, 2021 at 8:01 PM Fritz Mueller via cctalk <
cctalk@classiccmp.org> wrote:
> Hi Josh,
>
> In the situation you describe, I guess I would first chip clip '174s for a
> slice of both PCA and PBC on the LA, run the troublesome instruction
> sequence, and look at the trace. Check that C
Hi Josh,
In the situation you describe, I guess I would first chip clip '174s for a
slice of both PCA and PBC on the LA, run the troublesome instruction sequence,
and look at the trace. Check that CLKPCA H and CLKPCB H are happening when and
only when expected, and that all the timing there lo
