[bug #8297] Allow multiple targets to be built from a single explicit rule recipe invocation

Follow-up Comment #11, bug #8297 (project make): [comment #10 comment #10:] How do you think about to insert a specification like “@cindex &:” in the file “make.texi” ? __

Re: Converting make rules into other file formats

> Are the chances better to extend the tool “remake” then? … > Probably. Can it be that our software development resources are also too limited for mentioned tasks? > My intention was to provide profiling information by default … This is generally fine. Do any collaboration challenges hind

Re: Converting make rules into other file formats

> Before talking about formats and graphical representation, > I advise you to ask if Paul agrees with this kind thing. Are the chances better to extend the tool “remake” then? https://github.com/rocky/remake/wiki Regards, Markus ___ Bug-make mailing l

Re: Converting make rules into other file formats

> A Makefile is basically a human-readable text file with instructions > on how to create executables with a compiler for example. How often do you look for a more visual representation of this content? > It has pretty much nothing to do with creating graphics. I got an other opinion. * Do you

Converting make rules into other file formats

Hello, How does the current software situation look like for the conversion of data from make scripts into file formats with which other users are more familiar? Examples: * Outlines * Vector graphics Would you like to point any special development tools out? Regards, Markus ___

[bug #51309] Determination of a file list from a single folder without changing the working directory

Follow-up Comment #10, bug #51309 (project make): Would you like to compare run time characteristics a bit more with an approach similar to “$(shell find ~/Projekte/Bau/OCamlbuild -name '*.txt' -printf "%f ")”? ___ Reply to this item at:

Checking unique recipe execution during parallel software builds

Hello, I am testing my recent adjustments for a few build scripts. Now I wonder again about an error message. But I guess that it should only be taken into account when an other issue will be checked once more and resolved then hopefully. elfring@Sonne:~/Projekte/Bau/OCamlbuild> LANG=C make -r -

Re: Switching from relative paths to absolute directory specifications in make scripts?

>> This test result seems to show that it can make a significant difference >> if such a target was specified by a relative or absolute path. >> (I would expect that these specifications will refer to the same file.) > > Keep in mind that targets are opaque strings, I would prefer a more convenie

Switching from relative paths to absolute directory specifications in make scripts?

Hello, I am fiddling with a few build scripts for another free software. elfring@Sonne:~/Projekte/Bau/OCamlbuild> rm -f src/glob_lexer.ml && LANG=C make --no-builtin-rules V=1 src/glob_lexer.ml; LANG=C make --no-builtin-rules V=1 ~/Projekte/Bau/OCamlbuild/src/glob_lexer.ml make: *** No rule to

Re: Ensuring existance of directories before writing files into them

> Here's one way to solve the problem: > http://www.chaos.org.uk/~eddy/craft/make.html#AutoDir Thanks for your link for information around the topic “Autogenerating (needed) directories”. Will it become better recognised as another design/construction pattern? Regards, Markus _

Re: [bug #51311] Checking search retries for implicit make rules

> At the risk of stating the obvious, note that there is a trivial > work-around for this - there is nothing special about dot in patterns, > so you could merge the dot into what % matches to make it non-empty: It might be acceptable to give up a character from either end of the prefix (or suffix)

Ensuring existance of directories before writing files into them

Hello, Files are stored within directories. So there is a general dependency that the directory should exist (together with an identifier) before a file can be changed. Prerequisites for make rules can be specified in the way that their file names reference a specific build directory. I have got

[bug #51338] Support for construction patterns by make functions

Follow-up Comment #8, bug #51338 (project make): > …, including POSIX-compliant makefiles as well as GNU make-specific makefiles. I contributed also a bit in this area. > In any event, the bug tracker is not the place for that discussion. It seems that it will occasionally happen to “loose” th

Re: [bug #51309] Determination of a file list from a single folder without changing the working directory

> Are you able to provide any example proving how it matters under some more > or less rare circumstances? I guess not at the moment. > Or do you find the current software good enough I dared to point some change possibilities out recently. > and no changes needed? It depends on your views f

[bug #51309] Determination of a file list from a single folder without changing the working directory

Follow-up Comment #9, bug #51309 (project make): I suggested also a comparison of two algorithms . * A simple time measurement can also show test results for which you might not be looking for. * The usage of data structures like list

[bug #51338] Support for construction patterns by make functions

Follow-up Comment #6, bug #51338 (project make): > …, but I can't tell exactly what aspects of the current capabilities you want to be different. This one is more a feature request. > That's not a design, But I find that a selection of two rules could fit into this area. > it's basically a r

[bug #51306] Checking programming possibilities around “MAKECMDGOALS”

Follow-up Comment #4, bug #51306 (project make): But the make rule set can be adjusted in some ways according to the query result. ___ Reply to this item at:

[bug #51338] Support for construction patterns by make functions

Follow-up Comment #4, bug #51338 (project make): > You don't need to use secondary expansion inside the recipe, because you already have access to the automatic variables like $@ there. I thought about a need for a “second expansion” (for a moment) while it could be implemented in the mentioned u

[bug #51311] Checking search retries for implicit make rules

Follow-up Comment #4, bug #51311 (project make): > In fact there can be zero, one, or as many prerequisites containing the pattern character as you like. Essentially if the target contains a pattern character then it's a pattern rule: Can examples in the manual cause the impression that there is

[bug #51306] Checking programming possibilities around “MAKECMDGOALS”

Follow-up Comment #2, bug #51306 (project make): I imagine that there is a need to express higher level requirements. If you know for example that parameter like “distclean” was passed somewhere in the list of make goals, I guess that it can make sense to omit the execution of previous targets wh

[bug #51292] Handling make rules where prerequisites are determined by functions for specific targets lists

Follow-up Comment #7, bug #51292 (project make): > If you want a "callback"-like setup you can already do it with eval and call: This approach might be an approximation which can work as usual for a while. > Personally I'm not convinced this is useful in general... I dared to propose a softwar

[bug #51292] Handling make rules where prerequisites are determined by functions for specific targets lists

Follow-up Comment #6, bug #51292 (project make): Was your feedback truncated by the tracking interface for this issue? ___ Reply to this item at: ___ Me

[bug #51309] Determination of a file list from a single folder without changing the working directory

Follow-up Comment #7, bug #51309 (project make): > (a) you prefer to do it this way rather than the currently supported method of post-processing the wildcard results, … Yes. >(b) there's a significant performance benefit to avoiding the extra processing. I find that the difference can be even

[bug #51278] Support for the specification of special build properties together with each make rule

Follow-up Comment #2, bug #51278 (project make): > .SUFFIXES is an entirely different thing and doesn't belong on this list: it doesn't modify a target. Is this target relevant for suffix rules? >.SECONDEXPANSION is a boolean flag for the entire make process, it doesn't apply to specific target

[bug #51309] Determination of a file list from a single folder without changing the working directory

Follow-up Comment #4, bug #51309 (project make): I repeat my argument from 26. June: https://lists.gnu.org/archive/html/bug-make/2017-06/msg00198.html If the desired directory on which a file filter should be applied could be selected before, the file names would not contain references to this di

[bug #51269] Reusing data from targets for prerequisites

Follow-up Comment #2, bug #51269 (project make): I would also like to restrict secondary expansion (or evaluation?) to specific make rules which might not fit to the following information. “… In order for this second expansion to occur, the special target .SECONDEXPANSION must be defined before t

[bug #51309] Determination of a file list from a single folder without changing the working directory

Follow-up Comment #2, bug #51309 (project make): I disagree with the run time characteristics of the mentioned functionality for my special use case. ~/Projekte> $(cd Bau && echo "echo $(ls *txt)") MOTD.txt Can a similar data processing operation be performed faster by advanced make functions

[bug #51338] Support for construction patterns by make functions

Follow-up Comment #2, bug #51338 (project make): > You can do that today, no need for any enhancement. I was also unsure about differences in the desired application of “second expansion”. I have shown a bit with the code example that special build rule combinations can be implemented with make

[bug #51338] Support for construction patterns by make functions

URL: Summary: Support for construction patterns by make functions Project: make Submitted by: elfring Submitted on: Thu 29 Jun 2017 07:55:34 AM CEST Severity: 3 - Normal

Trying to avoid a repeated search for a prerequisite (or target)

Hello, The variable “VPATH” has got a special meaning for the make software. https://www.gnu.org/software/make/manual/html_node/General-Search.html “… Thus, if a file that is listed as a target or prerequisite does not exist in the current directory, make searches … …” I would interpret this in

Re: Improving dependency specifications in make rules?

> I am also curious on how other involved contributors will react to > a pull request for recent software developments around the discussed > build scripts. Would you like to add any constructive comments there? https://github.com/coccinelle/coccinelle/pull/108 How do you think about to clarify r

Re: Checking application of dependencies from make rules without recipes

> I can only assume you are referring to this pattern rule: > >> %.cmo: %.ml %.cmi >> $(o_compilation) '$<' > $@ > > and you're saying that if the .cmi file cannot be created, that make > should not consider this an error. I became also curious on how the clarification will evolve for th

Re: [bug #51309] Determination of a file list from a single folder without changing the working directory

> MY_FILES=$(notdir $(wildcard somedir/*.ext)) I agree that this algorithm can work. But it does not fit to my imaginations for efficient data processing. If the desired directory on which a file filter should be applied could be selected before, the file names would not contain references to thi

Re: [bug #51311] Checking search retries for implicit make rules

> To quote the make info pages, section 10.5.1 "Introduction to Pattern Rules": > - > A pattern rule contains the character `%' (exactly one of them) I interpreted this description in the way that one placeholder would be supported for each element in the list of prerequisites. > …; the `%'

[bug #51311] Checking search retries for implicit make rules

Follow-up Comment #2, bug #51311 (project make): From Mike Gran: “… So your interpretation is incorrect. …” I find that the documentation can be clarified a bit more on this aspect. I propose another software extension then. From Mike Gran: “… It needs to match at least a single character, …”

[bug #51311] Checking search retries for implicit make rules

URL: Summary: Checking search retries for implicit make rules Project: make Submitted by: elfring Submitted on: Sun 25 Jun 2017 09:40:47 PM CEST Severity: 3 - Normal Item

[bug #51309] Determination of a file list from a single folder without changing the working directory

URL: Summary: Determination of a file list from a single folder without changing the working directory Project: make Submitted by: elfring Submitted on: Sun 25 Jun 2017 07:53:27 PM CEST

[bug #51306] Checking programming possibilities around “MAKECMDGOALS”

URL: Summary: Checking programming possibilities around “MAKECMDGOALS” Project: make Submitted by: elfring Submitted on: Sat 24 Jun 2017 10:22:36 PM CEST Severity: 3 - Normal

Re: Replacing suffix rules in make scripts?

> Why do I get such an error message for a parallel software build attempt > when the specified dependencies worked as expected for the non-parallel > build try before? How do you think about the corresponding update suggestion “Improve some dependency specifications in make rules”? https://github

Re: Replacing suffix rules in make scripts?

> The OCaml makefile specifies an order in which the files should be > compiled in the project. If you are sidestepping that ordering, then you > are not doing things in the intended manner. I hope that some details were clarified to some degree in the meantime. > There is only an intent to sup

[bug #51297] Better support for escaping of function parameters

URL: Summary: Better support for escaping of function parameters Project: make Submitted by: elfring Submitted on: Fri 23 Jun 2017 12:11:01 PM CEST Severity: 3 - Normal I

[bug #51292] Handling make rules where prerequisites are determined by functions for specific targets lists

Follow-up Comment #3, bug #51292 (project make): Another example by Mike Gran: demo: $(guile (root->list-of-objects "demo")) $(CC) $(LDFLAGS) -o $@ $^ You showed an other interesting use case. It seems that only simple input file dependencies would be constructed. I guess that the concr

Re: How to avoid the double execution of a make info call?

> If the makefile, or any of the files it includes, is updated by make > then make will re-execute itself and re-read all the makefiles from > scratch so it can see the updated content. When that happens, > obviously all the $(info ...) functions etc. will be re-expanded. Thanks for your repeated

[bug #51292] Handling make rules where prerequisites are determined by functions for specific targets lists

Follow-up Comment #1, bug #51292 (project make): Example by Mike Gran: $(objects): $(foreach X,$@,\ $(guile (gcomp "$(X)"))) @true I would like to see a kind of function call for the specification of prerequisites (instead of the shown function calls in the recipe). A v

Re: How to avoid the double execution of a make info call?

> Your Makefile looks likely to rebuild .depend, a file that it includes. > So, like Paul said: >>> or else make has re-executed itself >>> because this makefile or one of its >>> included files was rebuilt; Yes. - This can happen at the moment. > I wonder about the information “Re-executing[1]

Re: How to avoid the double execution of a make info call?

> If you are seeing these values printed multiple times it means that the > makefile is being parsed multiple times. How can such additional parsing be clarified further? Will it help to display extra data from special make variables? > Why that might be, we can't determine from the information

[bug #51292] Handling make rules where prerequisites are determined by functions for specific targets lists

URL: Summary: Handling make rules where prerequisites are determined by functions for specific targets lists Project: make Submitted by: elfring Submitted on: Thu 22 Jun 2017 03:10:13 PM CEST

Re: How to avoid the double execution of a make info call?

> modules_without_mli::=$(filter-out $(basename $(mli_sources)),$(basename > $(ml_sources))) > $(info modules_without_mli) > $(info $(sort $(modules_without_mli))) It seems that I got this design approach working to some degree by the addition of a few calls of make functions. I am not completely

Re: Checking application of dependencies from make rules without recipes

> Your claim was that either explicit rules should come before implicit rules > or vice versa. You are more free with your choices for placement of explicit rules in make scripts (because you can not and will therefore not cancel them). You should be careful then which of your explicit rules wil

Re: Checking application of dependencies from make rules without recipes

> I don't think that's relevant: a graph's topology isn't dependent > on the order in which its arcs are enumerated. I have tried to stress the construction sequence. > When you submit a test case that demonstrates a bug, I stumbled on two special cases depending on your view of the correspondi

[bug #51286] Support for additional local make variables

URL: Summary: Support for additional local make variables Project: make Submitted by: elfring Submitted on: Wed 21 Jun 2017 07:00:14 PM CEST Severity: 3 - Normal Item Gro

Re: [bug #51269] Reusing data from targets for prerequisites

> It's important to realize that even though the unfortunate choice of > naming implies otherwise, static pattern rules are in all ways > _explicit_ rules. They are not and should never be considered > implicit rules. Thanks for your explanation. This terminology can occasionally trigger corresp

Re: Checking application of dependencies from make rules without recipes

> I don't see why it makes a difference in how rule types should be ordered A dependency graph is constructed by make scripts. > (I assume that by "ordered" you mean which rules are defined > first in the makefile). Yes. The possibility is supported to cancel implicit rules (which refer to tar

Re: Checking application of dependencies from make rules without recipes

>> How much can make scripts help to manage (optional) programming >> interface descriptions? > > Are you asking, how can a makefile represent a prerequisite which may be > built, but is not required to be built and it's not an error if it > cannot be built? How do you think about the following a

Re: [bug #51269] Reusing data from targets for prerequisites

>> * Can it eventually happen that dependencies will not be resolved if >> target names do not contain the percent character? > > I can't remember, but a simple experiment should answer that ! I guess that it will be noticed once more that implicit rules will work in an other way than static pa

[bug #51278] Support for the specification of special build properties together with each make rule

URL: Summary: Support for the specification of special build properties together with each make rule Project: make Submitted by: elfring Submitted on: Tue 20 Jun 2017 03:30:32 PM CEST

Re: Checking application of dependencies from make rules without recipes

> This applies only to implicit rules, not explicit rules. > >> Can an explicit make rule also be cancelled anyhow? > > No. Thanks for this clarification. This distinction has got important consequences on how the different make rule types can and should be ordered relative to each other. Woul

Re: [bug #51269] Reusing data from targets for prerequisites

>> Would it make sense to allow that another special syntax will denote >> additional placeholders (similar to the handling of the percent character)? > > Take a look at > https://www.gnu.org/software/make/manual/html_node/Static-Usage.html > > It may enable what you want already. This functiona

Re: [bug #51269] Reusing data from targets for prerequisites

>> Would it make sense to allow that another special syntax will denote >> additional placeholders (similar to the handling of the percent character)? > > Take a look at > https://www.gnu.org/software/make/manual/html_node/Static-Usage.html Thanks for your link. > It may enable what you want al

Re: Checking file generation for a test script

>> My pattern example does not work with the current make software in the >> way I hoped would be occasionally convenient. > > No it does not. Did you read my entire previous answer? Yes. - I replied to it twice with different information. Regards, Markus ___

Re: Checking application of dependencies from make rules without recipes

>> Would you like to add any more advice to this aspect? > > Only if you have a specific question. I have got another software development concern. The section “Canceling implicit rules” of the documentation mentions something about the omission of recipes (or do they become “empty”?). https://w

[bug #51269] Reusing data from targets for prerequisites

URL: Summary: Reusing data from targets for prerequisites Project: make Submitted by: elfring Submitted on: Mon 19 Jun 2017 07:34:22 PM CEST Severity: 3 - Normal Item Gro

[bug #51267] Improve error handling after a special command

URL: Summary: Improve error handling after a special command Project: make Submitted by: elfring Submitted on: Mon 19 Jun 2017 06:08:34 PM CEST Severity: 3 - Normal Item

Re: Checking file generation for a test script

> It would have been generated if you would have called make with a command > like: elfring@Sonne:~/Projekte/Bau> LANG=C make --no-builtin-rules -f ../rule-check2.make MOTD.log make: *** No rule to make target 'MOTD.log'. Stop. > LANG=C make --no-builtin-rules -f ../rule-check2.make MOTD.log

Re: Checking application of dependencies from make rules without recipes

>> Does such a feedback indicate that would like to look also into the >> corresponding development repository? > > No. At least I don't have time to review an entire development environment. Such a choice is also fine. > If you post the set of rules responsible for creating those files > in t

Re: Checking application of dependencies from make rules without recipes

>> It seems then that the original make scripts could treat more >> interface descriptions as optional somehow. > > Without know what your original makefiles said I can't comment on that. Does such a feedback indicate that would like to look also into the corresponding development repository? Ex

Re: Checking application of dependencies from make rules without recipes

>>> LANG=C make --no-builtin-rules -f parsing-rule-check1.make >> make: *** No rule to make target 'ast_c.cmo', needed by 'parsing_c.cma'. >> Stop. > > I feel like this is the same question you've already asked, > and Philip already answered, before. An other area was eventually easier to expla

Re: Checking application of dependencies from make rules without recipes

> Could you provide examples of the Makefiles rules you tried? A rough approximation for further discussion: i_compilation?=echo o_compilation?=echo a_generation?=$(o_compilation) 'Checked modules: ' parsing_c.cma: ast_c.cmo token_annot.cmo $(a_generation) '$<' > $@ %.cmi: %.mli

Re: Checking file generation for a test script

> It would have been generated if you would have called make with a > command like: > LANG=C make --no-builtin-rules -f ../rule-check2.make MOTD.log I hoped that I do not need to specify another file name for such command variant just to test a special default setting. > and if you had a rule to

Checking file generation for a test script

Hello, I have tried the following small script out together with the program “GNU Make 4.2.1-1.7” on my openSUSE Tumbleweed system. my_compilation?=echo my_preparation?=cat footer?=MOTD.txt prepared_file?=MOTD.in MOTD%.log: MOTD%.txt MOTD%.in ${my_compilation} "$<: $$(cat ${prepared_fil

Re: Checking alternatives for a dynamic make rule construction

> Sure, it could be made clear in the documentation that either of the > sides of the "=" could be empty. In how many source files should corresponding information be integrated to make these special cases better known for substitution references? > However, there are plenty of ways to do this s

Re: Checking alternatives for a dynamic make rule construction

>> my_test_command?=cat >> >> define my_rule_demo= >> name::=${1} >> $${name:.in=.txt}: ${1} >> $${my_test_command} $$< > $$@ >> endef >> >> $(eval $(call my_rule_demo,MOTD.in)) > > Is there something wrong with it? The answer depends on our views about approaches how customised make func

Re: Checking alternatives for a dynamic make rule construction

>> define my_broken_rule= >> name::=${1} >> ${name:.in=.txt}: ${1} >> $${my_test_command} $$< > $$@ >> endef >> >> $(eval $(call my_broken_rule,MOTD.in)) > > Yes, this will not work. Thanks for your quick answer. It might also be expected that this simple example just can not work as in

Re: Checking alternatives for a dynamic make rule construction

> What Philip is saying (and I agree 100%) is that you provide the above > example which is excellent and helpful and allows us to see exactly what > you're doing. Thank you for that. I was also curious in this case how the interest will evolve to clarify the shown construction of make rules. >

Re: Checking application of dependencies from make rules without recipes

> Could you provide examples of the Makefiles rules you tried? It depends on the detail level you prefer and my tendency to increase corresponding efforts only incrementally. > It's very difficult to provide feedback without complete information. Would you like to add any advice to a discussion

Re: Checking alternatives for a dynamic make rule construction

> Using ::= in a makefile which is already dependent on GNU make is, IMO, > pointless. I am trying to use portable make specifications to some degree. But it seems to be challenging to avoid the usage of all the nice functionality which is provided as extensions also by this software development

Re: Checking software build tries for “commands.cmo”

> I believe the point of Martin's rhetorical query is "why should make treat > the failure of *this* pattern rule any different than the failure of the > many other pattern rules that would have permitted this compilation > to complete?" It seems that I need to try harder for the desired clarifi

Re: Checking software build tries for “commands.cmo”

>> I needed another moment to become really aware that this software module >> is a bit special. It seems that it is intended that it will be compiled >> without a corresponding interface description file (suffix “mli”). > > Well, I'm totally lost. Here's why: > > You told make ".cmo files can b

Checking application of dependencies from make rules without recipes

Hello, I got some special software development experiences by the usage of the program “GNU Make 4.2.1-1.7” on my openSUSE Tumbleweed system. The functionality “Generating prerequisites automatically” is desribed in the manual. I would like to check again how good this works at the moment. I am t

Re: Checking software build tries for “commands.cmo”

> Did you tell make, then, to disable all of its default rules for creating > commands.mli or, > for that matter, commands.cmo, by checking them out of version control? Not directly so far. - The source file “commands.mli” is not needed for the generation of the object module “commands.cmo” in th

Checking alternatives for a dynamic make rule construction

Hello, I have constructed the following small script to be executed by the program “GNU Make 4.2.1-1.7” on my openSUSE Tumbleweed system. define rule_pair = name::=$(1) $$(name:.ml=.cmo): $$(name) $$(OCAMLC_CMD) -c $$< $$(name:.ml=.cmx): $$(name) $$(OCAMLOPT_CMD) -c $$< endef $

Re: Checking software build tries for “commands.cmo”

>> I have noticed a moment ago that an interface description file was missing >> somehow for the OCaml source file in this compilation attempt. > ... >> I wonder then that the make tool did not give me a direct clue for a failed >> software dependency as I am used to in other cases. > Would you hav

Re: Checking software build tries for “commands.cmo”

> (I would guess that most of the people on the bug-make mailing list have > never worked with ocaml and therefore don't know what needs to be done to > build it.) Yesterday I realised that one source source file needed a special handling in the mentioned subdirectory. > The snippet of Makefil

Re: Checking software build tries for “commands.cmo”

> elfring@Sonne:~/Projekte/Coccinelle/20160205/commons> LANG=C make -d > commands.cmo V=1 > … > No implicit rule found for 'commands.cmo'. > Finished prerequisites of target file 'commands.cmo'. > Must remake target 'commands.cmo'. > Successfully remade target file 'commands.cmo'. > make: Nothin

Checking software build tries for “commands.cmo”

Hello, I am testing the following pattern rules with the program “GNU Make 4.2.1-1.7” on my openSUSE Tumbleweed system as I would like to adjust some areas in affected make scripts for another evolving software tool. … %.cmi: %.mli $(OCAMLC_CMD) -c $< %.cmo: %.ml %.cmi $(OCAMLC_C

Re: Management for relative paths in global build parameters

> Read up on the differences between builddir and srcdir, current and top_, > relative and abs_. > These are all preset output variables in Autoconf. Thanks for your reminder. I submitted a similar clarification request also for this software area. “Management for relative paths in global buil

Re: Management for relative paths in global build parameters

> Relative paths are fine when including makefiles from sub-directories. > What matters is that targets use *consistent* paths. Thanks for your feedback. I would like to clarify dependencies for other build system details a bit more. > This assumes your make system is non-recursive, of course.

Management for relative paths in global build parameters

Hello, Software development projects can grow in the way that corresponding components will be stored in several subdirectories. Such a project organisation has got consequences on the management of some dependencies. Now I am looking for advanced support possibilities by the make software once m

Re: Fine-tuning for parallel building with GNU make

> Visiting folders non PARALLEL while compiling itself inside of the folders is > IN PARALLEL. How do you think about to traverse the affected directory hierarchy by a dedicated make recipe? * Have you got any expectations about the amount of parallel work which should be triggered by script

Re: Parallel build consequences from GNU make

> I tried to use the following command for parallel build but it is not working. > *Make **–**j 7 **–**f makefile.mak build* I find your impression strange. > When I execute the above command, I can see that the GNU make is utilizing > 40%-60% of CPU. Which tools did you use to check the run ti

[bug #43936] Completion of error handling

Follow-up Comment #8, bug #43936 (project make): I try to reduce return value ignorance a bit more. I find quick error detection generally better because immediate exception handling might also reduce the time during which the affected software will run under "unexpected" conditions. Should compu

[bug #43936] Completion of error handling

Follow-up Comment #6, bug #43936 (project make): I find that my question contained another bit of information for further considerations. How long does a program may continue to run after an error occurred? How do you think about to improve static source code analysis also for your software? http

[bug #43936] Completion of error handling

Follow-up Comment #4, bug #43936 (project make): I find a comment like the following unsafe. "… Besides, it's wasteful to check the return value from every call that writes to stdout …" Can the delay between error occurrence and exception handling by the function "close_stdout" become inap

[bug #43936] Completion of error handling

Follow-up Comment #2, bug #43936 (project make): Would it be a bit safer to detect every error situation as early as possible? When does a failed output need an immediate reaction in this software? ___ Reply to this item at:

Re: Parallel make with distributed systems

> The question is, why is it the case that these challenges, tasks, work, > and constraints need to be handled within make itself, > rather than farmed out to a separate process via the SHELL capability? Does it matter to get the accounting for the processor cores right? > Offhand I can't see an

Re: Parallel make with distributed systems

> I have nothing against doing more than that in theory, but before I'd > agree to add something complex I'd need to understand where the existing > method fails, and the new method would provide significant benefits. I guess that there are some software development challenges around the specifica

Re: Parallel make

> GNU make has no built-in capability to use multiple machines: How are the chances to integrate additional job submission systems? > conceptually it may be a straightforward extension but the effort needed > to communicate between multiple systems over a network, send and receive > results reli

Re: Conditional recipe execution

> But a quick check of your link above shows no comments or anything > in the makefile describing what it does, Thanks for your look at my example. > and I don't really understand the purpose behind all these recipes > which consist of if-statements where the body of the recipe is made empty > i

Re: Challenges around the combination of functions "call" and "eval"

> $(eval ...) is a (relatively) recently implemented, very advanced > feature that exists only in GNU make: no other implementation of make > has anything like it (that I'm aware of). Since which program version are the functions "call" and "eval" generally available? > So you really just don't

Re: Extensions for make file parsing?

>>> As I've said, it is not possible for a single variable or function >>> reference to span multiple logical lines. >> >> Are there any chances to lift this restriction for make functions? > > It's very unlikely. The entire implementation of the parser in make at > its most basic level is comple

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