Soham Das wrote:
> Mucho Thanks :) for this entire thing.
YW. :-)
> Yes I did went through, Learning Perl, but it contains very less
> about Modules. In the mean while I was exploring Test::Simple and
> Test::More modules. There is a very good presentation on
> petdance.com.
> Its good. I liked
Soham Das wrote:
> Thank You!
YW. :-)
> But isn't Perl used to generate those testbench scripted in Verilog?
> This is what I had an impression of.
One of Perl's slogans is "there is more than one way to do it" (TIMTOWTDI). I
described one approach; using Perl to generate HDL test benches i
Original Message
From: David Christensen
To: beginners@perl.org
Cc: Soham Das
Sent: Sunday, 12 July, 2009 10:39:08 AM
Subject: RE: Perl for HDL Verification
Soham Das wrote:
> Can anyone who has worked in Hardware Designing domain, particularly
> HDL and RTL design, tell
Soham Das wrote:
> Can anyone who has worked in Hardware Designing domain, particularly
> HDL and RTL design, tell me how exactly is Perl used to generate
> testbenches and verification work.
I used Perl for testing Verilog designs back in ~2002. Going from memory, I
wrote my designs and test be
Hi All,
For the disclaimers: I am new to Perl[as I was some 7 months back :) ] and to
get things rolling, I know just a bit of it. Hence the question, might appear a
bit, unpolished.
Can anyone who has worked in Hardware Designing domain, particularly HDL and
RTL design, tell me how exactly i
