Soham Das wrote: > Can anyone who has worked in Hardware Designing domain, particularly > HDL and RTL design, tell me how exactly is Perl used to generate > testbenches and verification work.
I used Perl for testing Verilog designs back in ~2002. Going from memory, I wrote my designs and test benches in Verilog, had the test benches generate "ok"/ "not ok" messages, wrote *.t Perl scripts to run each design/ test bench through the Verilog simulator (Icarus), and wrote a top-level Perl script that used Test::Harness to process the *.t scripts. I can't remember if the "1..N" messages were in the test bench or the *.t script. But, it worked great! :-) David -- To unsubscribe, e-mail: beginners-unsubscr...@perl.org For additional commands, e-mail: beginners-h...@perl.org http://learn.perl.org/
