Hey Christian,
On 19/08/2024 13:21, Christian König wrote:
Am 19.08.24 um 09:21 schrieb Friedrich Vock:
In Vulkan, it is the application's responsibility to perform adequate
synchronization before a sparse unmap, replace or BO destroy operation.
This adds an option to AMDGPU_VA_OPs to disable r
Hello Alex
On 09/09/2024 22:31, Alex Deucher wrote:
On Mon, Sep 9, 2024 at 4:18 PM Shashank Sharma wrote:
From: Shashank Sharma
This reverts commit 81af32520e7aaa337fe132f16c12ce54170187ea.
This commit prevents a usermode queue client to get the shadow related
information.
Signed-off-by: S
Hey Christian,
On 01/02/2024 14:48, Christian König wrote:
Am 31.01.24 um 18:14 schrieb Shashank Sharma:
This patch:
- Attaches the TLB flush fence to the PT objects being freed
- Adds a new ptr in VM to save this last TLB flush fence
- Adds a new lock in VM to prevent out-of-context update o
[AMD Official Use Only - General]
Please feel free to use:
Reviewed-by: Shashank Sharma
Regards
Shashank
From: Christian König
Sent: Monday, February 26, 2024 3:45 PM
To: Sharma, Shashank ; amd-gfx@lists.freedesktop.org
Cc: Koenig, Christian ; Deucher
On 26/02/2024 17:52, Philip Yang wrote:
On 2024-02-23 08:42, Shashank Sharma wrote:
This patch:
- adds a new list in amdgou_vm to hold the VM PT entries being freed
- waits for the TLB flush using the vm->tlb_flush_fence
- actually frees the PT BOs
V2: rebase
V3: Do not attach the tlb_fence
On 01/03/2024 13:59, Christian König wrote:
Am 01.03.24 um 12:07 schrieb Shashank Sharma:
From: Christian König
The problem is that when (for example) 4k pages are replaced
with a single 2M page we need to wait for change to be flushed
out by invalidating the TLB before the PT can be freed.
On 01/03/2024 18:07, Felix Kuehling wrote:
On 2024-02-05 12:05, Shashank Sharma wrote:
This patch changes the handling and lifecycle of vm->task_info object.
The major changes are:
- vm->task_info is a dynamically allocated ptr now, and its uasge is
reference counted.
- introducing two new h
On 01/03/2024 14:29, Christian König wrote:
Am 01.03.24 um 12:07 schrieb Shashank Sharma:
The idea behind this patch is to delay the freeing of PT entry objects
until the TLB flush is done.
This patch:
- Adds a tlb_flush_waitlist which will keep the objects that need to be
freed after tl
On 07/03/2024 00:54, Felix Kuehling wrote:
On 2024-03-06 09:41, Shashank Sharma wrote:
From: Christian König
The problem is that when (for example) 4k pages are replaced
with a single 2M page we need to wait for change to be flushed
out by invalidating the TLB before the PT can be freed.
S
On 07/03/2024 20:22, Philip Yang wrote:
On 2024-03-06 09:41, Shashank Sharma wrote:
From: Christian König
The problem is that when (for example) 4k pages are replaced
with a single 2M page we need to wait for change to be flushed
out by invalidating the TLB before the PT can be freed.
Solv
On 12/03/2024 09:31, Christian König wrote:
Am 11.03.24 um 15:37 schrieb Sharma, Shashank:
On 07/03/2024 20:22, Philip Yang wrote:
On 2024-03-06 09:41, Shashank Sharma wrote:
From: Christian König
The problem is that when (for example) 4k pages are replaced
with a single 2M page we need
On 14/03/2024 06:58, Khatri, Sunil wrote:
On 3/14/2024 2:06 AM, Alex Deucher wrote:
On Tue, Mar 12, 2024 at 8:42 AM Sunil Khatri
wrote:
Add firmware version information of each
IP and each instance where applicable.
Is there a way we can share some common code with devcoredump,
debugfs, a
[AMD Official Use Only - General]
Already sent a NULL check patch based on this backtrace, I am waiting for
Rajneesh's feedback.
Regards
Shashank
From: Bhardwaj, Rajneesh
Sent: Monday, March 18, 2024 3:04 PM
To: Sharma, Shashank ; amd-gfx@lists.freedeskto
On 18/03/2024 15:58, Christian König wrote:
Am 18.03.24 um 13:08 schrieb Shashank Sharma:
From: Christian Koenig
The problem is that when (for example) 4k pages are replaced
with a single 2M page we need to wait for change to be flushed
out by invalidating the TLB before the PT can be freed.
On 18/03/2024 16:01, Christian König wrote:
Am 18.03.24 um 15:44 schrieb Shashank Sharma:
The idea behind this patch is to delay the freeing of PT entry objects
until the TLB flush is done.
This patch:
- Adds a tlb_flush_waitlist in amdgpu_vm_update_params which will
keep the
objects tha
On 18/03/2024 19:10, Christian König wrote:
Am 18.03.24 um 17:11 schrieb Shashank Sharma:
From: Christian Koenig
The problem is that when (for example) 4k pages are replaced
with a single 2M page we need to wait for change to be flushed
out by invalidating the TLB before the PT can be freed.
, Alexander
; Sharma, Shashank
Subject: [PATCH v9 1/2] drm/amdgpu: implement TLB flush fence
Caution: This message originated from an External Source. Use proper caution
when opening attachments, clicking links, or responding.
From: Christian Koenig
The problem is that when (for example) 4k pages
On 18/03/2024 16:24, Christian König wrote:
Am 18.03.24 um 16:22 schrieb Sharma, Shashank:
On 18/03/2024 16:01, Christian König wrote:
Am 18.03.24 um 15:44 schrieb Shashank Sharma:
The idea behind this patch is to delay the freeing of PT entry objects
until the TLB flush is done.
This
On 23/03/2024 15:52, Johannes Weiner wrote:
On Thu, Mar 14, 2024 at 01:09:57PM -0400, Johannes Weiner wrote:
Hello,
On Fri, Mar 08, 2024 at 12:32:33PM +0100, Christian König wrote:
Am 07.03.24 um 23:07 schrieb Johannes Weiner:
Lastly I went with an open loop instead of a memcpy() as I wasn'
[AMD Official Use Only - General]
Hey Alex,
Sure, I will pick it up and push it to staging.
Regards
Shashank
From: Alex Deucher
Sent: Monday, March 25, 2024 12:23 AM
To: Sharma, Shashank
Cc: Johannes Weiner ; Christian König
; Deucher, Alexander
; Koenig
[AMD Official Use Only - General]
From: amd-gfx on behalf of Liu, Shaoyun
Sent: Monday, March 25, 2024 1:58 PM
To: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu : Increase the mes log buffer size as per new
MES FW version
[AMD Official Use
Thanks for the patch,
Patch pushed for staging.
Regards
Shashank
On 25/03/2024 00:23, Alex Deucher wrote:
On Sat, Mar 23, 2024 at 4:47 PM Sharma, Shashank
wrote:
On 23/03/2024 15:52, Johannes Weiner wrote:
On Thu, Mar 14, 2024 at 01:09:57PM -0400, Johannes Weiner wrote:
Hello,
On Fri
Hey Lang,
On 03/04/2024 08:51, Yu, Lang wrote:
[AMD Official Use Only - General]
-Original Message-
From: Christian König
Sent: Tuesday, April 2, 2024 9:38 PM
To: Yu, Lang ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christian
; Sharma, Shashank
Subject: Re
On 03/04/2024 09:31, Yu, Lang wrote:
[AMD Official Use Only - General]
-Original Message-
From: Sharma, Shashank
Sent: Wednesday, April 3, 2024 3:19 PM
To: Yu, Lang ; Christian König
; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christian
Subject: Re: [PATCH] drm
Hi Alex,
On 02/04/2024 02:42, Liu, Shaoyun wrote:
[AMD Official Use Only - General]
[AMD Official Use Only - General]
Comments inline
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Saturday, March 30, 2024 10:01 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alex
On 05/04/2024 17:26, Joshi, Mukul wrote:
[AMD Official Use Only - General]
-Original Message-
From: amd-gfx On Behalf Of
Shashank Sharma
Sent: Friday, April 5, 2024 10:36 AM
To: amd-gfx@lists.freedesktop.org
Cc: Sharma, Shashank ; Koenig, Christian
; Deucher, Alexander
; Yadav
On 05/04/2024 18:39, Joshi, Mukul wrote:
[AMD Official Use Only - General]
-Original Message-
From: Sharma, Shashank
Sent: Friday, April 5, 2024 11:37 AM
To: Joshi, Mukul ; amd-gfx@lists.freedesktop.org
Cc: Koenig, Christian ; Deucher, Alexander
; Yadav, Arvind
Subject: Re: [PATCH
Hey Alex,
On 01/05/2024 22:39, Alex Deucher wrote:
On Fri, Apr 26, 2024 at 10:07 AM Shashank Sharma
wrote:
From: Alex Deucher
This patch intorduces new UAPI/IOCTL for usermode graphics
queue. The userspace app will fill this structure and request
the graphics driver to add a graphics work qu
On 01/05/2024 22:50, Alex Deucher wrote:
On Fri, Apr 26, 2024 at 9:48 AM Shashank Sharma wrote:
A Memory queue descriptor (MQD) of a userqueue defines it in
the hw's context. As MQD format can vary between different
graphics IPs, we need gfx GEN specific handlers to create MQDs.
This patch:
On 01/05/2024 23:11, Alex Deucher wrote:
On Fri, Apr 26, 2024 at 10:07 AM Shashank Sharma
wrote:
The FW expects us to allocate at least one page as context
space to process gang, process, GDS and FW related work.
This patch creates a joint object for the same, and calculates
GPU space offset
On 01/05/2024 23:36, Alex Deucher wrote:
On Fri, Apr 26, 2024 at 9:57 AM Shashank Sharma wrote:
To support oversubscription, MES FW expects WPTR BOs to
be mapped into GART, before they are submitted to usermode
queues. This patch adds a function for the same.
V4: fix the wptr value before ma
On 01/05/2024 22:41, Alex Deucher wrote:
On Fri, Apr 26, 2024 at 10:27 AM Shashank Sharma
wrote:
This patch does necessary modifications to enable the SDMA
usermode queues using the existing userqueue infrastructure.
V9: introduced this patch in the series
Cc: Christian König
Cc: Alex Deuc
On 01/05/2024 22:44, Alex Deucher wrote:
On Fri, Apr 26, 2024 at 10:27 AM Shashank Sharma
wrote:
From: Arvind Yadav
This patch does the necessary changes required to
enable compute workload support using the existing
usermode queues infrastructure.
Cc: Alex Deucher
Cc: Christian Koenig
S
On 02/05/2024 07:23, Sharma, Shashank wrote:
Hey Alex,
On 01/05/2024 22:39, Alex Deucher wrote:
On Fri, Apr 26, 2024 at 10:07 AM Shashank Sharma
wrote:
From: Alex Deucher
This patch intorduces new UAPI/IOCTL for usermode graphics
queue. The userspace app will fill this structure and
On 02/05/2024 15:06, Kasiviswanathan, Harish wrote:
[AMD Official Use Only - General]
-Original Message-
From: amd-gfx On Behalf Of Sharma,
Shashank
Sent: Thursday, May 2, 2024 1:32 AM
To: Alex Deucher
Cc: amd-gfx@lists.freedesktop.org; Yadav, Arvind ; Deucher, Alexander
; Koenig
On 02/05/2024 15:55, Alex Deucher wrote:
On Thu, May 2, 2024 at 1:47 AM Sharma, Shashank wrote:
On 01/05/2024 22:41, Alex Deucher wrote:
On Fri, Apr 26, 2024 at 10:27 AM Shashank Sharma
wrote:
This patch does necessary modifications to enable the SDMA
usermode queues using the existing
On 02/05/2024 16:10, Alex Deucher wrote:
On Thu, May 2, 2024 at 1:51 AM Sharma, Shashank wrote:
On 01/05/2024 22:44, Alex Deucher wrote:
On Fri, Apr 26, 2024 at 10:27 AM Shashank Sharma
wrote:
From: Arvind Yadav
This patch does the necessary changes required to
enable compute workload
On 02/05/2024 17:14, Christian König wrote:
Am 26.04.24 um 15:48 schrieb Shashank Sharma:
A Memory queue descriptor (MQD) of a userqueue defines it in
the hw's context. As MQD format can vary between different
graphics IPs, we need gfx GEN specific handlers to create MQDs.
This patch:
- Add
On 02/05/2024 17:18, Christian König wrote:
Am 26.04.24 um 15:48 schrieb Shashank Sharma:
To support oversubscription, MES FW expects WPTR BOs to
be mapped into GART, before they are submitted to usermode
queues. This patch adds a function for the same.
V4: fix the wptr value before mapping l
On 02/05/2024 17:19, Christian König wrote:
Am 26.04.24 um 15:48 schrieb Shashank Sharma:
Current MES GFX mask prevents FW to enable oversubscription. This patch
does the following:
- Fixes the mask values and adds a description for the same.
- Removes the central mask setup and makes it IP sp
On 02/05/2024 17:22, Christian König wrote:
Am 26.04.24 um 15:48 schrieb Shashank Sharma:
This patch:
- adds a kernel config option "CONFIG_DRM_AMD_USERQ_GFX"
- moves the usequeue initialization code for all IPs under
this flag
so that the userqueue works only when the config is enabled.
On 02/05/2024 17:22, Christian König wrote:
Am 26.04.24 um 15:48 schrieb Shashank Sharma:
This patch:
- adds a kernel config option "CONFIG_DRM_AMD_USERQ_GFX"
- moves the usequeue initialization code for all IPs under
this flag
so that the userqueue works only when the config is enabled.
On 02/05/2024 23:25, Alex Deucher wrote:
On Thu, May 2, 2024 at 1:27 PM Shashank Sharma wrote:
This patch adds:
- A new IOCTL function to create and destroy
- A new structure to keep all the user queue data in one place.
- A function to generate unique index for the queue.
V1: Worked on revi
Hello Brian,
(+Uma in cc)
Thanks for your comments, Let me try to fill-in for Harry to keep the
design discussion going. Please find my comments inline.
On 8/2/2021 10:00 PM, Brian Starkey wrote:
Hi,
Thanks for having a stab at this, it's a massive complex topic to
solve.
Do you have the th
Hi Satyajit,
On 8/10/2021 12:39 PM, Satyajit Sahu wrote:
VCN and VCE support multiple queues with different priority.
Use differnt encoder queue based on the priority set by UMD.
Signed-off-by: Satyajit Sahu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 35 +--
drivers
From 4841e5ba60e33ff798bde6cb69fbd7e137b6db9c Mon Sep 17 00:00:00 2001
From: Shashank Sharma
Date: Fri, 20 Aug 2021 10:20:02 +0530
Subject: [PATCH v2] drm/amdgpu/OLAND: clip the ref divider max value
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This p
[AMD Official Use Only]
Agree, on the similar note, which Gen is OLAND BTW 😊 ?
Regards
Shashank
-Original Message-
From: Koenig, Christian
Sent: Friday, August 20, 2021 12:08 PM
To: Sharma, Shashank ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: Re: [PATCH v2] drm
[AMD Official Use Only]
No problem, let me dig for this information.
Regards
Shashank
-Original Message-
From: Koenig, Christian
Sent: Friday, August 20, 2021 1:36 PM
To: Sharma, Shashank ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: Re: [PATCH v2] drm/amdgpu/OLAND
[AMD Official Use Only]
Please feel free to use:
Reviewed-by: Shashank Sharma
Regards
Shashank
-Original Message-
From: amd-gfx On Behalf Of Christian
König
Sent: Friday, August 20, 2021 2:01 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu: use
[Public]
Thanks Alex,
Regards
Shashank
-Original Message-
From: Alex Deucher
Sent: Friday, August 20, 2021 6:42 PM
To: Sharma, Shashank
Cc: Koenig, Christian ;
amd-gfx@lists.freedesktop.org; Deucher, Alexander
Subject: Re: [PATCH v2] drm/amdgpu/OLAND: clip the ref divider max value
Hi Christian,
I am a bit curious here.
I thought it would be a good idea to add a new SW priority level, so
that any other driver can also utilize this SW infrastructure.
So it could be like, if you have a HW which matches with SW priority
levels, directly map your HW queue to the SW priority
higher priority work queue, and their drivers might be
handling them in very similar ways.
- Shashank
Regards,
Christian.
Am 24.08.21 um 10:32 schrieb Sharma, Shashank:
Hi Christian,
I am a bit curious here.
I thought it would be a good idea to add a new SW priority level, so
that any other
t;vcn.inst[i].irq, 0,
-AMDGPU_RING_PRIO_DEFAULT,
-&adev->vcn.inst[i].sched_score);
+hw_prio,
&adev->vcn.inst[i].sched_score);
if (r)
return r;
}
Please feel free to use:
Reviewed-by: Shashank Sharma
- Shashank
On 8/26/2021 12:43 PM, Satyajit Sahu wrote:
Schedule the encode job in VCE/VCN encode ring
based on the priority set by UMD.
Signed-off-by: Satyajit Sahu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 30 +
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/
Hi Satyajit,
On 8/26/2021 12:43 PM, Satyajit Sahu wrote:
There are multiple rings available in VCN encode. Map each ring
to different priority.
Signed-off-by: Satyajit Sahu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 14 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 9
in such a way
that all IP sw_init changes to go into single patch, as patch 1 was
getting too big with that.
If it is not a problem with Christian, LGTM
Feel free to use: Reviewed-by: Shashank Sharma
- Shashank
Signed-off-by: Satyajit Sahu
---
drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4
On 8/26/2021 6:04 PM, Christian König wrote:
Am 26.08.21 um 14:31 schrieb Sharma, Shashank:
On 8/26/2021 5:54 PM, Christian König wrote:
Am 26.08.21 um 13:32 schrieb Sharma, Shashank:
Hi Satyajit,
On 8/26/2021 12:43 PM, Satyajit Sahu wrote:
There are multiple rings available in VCN
On 8/26/2021 5:55 PM, Christian König wrote:
Am 26.08.21 um 13:44 schrieb Sharma, Shashank:
On 8/26/2021 12:43 PM, Satyajit Sahu wrote:
Schedule the encode job in VCE/VCN encode ring
based on the priority set by UMD.
Signed-off-by: Satyajit Sahu
---
drivers/gpu/drm/amd/amdgpu
On 8/26/2021 5:54 PM, Christian König wrote:
Am 26.08.21 um 13:32 schrieb Sharma, Shashank:
Hi Satyajit,
On 8/26/2021 12:43 PM, Satyajit Sahu wrote:
There are multiple rings available in VCN encode. Map each ring
to different priority.
Signed-off-by: Satyajit Sahu
---
drivers/gpu/drm
On 9/2/2021 5:14 PM, Nirmoy Das wrote:
debugfs APIs returns encoded error so use
IS_ERR for checking return value.
References: https://gitlab.freedesktop.org/drm/amd/-/issues/1686
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 6 ++
drivers/gpu/drm/amd/amdg
On 9/2/2021 5:14 PM, Nirmoy Das wrote:
Use debugfs_create_file_size API for creating ring debugfs
file, also cleanup surrounding code.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 +---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c| 16 +---
d
On 9/3/2021 1:39 PM, Das, Nirmoy wrote:
On 9/3/2021 8:36 AM, Sharma, Shashank wrote:
On 9/2/2021 5:14 PM, Nirmoy Das wrote:
Use debugfs_create_file_size API for creating ring debugfs
file, also cleanup surrounding code.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu
On 9/3/2021 1:47 PM, Christian König wrote:
Yeah, sounds logical to me as well. Feel free to stick my rb on that as
well.
Christian.
Am 03.09.21 um 10:13 schrieb Das, Nirmoy:
Hi Christian and Shashank,
Please review the v2 : https://patchwork.freedesktop.org/patch/452175/
In v2, I am re
On 9/3/2021 9:44 PM, Das, Nirmoy wrote:
Hi Shashank,
On 9/3/2021 5:51 PM, Das, Nirmoy wrote:
On 9/3/2021 5:26 PM, Sharma, Shashank wrote:
On 9/3/2021 1:39 PM, Das, Nirmoy wrote:
On 9/3/2021 8:36 AM, Sharma, Shashank wrote:
On 9/2/2021 5:14 PM, Nirmoy Das wrote:
Use
On 9/5/2021 5:01 PM, Das, Nirmoy wrote:
On 9/5/2021 10:03 AM, Sharma, Shashank wrote:
On 9/3/2021 9:44 PM, Das, Nirmoy wrote:
Hi Shashank,
On 9/3/2021 5:51 PM, Das, Nirmoy wrote:
On 9/3/2021 5:26 PM, Sharma, Shashank wrote:
On 9/3/2021 1:39 PM, Das, Nirmoy wrote:
On 9/3/2021 8:36
On 1/11/2022 12:26 PM, Christian König wrote:
Am 11.01.22 um 08:12 schrieb Somalapuram Amaranath:
AMDGPURESET uevent added to notify userspace,
collect dump_stack and amdgpu_reset_reg_dumps
Signed-off-by: Somalapuram Amaranath
---
drivers/gpu/drm/amd/amdgpu/nv.c | 31 +
Hello Christian,
On 1/17/2022 11:37 AM, Christian König wrote:
Am 17.01.22 um 11:34 schrieb Somalapuram, Amaranath:
[SNIP]
Any suggestion how we can notify user space during this situation.
Well trace points should work. They use a ring buffer and are specially
made to work in such situatio
From 8144e60d9f80941dd9f8a53e4b468582aaa849b4 Mon Sep 17 00:00:00 2001
From: Shashank Sharma
Date: Fri, 21 Jan 2022 17:23:41 +0100
Subject: [PATCH 1/4] drm: add a new drm event for GPU reset
This patch adds a DRM uevent to indicate GPU reset event. A
userspace can register to this event and do s
From 1c5c552eeddaffd9fb3e7d45ece1b2b28fccc575 Mon Sep 17 00:00:00 2001
From: Somalapuram Amaranath
Date: Fri, 21 Jan 2022 14:19:10 +0530
Subject: [PATCH 3/4] drm/amdgpu: add reset register trace dump function for
gfx_v10_0
Implementation of register trace dump function on the AMD GPU resets
Si
From 899ec6060eb7d8a3d4d56ab439e4e6cdd74190a4 Mon Sep 17 00:00:00 2001
From: Somalapuram Amaranath
Date: Fri, 21 Jan 2022 14:19:42 +0530
Subject: [PATCH 4/4] drm/amdgpu/nv: add navi GPU reset handler
This patch adds a GPU reset handler for Navi ASIC family, which
typically dumps some of the regi
From c598dd586dd15fc5ae0a883a2e6f4094ec024085 Mon Sep 17 00:00:00 2001
From: Shashank Sharma
Date: Fri, 21 Jan 2022 17:33:10 +0100
Subject: [PATCH 2/4] drm/amdgpu: add work function for GPU reset
This patch adds a new work function, which will get scheduled
in event of a GPU reset, and will send
:
You probably can add the STB dump we worked on a while ago to your info
dump - a reminder
on the feature is here https://www.spinics.net/lists/amd-gfx/msg70751.html
Andrey
On 2022-01-21 15:34, Sharma, Shashank wrote:
From 899ec6060eb7d8a3d4d56ab439e4e6cdd74190a4 Mon Sep 17 00:00:00 2001
From
Hello Christian,
Thank for your comments, please fine mine inline:
On 1/24/2022 8:15 AM, Christian König wrote:
Am 21.01.22 um 21:34 schrieb Sharma, Shashank:
From 1c5c552eeddaffd9fb3e7d45ece1b2b28fccc575 Mon Sep 17 00:00:00 2001
From: Somalapuram Amaranath
Date: Fri, 21 Jan 2022 14:19:10
On 1/24/2022 8:17 AM, Christian König wrote:
Am 21.01.22 um 21:37 schrieb Sharma, Shashank:
From c598dd586dd15fc5ae0a883a2e6f4094ec024085 Mon Sep 17 00:00:00 2001
From: Shashank Sharma
Date: Fri, 21 Jan 2022 17:33:10 +0100
Subject: [PATCH 2/4] drm/amdgpu: add work function for GPU reset
On 1/24/2022 8:18 AM, Christian König wrote:
Am 21.01.22 um 21:34 schrieb Sharma, Shashank:
From 899ec6060eb7d8a3d4d56ab439e4e6cdd74190a4 Mon Sep 17 00:00:00 2001
From: Somalapuram Amaranath
Date: Fri, 21 Jan 2022 14:19:42 +0530
Subject: [PATCH 4/4] drm/amdgpu/nv: add navi GPU reset
On 1/24/2022 5:49 PM, Christian König wrote:
Am 24.01.22 um 17:46 schrieb Sharma, Shashank:
On 1/24/2022 8:17 AM, Christian König wrote:
Am 21.01.22 um 21:37 schrieb Sharma, Shashank:
From c598dd586dd15fc5ae0a883a2e6f4094ec024085 Mon Sep 17 00:00:00 2001
From: Shashank Sharma
Date
On 1/24/2022 5:48 PM, Christian König wrote:
Am 24.01.22 um 17:45 schrieb Sharma, Shashank:
Hello Christian,
Thank for your comments, please fine mine inline:
On 1/24/2022 8:15 AM, Christian König wrote:
Am 21.01.22 um 21:34 schrieb Sharma, Shashank:
From
On 1/24/2022 6:07 PM, Christian König wrote:
Am 24.01.22 um 18:00 schrieb Sharma, Shashank:
On 1/24/2022 5:48 PM, Christian König wrote:
Am 24.01.22 um 17:45 schrieb Sharma, Shashank:
Hello Christian,
Thank for your comments, please fine mine inline:
On 1/24/2022 8:15 AM, Christian
01-24 11:38, Sharma, Shashank wrote:
Hey Andrey,
That seems like a good idea, may I know if there is a trigger for STB
dump ? or is it just the infrastructure which one can use when they
feel a need to dump info ? Also, how reliable is the STB infra during
a reset ?
Regards
Shashank
On 1/24/2022
Hey Lijo,
I somehow missed to respond on this comment, pls find inline:
Regards
Shashank
On 1/22/2022 7:42 AM, Lazar, Lijo wrote:
On 1/22/2022 2:04 AM, Sharma, Shashank wrote:
From 899ec6060eb7d8a3d4d56ab439e4e6cdd74190a4 Mon Sep 17 00:00:00 2001
From: Somalapuram Amaranath
Date: Fri, 21
in design philosophy maybe :)
- Shashank
Thanks,
Lijo
-Original Message-
From: Sharma, Shashank
Sent: Friday, February 4, 2022 10:09 PM
To: Lazar, Lijo ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Somalapuram, Amaranath
; Koenig, Christian
Subject: Re: [PATCH 4/4] drm/amd
eader app. Even if we filter out the S3/S4 resets in
the kernel, the situation remains the same, isn't it ?
- Shashank
Thanks,
Lijo
-Original Message-----
From: Sharma, Shashank
Sent: Friday, February 4, 2022 10:29 PM
To: Lazar, Lijo ; amd-gfx@lists.freedesktop.org
Cc: Deucher,
On 2/4/2022 6:11 PM, Lazar, Lijo wrote:
BTW, since this is already providing a set of values it would be useful to
provide one more field as the reset reason - RAS error recovery, GPU hung
recovery or something else.
Adding this additional parameter instead of blocking something in
kernel
anks,
Lijo
Again, this opens scope for discussion. What if there is a GPU error
during suspend-reset, which is very probable case.
- Shashank
-Original Message-----
From: Sharma, Shashank
Sent: Friday, February 4, 2022 10:47 PM
To: Lazar, Lijo ; amd-gfx@lists.freedesktop.org
Cc: Deucher,
, February 4, 2022 1:41 PM
*To:* Sharma, Shashank ; Lazar, Lijo
; amd-gfx@lists.freedesktop.org
*Cc:* Somalapuram, Amaranath ; Koenig,
Christian
*Subject:* Re: [PATCH 4/4] drm/amdgpu/nv: add navi GPU reset handler
[Public]
[Public]
In the suspend and hibernate cases, we don't care
-gfx@lists.freedesktop.org
Cc: Koenig, Christian ; Deucher, Alexander
; Sharma, Shashank ;
Somalapuram, Amaranath
Subject: [PATCH 1/2] drm/amdgpu: add debugfs for reset registers list
List of register to be populated for dump collection during the GPU reset.
Signed-off-by: Somalapuram Amaranath
Amar,
Apart from the long comment,there are a few more bugs in the patch,
which I have mentioned here inline. Please check them out.
- Shashank
On 2/8/2022 9:18 AM, Christian König wrote:
Am 08.02.22 um 09:16 schrieb Somalapuram Amaranath:
List of register to be populated for dump collectio
On 2/8/2022 2:39 PM, Somalapuram, Amaranath wrote:
On 2/8/2022 4:43 PM, Sharma, Shashank wrote:
I thought we spoke and agreed about:
- Not doing dynamic memory allocation during a reset call,
as there is a redesign debugfs call will happen during the application
initialization and not
that if user doesn't define the list at
init, we will not send the trace_event().
Or was it kernel has a list, and user can modify if he wants to, and we
will dump the values as per the register list.
@Christian ?
Regards
Shashank
On 2/8/2022 3:18 PM, Sharma, Shashank wrote:
On 2/8/2022 2:3
uint32_t stuff. With those two changes in place, feel free to use
for this patch:
Reviewed-by: Shashank Sharma
- Shashank
On 2/8/2022 3:31 PM, Sharma, Shashank wrote:
>> User only update the list of reg offsets on init, there is no
>> predefined reg offset from kernel code.
I
On 2/10/2022 6:29 AM, Somalapuram, Amaranath wrote:
On 2/9/2022 1:17 PM, Christian König wrote:
Am 08.02.22 um 16:28 schrieb Alex Deucher:
On Tue, Feb 8, 2022 at 3:17 AM Somalapuram Amaranath
wrote:
Dump the list of register values to trace event on GPU reset.
Signed-off-by: Somalapuram
On 2/10/2022 8:38 AM, Christian König wrote:
Am 10.02.22 um 08:34 schrieb Somalapuram, Amaranath:
On 2/10/2022 12:39 PM, Christian König wrote:
Am 10.02.22 um 06:29 schrieb Somalapuram, Amaranath:
On 2/9/2022 1:17 PM, Christian König wrote:
Am 08.02.22 um 16:28 schrieb Alex Deucher:
On
On 2/10/2022 3:05 PM, Christian König wrote:
Am 10.02.22 um 14:18 schrieb Sharma, Shashank:
On 2/10/2022 8:38 AM, Christian König wrote:
Am 10.02.22 um 08:34 schrieb Somalapuram, Amaranath:
On 2/10/2022 12:39 PM, Christian König wrote:
Am 10.02.22 um 06:29 schrieb Somalapuram
[AMD Official Use Only - Internal Distribution Only]
Sure, let me try this out,
Regards
Shashank
-Original Message-
From: Christian König
Sent: Monday, February 15, 2021 5:15 PM
To: amd-gfx@lists.freedesktop.org; Sharma, Shashank
Subject: Re: [PATCH] drm/amdgpu: Set GTT_USWC flag to
property is getting set.
Did some negative testing also,
- Without this patch, Fremebuffer creation fails, no flips, and VRR property
doesn't set.
Regards
Shashank
-Original Message-
From: Christian König
Sent: Monday, February 15, 2021 5:15 PM
To: amd-gfx@lists.freedesktop.org; S
, Christian
Sent: Wednesday, November 4, 2020 3:35 PM
To: Sharma, Shashank ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Qin, Eddy
Subject: Re: [PATCH] drm/amdgpu: clip the ref divider max value at 100
Am 03.11.20 um 18:13 schrieb Shashank Sharma:
> This patch limits the ref_div_
[AMD Public Use]
Thanks Alex, Christian,
Let me quickly run this patch through someone in DAL team, and see how it looks.
Regards
Shashank
From: Deucher, Alexander
Sent: Wednesday, November 4, 2020 8:03 PM
To: Koenig, Christian ; Sharma, Shashank
; amd-gfx@lists.freedesktop.org
Cc: Qin, Eddy
Looks good to me, Please feel free to use:
Reviewed-by: Shashank Sharma
Regards
Shashank
-Original Message-
From: Christian König
Sent: Tuesday, December 8, 2020 11:01 PM
To: amd-gfx@lists.freedesktop.org
Cc: Sharma, Shashank
Subject: [PATCH] drm/amdgpu: limit the
[AMD Official Use Only - General]
Hey Christian,
Will do that.
Regards
Shashank
-Original Message-
From: Koenig, Christian
Sent: Monday, September 11, 2023 1:15 PM
To: André Almeida ; dri-de...@lists.freedesktop.org;
amd-gfx@lists.freedesktop.org; linux-ker...@vger.kernel.org; Sharma
@lists.freedesktop.org; linux-ker...@vger.kernel.org; Sharma, Shashank
Cc: kernel-...@igalia.com; Deucher, Alexander ;
Pelloux-Prayer, Pierre-Eric
Subject: Re: [PATCH v6 1/5] drm/amdgpu: Allocate coredump memory in a
nonblocking way
Am 11.09.23 um 05:00 schrieb André Almeida:
> During a GPU reset, a normal mem
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