On 8/26/2021 12:43 PM, Satyajit Sahu wrote:
Schedule the encode job in VCE/VCN encode ring based on the priority set by UMD. Signed-off-by: Satyajit Sahu <satyajit.s...@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 30 +++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index c88c5c6c54a2..4e6e4b6ea471 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -120,6 +120,30 @@ static enum gfx_pipe_priority amdgpu_ctx_prio_to_compute_prio(int32_t prio) } }+static enum gfx_pipe_priority amdgpu_ctx_sched_prio_to_vce_prio(int32_t prio)+{ + switch (prio) { + case AMDGPU_CTX_PRIORITY_HIGH: + return AMDGPU_VCE_ENC_PRIO_HIGH; + case AMDGPU_CTX_PRIORITY_VERY_HIGH: + return AMDGPU_VCE_ENC_PRIO_VERY_HIGH; + default: + return AMDGPU_VCE_ENC_PRIO_NORMAL; + } +} + +static enum gfx_pipe_priority amdgpu_ctx_sched_prio_to_vcn_prio(int32_t prio) +{ + switch (prio) { + case AMDGPU_CTX_PRIORITY_HIGH: + return AMDGPU_VCN_ENC_PRIO_HIGH; + case AMDGPU_CTX_PRIORITY_VERY_HIGH: + return AMDGPU_VCN_ENC_PRIO_VERY_HIGH; + default: + return AMDGPU_VCN_ENC_PRIO_NORMAL; + } +} + static unsigned int amdgpu_ctx_get_hw_prio(struct amdgpu_ctx *ctx, u32 hw_ip) { struct amdgpu_device *adev = ctx->adev; @@ -133,6 +157,12 @@ static unsigned int amdgpu_ctx_get_hw_prio(struct amdgpu_ctx *ctx, u32 hw_ip) case AMDGPU_HW_IP_COMPUTE: hw_prio = amdgpu_ctx_prio_to_compute_prio(ctx_prio); break; + case AMDGPU_HW_IP_VCE: + hw_prio = amdgpu_ctx_sched_prio_to_vce_prio(ctx_prio); + break; + case AMDGPU_HW_IP_VCN_ENC: + hw_prio = amdgpu_ctx_sched_prio_to_vcn_prio(ctx_prio); + break; default: hw_prio = AMDGPU_RING_PRIO_DEFAULT; break;
IMO, this patch can be split and merged into patches 3 and 4 respectively, but is not a dealbreaker for me.
- Shashank
