From: Sung Joon Kim
[why & how]
There were some fixes in dcn35 that need
to be ported over to dcn351 to prevent any
regression.
Signed-off-by: Sung Joon Kim
Reviewed-by: Liu, Xi (Alex)
---
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c| 9 ++---
drivers/gpu/drm/amd/displa
From: Roman Li
This DC patchset brings improvements in multiple areas. In summary, we have:
- Fix underflow in subvp/non-subvp configs
- Fix compiler warnings
- Add handling for DC power mode
- Add extra logging for DMUB, HUBP and OTG
- Add timing pixel encoding for mst mode validation
- Expand
From: Hersen Wu
[Why] Mode pbn is not calculated correctly because timing pixel encoding is
not checked within convert_dc_color_depth_into_bpc.
[How] Get mode kbps from dc_bandwidth_in_kbps_from_timing, then calculate
pbn by kbps_to_peak_pbn.
Reviewed-by: Wayne Lin
Acked-by: Roman Li
Signed-o
From: Wenjing Liu
[why]
There could be cases that we are transition from MPC to ODM combine.
In this case if we map pipes before unmapping MPC pipes, we might
temporarly run out of pipes. The change reorders pipe resource
allocation. So we unmapping pipes before mapping new pipes.
Reviewed-by: D
From: Mounika Adhuri
[why & how]
Modified definitions of 1 function and 2 structs to remove warnings on
certain specific compiler configurations due to redefinition.
Reviewed-by: Martin Leung
Acked-by: Roman Li
Signed-off-by: Mounika Adhuri
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/
From: Samson Tam
[Why]
In two display configuration, switching between subvp and non-subvp
may cause underflow because it moves an existing pipe between
displays
[How]
Create helper function for applying pipe split flags
Apply pipe split flags prior to deciding on subvp
During subvp check, do
From: Roman Li
[Why]
dcn351 dmub fw was decoupled from dcn35.
[How]
Add dcn351 dmub fw load path.
Reviewed-by: Rodrigo Siqueira
Acked-by: Roman Li
Signed-off-by: Roman Li
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++-
1 file changed, 6 insertio
From: Joshua Aberback
[Why]
The function to count the number of valid connectors does not
guarantee that the first n indices are valid, only that there
exist n valid indices. When invalid indices are present, this
results in later valid connectors being missed, as processing
would end after check
From: Leon Huang
[Why]
Dmub provides several Replay residency calculation methods,
but current interface only supports either ALPM or PHY mode
[How]
Modify the interface for supporting different types
of Replay residency calculation.
Reviewed-by: Robin Chen
Acked-by: Roman Li
Signed-off-by: L
From: Daniel Miess
[Why]
With root clock optimization now enabled for DCN35 there
are still RCO registers still not being toggled
[How]
Add in logic to toggle RCO registers for DPPCLK,
DPSTREAMCLK and DSCCLK
Reviewed-by: Charlene Liu
Acked-by: Roman Li
Signed-off-by: Daniel Miess
Tested-by:
From: Sung Joon Kim
[why]
As per programming guide, we need to
enable the virtual pixel clock via DTBCLK
DTO and ungate the clock before we begin
programming OPP/OPTC control registers.
Otherwise, the double-buffered registers
will be left pending until the clocks are enabled.
[how]
Move the DTB
From: Dillon Varone
[WHY&HOW]
Update dmub and driver interface for future FAMS revisions.
Reviewed-by: Anthony Koo
Acked-by: Roman Li
Signed-off-by: Dillon Varone
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 2 +-
drivers/gpu/drm/amd/display/dc/hws
From: George Shen
[Why/How]
Some issues may require a trace of the previous SMU messages from DC to
understand the context and aid in debugging. Actual logging to be
implemented when needed.
Reviewed-by: Josip Pavic
Acked-by: Roman Li
Signed-off-by: George Shen
Tested-by: Daniel Wheeler
---
From: Hersen Wu
[Why] Mst slot nums equals to pbn / pbn_div.
Today, pbn_div refers to dm_mst_get_pbn_divider ->
dc_link_bandwidth_kbps. In dp_link_bandwidth_kbps,
which includes effect of FEC overhead already. As
result, we should not include effect of FEC overhead
again while calculating pbn by
From: Wenjing Liu
[why]
There is an ambiguity in subvp pipe topology log. The log doesn't show
subvp relation to main stream and it is not clear that certain stream
is an internal stream for subvp pipes.
[how]
Separate subvp pipe topology logging from main pipe topology. Log main
stream indices
From: Duncan Ma
[Why]
HPO can be power gated unconditionally for
DCN35.
[How]
Set disable flag to false.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Roman Li
Signed-off-by: Duncan Ma
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c | 2 +-
1 file
From: Alvin Lee
[Description]
Add extra logging for DCSURF_FLIP_CNTL, DCHUBP_CNTL,
OTG_MASTER_EN, and OTG_DOUBLE_BUFFER_CONTROL for more
debuggability for a system crash.
Reviewed-by: Samson Tam
Acked-by: Roman Li
Signed-off-by: Alvin Lee
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/di
From: Alex Hung
[WHY]
dynamic memory safety error detector (KASAN) catches and generates error
messages "BUG: KASAN: slab-out-of-bounds" as writeback connector does not
support certain features which are not initialized.
[HOW]
Skip them when connector type is DRM_MODE_CONNECTOR_WRITEBACK.
Link:
From: "Leo (Hanghong) Ma"
[Why && How]
OTG can be disabled before setting dpms on. Add check to skip wait
when setting AV mute if OTG is disabled.
Reviewed-by: Wenjing Liu
Acked-by: Roman Li
Signed-off-by: Leo (Hanghong) Ma
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/hwss/d
From: Daniel Miess
[Why & How]
Enable root clock optimization for HDMISTREAMCLK and only
disable it when it's actively being used.
Reviewed-by: Charlene Liu
Acked-by: Roman Li
Signed-off-by: Daniel Miess
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dc.h| 1 +
From: Alvin Lee
[Description]
- Add logging for first DMUB inbox message that timed out to diagnostic
data
- It is useful to track the first failed message for debug purposes
because once DMUB becomes hung (typically on a message), it will
remain hung and all subsequent messages. In these c
From: Nicholas Kazlauskas
[Why]
The threshold is no longer useful for blocking suboptimal power states
for DCN35 based on real measurement.
[How]
Reduce to the minimum threshold duration, 1us.
Reviewed-by: Gabe Teeger
Acked-by: Roman Li
Signed-off-by: Nicholas Kazlauskas
Tested-by: Daniel Wh
From: Wenjing Liu
[why]
Move built test pattern as part of pipe resource update for odm to ensure we
rebuild
test pattern params every time we have an ODM update
Reviewed-by: George Shen
Acked-by: Roman Li
Signed-off-by: Wenjing Liu
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display
From: Joshua Aberback
[Why]
Future implementations will require a distinction between AC power and
DC power (wall power and battery power, respectively). To accomplish this,
adding a power mode parameter to certain dc interfaces, and adding a
separate DML2 instance for DC mode validation. Default
From: "Xi (Alex) Liu"
[Why and how]
External display has corruption because no root clock control function. Add the
function pointer to fix the issue.
Reviewed-by: Daniel Miess
Reviewed-by: Nicholas Kazlauskas
Acked-by: Roman Li
Signed-off-by: Xi (Alex) Liu
Tested-by: Daniel Wheeler
---
From: Joshua Aberback
[Why]
When the DML2 wrapper explicitly accesses context->dml2, that creates a
dependency on where dc saves the DML object. This dependency makes it
harder to have multiple co-existing DML objects, which we would like to
have for upcoming functionality.
[How]
- make all DML
From: Aric Cyr
This version pairs with DMUB FW Release 0.0.211.0 for dcn314, dcn35, dcn351
and brings along the following:
- Fix underflow in subvp/non-subvp configs
- Fix compiler warnings
- Add handling for DC power mode
- Add extra logging for DMUB, HUBP and OTG
- Add timing pixel encodi
From: Rodrigo Siqueira
This commit adds some comments to make easier to understand the clock
update for DCN 201, the encode function, and other minor comments.
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
.../amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c| 11 +++
From: Roman Li
[Why]
We want to block IPS2 for static screen but allow it for power state
transitions.
[How]
Set DalDisableIPS=6 for DCN35 which allows:
1. RCG during static screen
2. RCG during LVP
3. IPS2 for display off / S0i3
Reviewed-by: Nicholas Kazlauskas
Acked-by: Roman Li
Signed-off-
From: Aric Cyr
[why]
Enabling higher compiler warning levels results in many issues that can
be trivially resolved as well as some potentially critical issues.
[how]
Fix all compiler warnings found with various compilers and higher
warning levels. Primarily, potentially uninitialized variables
From: Rodrigo Siqueira
Adjust bytes per pixel calculation to use div_u64.
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/ds
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
b/drivers/gpu/drm/amd/display/d
From: Rodrigo Siqueira
This commit drops the RESERVE0 and RESERVE1 since both of them can be
summarized as RESERVED.
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a
From: Rodrigo Siqueira
Set alpha_en to 0 in some specific color formats.
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dp
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
b/drivers/gpu/dr
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c| 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
b/drivers/gpu/drm/amd/dis
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_inp
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
.../include/asic_reg/dcn/dcn_3_0_3_offset.h | 20 +++
.../include/asic_reg/dcn/dcn_3_0_3_sh_mask.h | 11
.../include/asic_reg/dcn/dcn_3_1_2_offset.h | 4 ++
.../include/asic_reg/dcn/dcn_3_1_2_sh
From: Eric Bernstein
[Why]
DTN only logs 'pipe_count' instances of MPCC.
However in some cases there are different number of
MPCC than DPP (pipe_count).
[How]
Add mpcc_count parameter to resource_pool and set it
during pool construction and use it for DTN logging of
MPCC state.
Signed-off-by: E
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dc_dp_types.h| 10 --
.../amd/display/dc/gpio/dcn21/hw_translate_dcn21.c | 13 -
2 files changed, 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/d
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
.../drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h | 4
.../include/asic_reg/dcn/dcn_3_0_0_offset.h | 24 +++
.../include/asic_reg/dcn/dcn_3_0_0_sh_mask.h | 9 +++
.../include/asic_reg
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
b/drivers/gpu/drm/amd/display/dc/dcn
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dc
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_
From: Rodrigo Siqueira
This commit clean up some of the includes used by DCN.
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c | 4
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.c | 2 --
.../gpu/drm
From: Roman Li
[Why]
htmldocs warning:
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h: warning:
Function parameter or struct member 'idle_workqueue' not described in
'amdgpu_display_manager'.
[How]
Add comment section for idle_workqueue with param description.
Reported-by: Stephen Rothwell
From: Roman Li
Cc: Daniel Wheeler
Aurabindo Pillai (1):
drm/amd/display: remove an extraneous call for checking dchub clock
Austin Zheng (1):
drm/amd/display: DML2.1 Reintegration for Various Fixes
Fangzhi Zuo (1):
drm/amd/display: Fix a typo in revert commit
Hansen Dsouza (1):
Rever
From: Hansen Dsouza
[Why]
Revert updated DCCG wrappers due to regression
[How]
This reverts commit 28b190df7a8f43b39e13886d744742a74a2c162d.
Reviewed-by: Chris Park
Signed-off-by: Hansen Dsouza
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c | 4 ++--
1 fi
From: Aurabindo Pillai
when removing the amdgpu module and reinserting it, a call trace is
triggered:
[ 334.230602] RIP: 0010:hubbub2_get_dchub_ref_freq+0xbb/0xe0 [amdgpu]
[ 334.230807] Code: 25 28 00 00 00 75 3c 48 8d 65 f0 5b 41 5c 5d 31 c0 31 d2
31 c9 31 f6 31 ff 45 31 c0 45 31 c9 45 31 d2
From: Sung Joon Kim
[why]
Supporting UHBR10 link rate on eDP leverages
the existing DP2.0 code but need to add some small
adjustments in code.
[how]
Acknowledge the given DPCD caps for UHBR10
link rate support and allow DP2.0 programming
sequence and link training for eDP.
Reviewed-by: Wenjing
From: Nevenko Stupar
[Why & How]
DCN4 Cursor has separate degamma block and should always
do Cursor degamma for Cursor color modes.
Reviewed-by: Chris Park
Signed-off-by: Nevenko Stupar
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c | 5 ++---
1 file ch
From: Nicholas Susanto
[Why]
Causes hard hangs when resuming after display off on extended/duplicate
modes
[How]
Set the min dispclk to 50Mhz for DCN35
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Nicholas Susanto
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35
From: Michael Strauss
[WHY]
eDP 2.0 is introducing support for UHBR link rates, however current eDP ILR
link optimization does not account for UHBR capabilities.
Either UHBR capabilities will be provided via the same 128b/132b rate DPCD caps
that are currently used on DP2.1, or Table 4-13 may be
From: Michael Strauss
[WHY]
Previous multi-display HPO fix moved where HPO I/O enable/disable is performed.
The codepath now taken to enable/disable HPO I/O is not used for compliance
test automation, meaning that if a compliance box being driven at a DP1 rate
requests retrain at UHBR, HPO I/O wi
From: Nicholas Susanto
Removing redundant condition.
Reviewed-by: Hansen Dsouza
Signed-off-by: Nicholas Susanto
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
From: Ilya Bakoulin
[Why/How]
The call to construct_phy will fail in cases where connector type is
MXM, and the dc_link won't be properly created/initialized.
Reviewed-by: Wenjing Liu
Signed-off-by: Ilya Bakoulin
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/link/link_factory.c
From: Tim Huang
Flexible endpoints use DIGs from available inflexible endpoints,
so only the encoders of inflexible links need to be freed.
Otherwise, a double free issue may occur when unloading the
amdgpu module.
[ 279.190523] RIP: 0010:__slab_free+0x152/0x2f0
[ 279.190577] Call Trace:
[ 27
From: Austin Zheng
[Why and How]
DML2.1 reintegration for several fixes and updates to the DML
code.
Reviewed-by: Dillon Varone
Signed-off-by: Austin Zheng
Signed-off-by: Roman Li fams2_required =
display_cfg->stage3.fams2_required;
dml2_core_calcs_get_global_fams2_programm
From: Fangzhi Zuo
A typo is fixed for "drm/amd/display: Fix MST BW calculation Regression"
Fixes: 4b6564cb120c ("drm/amd/display: Fix MST BW calculation Regression")
Reviewed-by: Roman Li
Signed-off-by: Fangzhi Zuo
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_
From: Martin Leung
- Various DML 2.1 fixes
- Fix MST Regression
- Fix module unload
- Fix construct_phy with MXM connector
- Support UHBR10 link rate on eDP
- Revert updated DCCG wrappers
Signed-off-by: Martin Leung
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 fil
From: Roman Li
This DC patchset brings improvements in multiple areas. In summary, we have:
- Fix powerpc compilation
- Fix TBT+TypeC Daisy-chain lightup
- Fix underflow on dcn35
- Fix DVI for dcn401
- Add 3DLUT DMA load trigger
- Modify clock programming to support DPM
From: George Shen
Move dsc functions from dc.c to dc_dsc.c.
Co-Developed-by: George Shen
Signed-off-by: Wenjing Liu
Reviewed-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc.c| 99 -
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 96
From: Alex Hung
The comparisons intend to be DCN401 inclusive, and fix it by adding
equal signs.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/disp
From: Rodrigo Siqueira
The function that commits planes calls the same set of functions twice,
and in the case of the FAMs utilization, it is not desired to call the
dmub, hwss_build and hwss_execute. This commit just removes the
unnecessary calls to those functions.
Acked-by: Roman Li
Signed-o
From: Alex Hung
This fixes indentations and adjust spaces for better readability and
code styles.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile | 1 -
.../amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 1 -
drivers/gpu/dr
From: "Revalla, Harikrishna"
[why]
Cleaning up the code refactor requires hubbub to be in its own
component.
[how]
Move all DCN401 files under newly created hubbub folder and fixing the
makefiles.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Harikrishna Revalla
---
drivers/gpu/drm/amd/displa
From: Samson Tam
[Why]
Enable adaptive scaler support for DCN401
[How]
- Enable build flag for SPL
- Set prefer_easf flag to true
- Apply light linear scaling policy based on transfer function and pixel
format. Choose between linear or non-linear scaling
- Set matrix_mode based on pixel forma
From: Chris Park
[Why]
DVI is TMDS signal like HDMI but without audio. Current signal check
does not correctly reflect DVI clock programming.
[How]
Define a new signal check for TMDS that includes DVI to HDMI TMDS
programming.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Chris Park
---
drive
From: Chris Park
[Why]
DML 2.1 allocates two types of memory in its ctx structure but does not
destroy them, causing memory leak whenever DML 2.1 instance is created
and destroyed.
[How]
Deallocate two instances of allocated memory whenever DML 2.1 is
destroyed.
Reviewed-by: Rodrigo Siqueira
S
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c | 2 ++
drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c
b/dr
From: Dillon Varone
Need to select DTBCLK and DPREFCLK as DTBCLK_p source according to
hardware guidance.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --
From: Hersen Wu
[Why] Coverity reports NULL_RETURN warning.
[How] Add pointer NULL check.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Hersen Wu
---
.../gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/displ
From: Nicholas Susanto
[Why]
Missing check for when there is new pipe configuration but both cur_pipe
and new_pipe are both populated causing update_state of DSC for that
instance not being updated correctly.
This causes some display mode changes to cause underflow since DSCCLK
is still gated w
From: Roman Li
[Why]
For debugging and testing purposes.
[How]
If IPS is supported create ips_status debugfs entry.
Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_ips_status
Reviewed-by: Jerry Zuo
Acked-by: Roman Li
Signed-off-by: Roman Li
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 4
From: Ilya Bakoulin
[Why/How]
Need to be able to trigger a DMA load to update 3DLUT contents in MPC.
Adding a HWSS function to serve as the trigger.
Reviewed-by: Krunoslav Kovac
Acked-by: Roman Li
Signed-off-by: Ilya Bakoulin
---
drivers/gpu/drm/amd/display/dc/core/dc.c| 8
From: Dillon Varone
[WHY&HOW]
Disable to improve stability for now.
Reviewed-by: Alvin Lee
Acked-by: Roman Li
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/r
From: Dillon Varone
[WHY&HOW]
At the time of block sequence construction, the exact reference DPP/DISP clock
is
not yet known, so the clock should be passed by reference to the DTO programming
function.
Reviewed-by: Alvin Lee
Acked-by: Roman Li
Signed-off-by: Dillon Varone
---
.../dc/clk_mg
From: Wenjing Liu
The functions are missing. These two functions are required to support
MST.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Wenjing Liu
---
.../amd/display/dc/dccg/dcn401/dcn401_dccg.c | 159 ++
.../amd/display/dc/dccg/dcn401/dcn401_dccg.h | 12 ++
.../amd/di
From: Roman Li
[Why]
Disable idle optimization for each atomic commit is unnecessary,
and can lead to a potential race condition.
[How]
Remove idle optimization check from amdgpu_dm_atomic_commit_tail()
Fixes: 196107eb1e15 ("drm/amd/display: Add IPS checks before dcn register
access")
Cc: sta
From: Cruise
[Why]
When the link BW is smaller than the request BW,
the DP LT just kept running and fallback to lower link config.
DP LT just aborted if is_hpd_pending bit is high.
But is_hpd_pending bit indicates a new HPD event received.
It doesn't mean the HPD is low.
[How]
Abort the DP LT if
From: Wenjing Liu
[why]
A recent change for ODM combine refactor contains a typo which causes ODM
combine mode programmed incorrectly.
Reviewed-by: George Shen
Acked-by: Roman Li
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 2 +-
1 file changed, 1
From: Roman Li
[Why]
Reset the shared dmub firmware region on dmub hw init to start with
known state.
[How]
Memset the shared region to 0 in dmub_hw_init().
Suggested-by: Nicholas Kazlauskas
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/a
From: Aric Cyr
This version pairs with DMUB FW Release 0.0.218.0 for dcn314/315/316,
dcn35/351, dcn401
and brings along the following:
- Fix powerpc compilation
- Fix TBT+TypeC Daisy-chain lightup
- Fix ODM combine setup
- Fix OTC underflow on dcn35
- Fix DVI config for dcn401
- Add ips status
From: Alvin Lee
[Description]
There is a corner case where we're in an ODM config that
has recout.x != 0. In these scenarios we have to take into
account the extra offset in the ODM adjustment for cursor.
Reviewed-by: Aric Cyr
Acked-by: Roman Li
Signed-off-by: Alvin Lee
---
.../drm/amd/displ
From: Roman Li
[Why]
Compilation errors while compiling without CONFIG_DRM_AMD_DC_FP:
"undefined reference to `dc_bandwidth_in_kbps_from_timing'"
[How]
Fix Makefile to move dsc files out of DC_FP guard.
Fixes: 50253f5d9ff4 ("drm/amd/display: Add misc DC changes for DCN401")
Signed-off-by: Roman
From: Roman Li
[Why]
Instability is observed on DCN35 if idle power optimization is enabled.
[How]
Disable IPS until issue is resolved.
Signed-off-by: Roman Li
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: Roman Li
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Add power_state/pme_pending flag/usb4_bw_alloc_support flags
* Add GART memory support
* Improvements for HDMI, IPS, DML2 and others
Allen Pan (1):
drm/amd/display: Add NULL-checks in dml2 assi
From: "Leo (Hanghong) Ma"
[Why && How]
The current bandwidth calculation for timing doesn't account for
certain HDMI modes overhead which leads to DSC can't be enabled.
Add support to calculate the actual bandwidth for these HDMI modes.
Reviewed-by: Chris Park
Acked-by: Roman Li
Signed-off-by:
From: Muhammad Ahmed
[what]
Adding power_state to dc.h and pme_pending flag to clk_mgr_internal.h
Reviewed-by: Charlene Liu
Acked-by: Roman Li
Signed-off-by: Muhammad Ahmed
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_inter
From: Roman Li
[Why]
With IPS enabled a system hangs once PSR is active.
PSR active triggers transition to IPS2 state.
While in IPS2 an access to dcn registers results in hard hang.
Existing check doesn't cover for PSR sequence.
[How]
Safeguard register access by disabling idle optimization in a
From: Allen Pan
[Why]
NULL-deref regression after:
"drm/amd/display: Fix dml2 assigned pipe search"
[How]
Add verification for potential NULLs
Fixes: 133e813d5044 ("drm/amd/display: Fix dml2 assigned pipe search")
Reviewed-by: Charlene Liu
Reviewed-by: Nicholas Kazlauskas
Acked-by: Roman Li
From: Aric Cyr
Acked-by: Roman Li
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 1d052742d4c7..432ae08462e4 100644
--- a/drivers
From: Anthony Koo
- Add debug flag for Replay IPS visual confirm
- Remove unused debug flags that should not
be controlled inside Replay FSM
Acked-by: Roman Li
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 13 -
1 file changed, 4 insertions(
From: Charlene Liu
This reverts commit 080a7e9d7dc5a18401d0569a36d55e133ed10cf8.
It caused intermittent hangs when enabling IPS on static screen.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Roman Li
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 11 +-
From: Aric Cyr
- FW Release 0.0.201.0
- Fix resizing video window for dcn321
- Fix timing bandwidth calculation for HDMI
- Fix null-deref in dml2 assigned pipe search
- Add GART memory support for dmcub
- Add power_state and pme_pending flag
- Add usb4_bw_alloc_support flag
- Revert "Rework DC Z1
From: Fudongwang
[Why]
In dump file, GART memory can be accessed while frame buffer cannot.
[How]
Add GART memory support for dmcub.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Roman Li
Signed-off-by: Fudongwang
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 ++-
drivers/gpu/drm/amd
From: Peichen Huang
[Why]
dc should have a flag for DM to enable usb4_bw_alloc in dptx
[How]
- Add usb4_bw_alloc_support flag in dc_config
Reviewed-by: Wayne Lin
Reviewed-by: Meenakshikumar Somasundaram
Acked-by: Roman Li
Signed-off-by: Peichen Huang
---
drivers/gpu/drm/amd/display/dc/dc.h
From: ChunTao Tso
[Why]
Because ABM will wait VStart to start getting histogram data,
it will cause we can't enter IPS while full screnn video playing.
[How]
Modify the panel refresh rate to the maximun multiple of current
refresh rate.
Reviewed-by: Dennis Chan
Acked-by: Roman Li
Signed-off
From: Wenjing Liu
[why]
It has been found a regression caused by enabling this feature during ODM to
MPC combine switch when user is resizing video window. The transition is
only needed when the feature is enabled. During the transition driver will
temporary switch to use max dppclk level through
From: Roman Li
[Why]
While in IPS2 an access to dcn registers is not allowed.
If interrupt results in dc call, we should disable IPS.
[How]
Safeguard register access in IPS2 by disabling idle optimization
before calling dc interrupt setting api.
Signed-off-by: Roman Li
Tested-by: Mark Broadwor
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