From: Ilya Bakoulin <ilya.bakou...@amd.com>
[Why/How]
Need to be able to trigger a DMA load to update 3DLUT contents in MPC.
Adding a HWSS function to serve as the trigger.
Reviewed-by: Krunoslav Kovac <krunoslav.ko...@amd.com>
Acked-by: Roman Li <roman...@amd.com>
Signed-off-by: Ilya Bakoulin <ilya.bakou...@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 8 ++++++++
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 17 +++++++++++++----
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.h | 2 ++
.../amd/display/dc/hwss/dcn401/dcn401_init.c | 1 +
.../gpu/drm/amd/display/dc/hwss/hw_sequencer.h | 1 +
5 files changed, 25 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 1008fbc57dbd..3a2101b052ea 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -4074,6 +4074,14 @@ static void commit_planes_for_stream(struct dc *dc,
if (!should_update_pipe_for_plane(context,
pipe_ctx, plane_state))
continue;
+ if (srf_updates[i].cm2_params &&
+
srf_updates[i].cm2_params->cm2_luts.lut3d_data.lut3d_src ==
+
DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM &&
+
srf_updates[i].cm2_params->component_settings.shaper_3dlut_setting ==
+
DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT &&
+ dc->hwss.trigger_3dlut_dma_load)
+ dc->hwss.trigger_3dlut_dma_load(dc,
pipe_ctx);
+
/*program triple buffer after lock based on
flip type*/
if (dc->hwss.program_triplebuffer != NULL &&
dc->debug.enable_tri_buf) {
/*only enable triplebuffer for
fast_update*/
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index c3bed33eb5d6..a619da7716ed 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -498,9 +498,9 @@ void dcn401_populate_mcm_luts(struct dc *dc,
if (m_lut_params.pwl) {
if (mpc->funcs->populate_lut)
mpc->funcs->populate_lut(mpc, MCM_LUT_1DLUT,
m_lut_params, lut_bank_a, mpcc_id);
- if (mpc->funcs->program_lut_mode)
- mpc->funcs->program_lut_mode(mpc,
MCM_LUT_1DLUT, lut1d_xable, lut_bank_a, mpcc_id);
}
+ if (mpc->funcs->program_lut_mode)
+ mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT,
lut1d_xable, lut_bank_a, mpcc_id);
}
/* Shaper */
@@ -519,9 +519,9 @@ void dcn401_populate_mcm_luts(struct dc *dc,
if (m_lut_params.pwl) {
if (mpc->funcs->populate_lut)
mpc->funcs->populate_lut(mpc, MCM_LUT_SHAPER,
m_lut_params, lut_bank_a, mpcc_id);
- if (mpc->funcs->program_lut_mode)
- mpc->funcs->program_lut_mode(mpc,
MCM_LUT_SHAPER, shaper_xable, lut_bank_a, mpcc_id);
}
+ if (mpc->funcs->program_lut_mode)
+ mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER,
shaper_xable, lut_bank_a, mpcc_id);
}
/* 3DLUT */
@@ -635,6 +635,15 @@ void dcn401_populate_mcm_luts(struct dc *dc,
}
}
+void dcn401_trigger_3dlut_dma_load(struct dc *dc, struct pipe_ctx *pipe_ctx)
+{
+ struct hubp *hubp = pipe_ctx->plane_res.hubp;
+
+ if (hubp->funcs->hubp_enable_3dlut_fl) {
+ hubp->funcs->hubp_enable_3dlut_fl(hubp, true);
+ }
+}
+
bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx,
const struct dc_plane_state *plane_state)
{
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
index dd5bae93dc05..f91159a6e6d4 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
@@ -40,6 +40,8 @@ bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx,
bool dcn401_set_output_transfer_func(struct dc *dc,
struct pipe_ctx *pipe_ctx,
const struct dc_stream_state *stream);
+void dcn401_trigger_3dlut_dma_load(struct dc *dc,
+ struct pipe_ctx *pipe_ctx);
void dcn401_calculate_dccg_tmds_div_value(struct pipe_ctx *pipe_ctx,
unsigned int *tmds_div);
enum dc_status dcn401_enable_stream_timing(
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
index b9fcde08fdc8..8358ba74405f 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
@@ -24,6 +24,7 @@ static const struct hw_sequencer_funcs dcn401_funcs = {
.update_dchub = dcn10_update_dchub,
.update_pending_status = dcn10_update_pending_status,
.program_output_csc = dcn20_program_output_csc,
+ .trigger_3dlut_dma_load = dcn401_trigger_3dlut_dma_load,
.enable_accelerated_mode = dce110_enable_accelerated_mode,
.enable_timing_synchronization = dcn10_enable_timing_synchronization,
.enable_per_frame_crtc_position_reset =
dcn10_enable_per_frame_crtc_position_reset,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
index d2d1ba30f6ae..a9f2b7ee9dd8 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
@@ -304,6 +304,7 @@ struct hw_sequencer_funcs {
void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx,
enum dc_color_space colorspace,
uint16_t *matrix, int opp_id);
+ void (*trigger_3dlut_dma_load)(struct dc *dc, struct pipe_ctx
*pipe_ctx);
/* VM Related */
int (*init_sys_ctx)(struct dce_hwseq *hws,
--
2.34.1
