tches for achieving the complete
isolation of this file.
Signed-off-by: Rodrigo Siqueira
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/Makefile | 1 +
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 39 +---
.../drm/amd/display/dc/dcn20/dcn20_resource.h | 2 -
.../dr
We don't have any mechanism for tracing FPU operations inside the
display core, making the debug work a little bit tricky. For trying to
alleviate this problem, this commit introduces a trace mechanism inside
our DC_FP_START/END macros.
Signed-off-by: Rodrigo Siqueira
Acked-by: Rodrigo Siq
f the function is invoked under FP
protection. If not, it will trigger a kernel warning.
Signed-off-by: Rodrigo Siqueira
Acked-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/amdgpu_dm/dc_fpu.c| 34 ---
.../gpu/drm/amd/display/amdgpu_dm/dc_fpu.h| 1 +
.../drm/amd/displ
l FPU functions weekly until
we isolate everything in the fpu_operation folder.
Best Regards
Rodrigo Siqueira
Rodrigo Siqueira (4):
drm/amd/display: Introduce FPU directory inside DC
drm/amd/display: Add FPU event trace
drm/amd/display: Add ref count control for FPU utilization
drm/amd/dis
In general lgtm.
Reviewed-by: Rodrigo Siqueira
Mark Yacoub, do you have any comment?
On 04/05, Qingqing Zhuo wrote:
> This reverts commit 9f81b5d40ca2c689334ad8288a4ddca4722a6e10.
>
> The original commit was found to cause the following two issues
> on sienna cichlid:
> 1. Refr
like a duplicate cursor in applications that use multiple
planes. This commit fixes the cursor issue and others by adding adequate
verification for multiple planes.
Cc: Louis Li
Cc: Nicholas Kazlauskas
Cc: Harry Wentland
Cc: Hersen Wu
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/di
Harry Wentland
Cc: Hersen Wu
Cc: Sean Paul
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 51 +++
1 file changed, 51 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
Nice catch!
Are you using any tool to identify this problem?
Reviewed-by: Rodrigo Siqueira
On 04/29, Wan Jiabing wrote:
> In commit 482812d56698e ("drm/amd/display: Set max TTU on
> DPG enable"), "hubp.h" was added which caused the duplicate include.
> To be on th
/amd/display/dc/dc.h
> @@ -276,8 +276,6 @@ enum surface_update_type {
> /* Forward declaration*/
> struct dc;
> struct dc_plane_state;
> -struct dc_state;
> -
>
> struct dc_cap_funcs {
> bool (*get_dcc_compression_cap)(const struct dc *dc,
> --
> 2.25.1
&g
Reviewed-by: Rodrigo Siqueira
On 04/29, Wan Jiabing wrote:
> There are two declarations of struct dc_state here.
> Remove the later duplicate more secure.
>
> Signed-off-by: Wan Jiabing
> ---
> Changelog:
> v2:
> - Remove the later duplicate instead of the former.
>
Applied to amd-staging-drm-next.
Thanks
On 04/29, Rodrigo Siqueira wrote:
> Reviewed-by: Rodrigo Siqueira
>
> On 04/29, Wan Jiabing wrote:
> > There are two declarations of struct dc_state here.
> > Remove the later duplicate more secure.
> >
>
Is your robot public available?
btw, applied to amd-staging-drm-next.
Thanks
On 04/29, Jiabing Wan wrote:
>
> >Nice catch!
> >
> >Are you using any tool to identify this problem?
>
> Yes, I have a robot including many detecting scripts :)
>
> >Reviewed-b
C4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=tS6NA4FPNYFPCbIdngKshN3I%2BwRwAumgC0vdA50h9l8%3D&reserved=0
--
Rodrigo Siqueira
https://siqueira.tech
signature.asc
Description: PGP signature
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Lgtm
Reviewed-by: Rodrigo Siqueira
On 04/30, Felix Kuehling wrote:
> This function is only used in this source file.
>
> Reported-by: kernel test robot
> Signed-off-by: Felix Kuehling
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 +-
> 1 file changed, 1 ins
iqueira%40amd.com%7Ccd057517621142c86d6d08d9100fd033%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637558482375385783%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=j2z4VJ8ZGKim3R5BxIOLNRwjj%2B6yanIKNd5JQp738P8%3D&reserved=0
--
Rodrigo Siqueira
https://siqueira.tech
signature.asc
Description: PGP signature
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
, kms_plane_alpha_blend,
and kms_plane_scaling will pass.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display
the functions; it only changes some static
functions to global and adds some minor adjustments related to the copy
from one place to another.
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/amdgpu_dm/Makefile|9 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1479
LGTM,
Jay, any comment?
Reviewed-by: Rodrigo Siqueira
On 05/08, Rouven Czerwinski wrote:
> This function is not used anywhere, remove it. It was added in
> 40dd6bd376a4 ("drm/amd/display: Linux Set/Read link rate and lane count
> through debugfs") and moved in fe798de53a7
lgtm,
Reviewed-by: Rodrigo Siqueira
On 05/10, Andrey Grodzovsky wrote:
> It's already being released by DRM core through devm
>
> Signed-off-by: Andrey Grodzovsky
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 -
> 1 file changed, 1 deletion(-)
>
Thanks,
Reviewed-by: Rodrigo Siqueira
On 05/07, Alex Deucher wrote:
> The DCN3 guards were dropped a while ago, this one must have
> snuck in in a merge or something.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 --
&g
PU memory")
Do we need to add the Fixes tag for this patch?
Reviewed-by: Rodrigo Siqueira
> > Signed-off-by: Alex Deucher
> > ---
> > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 4
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/
tps://drive.google.com/file/d/1QklH_H2AlOTu8W1D3yl6_3rtZ7IqbjR_/view?usp=sharing
Hmmm... I don't think that the two cursor patch would cause that
flickering. Are you using the latest amd-staging-drm-next? Do you have
this patch in your local branch:
drm/amd/display: Reject non-zero
: Nicholas Choi
Cc: Bhawanpreet Lakha
Cc: Nicholas Kazlauskas
Cc: Mark Yacoub
Cc: Daniel Wheeler
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- Fixes and improvements in the LTTPR code
- Improve z-state
- Fix null pointer check
- Improve communication with s0i2
- Update multiple-display split policy
- Add missing registers
Cc: Daniel Wheeler
Thanks
Siqu
: Rodrigo Siqueira
Signed-off-by: George Shen
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 8a35370da867..6f552f7ee1db
ndard link training function.
Reviewed-by: Wenjing Liu
Acked-by: Rodrigo Siqueira
Signed-off-by: George Shen
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 338 +-
1 file changed, 337 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
: Dmytro Laktyushkin
Reviewed-by: Jun Lei
Acked-by: Rodrigo Siqueira
Signed-off-by: Charlene Liu
---
.../drm/amd/display/dc/dcn31/dcn31_resource.c | 25 +--
.../drm/amd/display/dc/dcn31/dcn31_resource.h | 31 +++
2 files changed, 54 insertions(+), 2 deletions(-)
diff
not ready.
Fixes: 118a33151658 ("drm/amd/display: Add DCN3.1 clock manager support")
Reviewed-by: Eric Yang
Acked-by: Rodrigo Siqueira
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a
From: Alvin Lee
[Why]
Bug fix for null function ptr (should check for NULL instead of not
NULL)
[How]
Fix if condition
Reviewed-by: Samson Tam
Acked-by: Rodrigo Siqueira
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 4 ++--
1 file changed, 2 insertions
til we can add a new interface to SMU to
signal when we can support z10 but not z9.
We can revert this once the interface change is in.
Reviewed-by: Eric Yang
Acked-by: Rodrigo Siqueira
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 3 +--
1 file
n period.
[How]
Hook up the handler like DCN21. It was also missed like the
exit_optimized_pwr_state callback.
Fixes: 64b1d0e8d500 ("drm/amd/display: Add DCN3.1 HWSEQ")
Reviewed-by: Eric Yang
Acked-by: Rodrigo Siqueira
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/
s for repeaters when
in LTTPR non-transparent mode.
Reviewed-by: Wesley Chalmers
Acked-by: Rodrigo Siqueira
Signed-off-by: George Shen
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp
From: Martin Leung
Undo ODM Combine regression causing causing pipe allocation issues.
Reviewed-by: Aric Cyr
Acked-by: Rodrigo Siqueira
Signed-off-by: Martin Leung
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 81 +--
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 11
From: "Lai, Derek"
[Why]
The change of setting a timer callback on boot for 10 seconds is still
working, just lacked power down for DCN10.
[How]
Added power down for DCN10.
Reviewed-by: Anthony Koo
Acked-by: Rodrigo Siqueira
Signed-off-by: Derek Lai
---
drivers/gpu/drm/amd/displa
From: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Rodrigo Siqueira
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd
From: Wesley Chalmers
[WHY]
These registers are currently missing from the DCN303 header files
Reviewed-by: George Shen
Acked-by: Rodrigo Siqueira
Signed-off-by: Wesley Chalmers
---
.../drm/amd/display/dc/dcn303/dcn303_dccg.h | 20 +--
1 file changed, 18 insertions(+), 2
objects out
of dc link. So instead of access a link resource from dc link. Current
link's resource can be accessible through pipe_ctx->link_res during
commit, or by calling dc_link_get_cur_link_res function with current
link passed in after commit.
Reviewed-by: Jun Lei
Acked-by: Rodrigo
From: Aric Cyr
This version brings along the following:
- Fixes and improvements in the LTTPR code
- Improve z-state
- Fix null pointer check
- Improve communication with s0i2
- Update multiple-display split policy
- Add missing registers
Acked-by: Rodrigo Siqueira
Signed-off-by: Aric Cyr
Acked-by: Rodrigo Siqueira
Signed-off-by: Angus Wang
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn30
From: Wenjing Liu
[why]
This commit is to populate link res in preparation of the next commit.
The next commit will replace all existing code to use link res instead
Reviewed-by: Jun Lei
Acked-by: Rodrigo Siqueira
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c
From: Wenjing Liu
[why]
Update all accesses to use hpo dp link encoder through link resource
only.
Reviewed-by: Jun Lei
Acked-by: Rodrigo Siqueira
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 22 +++---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c
From: Wenjing Liu
[why]
When there are more DP2.0 RXs connected than the number HPO DP link
encoders we have, we need to dynamically allocate HPO DP link encoder to
the port that needs it.
[how]
Only allocate HPO DP link encoder when it is needed.
Reviewed-by: Jun Lei
Acked-by: Rodrigo
: Rodrigo Siqueira
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 103 ++
drivers/gpu/drm/amd/display/dc/dc_link.h | 4 +
.../gpu/drm/amd/display/dc/inc/core_types.h | 5 +
3 files changed, 112 insertions(+)
diff --git a/drivers/gpu/drm/amd
ver, not the current chip.
[How]
Some ASICs would be fused display pipes less than the default setting.
In dcnxx_resource_construct function, driver would obatin real timing
generator count and store it into res_pool->timing_generator_count.
Reviewed-by: Anthony Koo
Acked-by: Rodrigo Siqueira
Si
Hi,
This is the last DC upstream of this year. As a result, it is a very
tiny one with a few bug fixes.
Just for curiosity, I decided to calculate how many patches we upstream
via this weekly process in 2021, and it was approximately 740 patches
where Daniel Wheeler tested each patchset. Thanks t
From: Charlene Liu
[why]
driver missed the check.
[how]
add the check.
add min display clock = 100mhz check based on dccg doc.
[note]
add SetPhyclkVoltageByFreq as confirmed with smu, but not enabled in
this change.
Reviewed-by: Dmytro Laktyushkin
Acked-by: Rodrigo Siqueira
Signed-off-by
ot be running and we will do a full hardware init.
In S3 DMCUB will be running but will not be DAL fw so we will also do
a full hardware init.
Reviewed-by: Mikita Lipski
Acked-by: Rodrigo Siqueira
Signed-off-by: Nicholas Kazlauskas
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
move the mapping to DMUB.
2. populate dio_output_idx/phy_idx for all configuration, define
usb4_enabled bit instead of dio_output_type as an external enum.
Reviewed-by: Eric Yang
Acked-by: Rodrigo Siqueira
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 145
From: Mikita Lipski
[why]
We want to know if new crtc state is enabling MPO configuration before
enabling it.
[how]
Detect if both primary and overlay planes are enabled on the same CRTC.
Reviewed-by: Bhawanpreet Lakha
Acked-by: Rodrigo Siqueira
Signed-off-by: Mikita Lipski
---
drivers/gpu
e the
legacy path otherwise.
Fixes: b60a041393f7 ("drm/amd/display: Query DMCUB for dp alt status")
Reviewed-by: Hansen Dsouza
Acked-by: Rodrigo Siqueira
Signed-off-by: Nicholas Kazlauskas
---
.../display/dc/dcn31/dcn31_dio_link_encoder.c | 114 +++---
1 file changed, 94 in
warning issues in amdgpu.
I tested this series with DCN, DCN disabled, and with `allmodconfig`; I
did not have any compilation issue.
Thanks
Siqueira
Rodrigo Siqueira (4):
drm/amdgpu: Treat warning as an error
drm/amdgpu: Fix compilation warning due to double semicolon
drm/amdgpu: Drop
This commit fix the following GCC warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:945:6: error:
unused variable ‘i’ [-Werror=unused-variable]
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd
We have one internal CI that builds our kernel with the -Werror flag; as
a result, when we try to sync our branch with amd-staging-drm-next we
get some failures due to warnings. This commit tries to alleviate this
problem by forcing a warning to be treated as an error.
Signed-off-by: Rodrigo
warning.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index aa8d614009d4..d47a510a7f5d 100644
--- a/drivers
: Rodrigo Siqueira
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
index f604a2235a9c..62f1f97ef7f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+++ b/drivers
by: Leo Li
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 87299e62fe12..5482b0925396 100644
---
This DC patchset brings improvements in multiple areas. In summary, we
have:
- Z9 improvements
- Clocks management adjustments
- Code cleanup
- Improve DSC and MST code
Thanks
Siqueira
Alvin Lee (1):
drm/amd/display: Driver support for MCLK query tool
Anthony Koo (1):
drm/amd/display: [F
From: Josip Pavic
[Why & How]
Increase width of some variables to avoid comparing integers of
different widths
Reviewed-by: Anthony Koo
Acked-by: Rodrigo Siqueira
Signed-off-by: Josip Pavic
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
1 file changed, 2 insertions(+
o make the matching logic can go to next to
get a valid one.
Reviewed-by: Aric Cyr
Acked-by: Rodrigo Siqueira
Signed-off-by: Martin Tsai
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 11 +---
.../gpu/drm/amd/display/dc/core/dc_link_
From: Alvin Lee
Implement handling for escape call to query the MCLK switch support for
the current display config.
Reviewed-by: Jun Lei
Acked-by: Rodrigo Siqueira
Signed-off-by: Alvin Lee
---
.../drm/amd/display/dc/dml/display_mode_vba.c | 24 +++
.../drm/amd/display/dc/dml
: Rodrigo Siqueira
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 87ed48d5530d..8bd265b40847 100644
--- a
From: Ian Chen
Prepare for future dm can have different implementation depends on the
return value.
Reviewed-by: Wenjing Liu
Acked-by: Rodrigo Siqueira
Signed-off-by: Ian Chen
---
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 24 ---
drivers/gpu/drm/amd/display/dc/core
enjing Liu
Acked-by: Rodrigo Siqueira
Signed-off-by: George Shen
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 5 ++
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 59 +++
drivers/gpu/drm/amd/display/dc/dc.h | 2 +
drivers/gpu/drm/amd/display/dc/dc_dp_typ
unsupported PSR
version number.
[How]
Fix the hang by using link->psr_settings.psr_version directly during
amdgpu_dm_link_setup_psr.
Reviewed-by: Anthony Koo
Acked-by: Rodrigo Siqueira
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 6 ++
1 f
From: Varone
[WHY?]
SKUs that contain an unused eDP connector will throw an error when no
display is connected.
[HOW?]
Change error to a warning.
Reviewed-by: Martin Leung
Acked-by: Rodrigo Siqueira
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/dce110
From: Fangzhi Zuo
Sequence to reset synaptics SDP fifo before enabling first stream
Reviewed-by: Hersen Wu
Acked-by: Rodrigo Siqueira
Signed-off-by: Fangzhi Zuo
---
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 133 ++
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 2
From: Fangzhi Zuo
Determine if DFP present and the type of downstream device
based on dsc_aux
Reviewed-by: Hersen Wu
Acked-by: Rodrigo Siqueira
Signed-off-by: Fangzhi Zuo
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 23
From: Roy Chan
[Why]
indirect register index/data pair may be used by multi-threads. when it
happens, it would cause register access issue that is hard to trace.
[How]
Using cgs service, which provide a sync indirect reg access api.
Reviewed-by: Aric Cyr
Acked-by: Rodrigo Siqueira
Signed
From: Fangzhi Zuo
DSC sequence for non virtual dpcd synaptics hub
Reviewed-by: Hersen Wu
Acked-by: Rodrigo Siqueira
Signed-off-by: Fangzhi Zuo
---
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 48 +++
.../amd/display/include/ddc_service_types.h | 3 ++
2 files changed
From: Anthony Koo
- Add Scr8 for GPINT messaging between driver and fw
Acked-by: Rodrigo Siqueira
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc
From: Oliver Logush
[why]
Need to add Cyan Skillfish support by adding the correct Device ID
Reviewed-by: Charlene Liu
Acked-by: Rodrigo Siqueira
Signed-off-by: Oliver Logush
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 3 ++-
drivers/gpu/drm/amd/display/include/dal_asic_id.h | 2
From: Wayne Lin
[Why & How]
In order to easily test ilr by immediately reset the preferred training
settings,
fix the code to disable skip_immediate_retrain.
Reviewed-by: Solomon Chiu
Acked-by: Rodrigo Siqueira
Signed-off-by: Wayne Lin
---
drivers/gpu/drm/amd/display/amdgp
Acked-by: Rodrigo Siqueira
Signed-off-by: Reza Amini
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
.../amd/display/modules/inc/mod_info_packet.h | 3 ++-
.../display/modules/info_packet/info_packet.c | 25 ++-
3 files changed, 16 insertions(+), 14 deletions(-)
diff
From: Sung Joon Kim
[why]
Due to bad hardware, the PHY repeater count in LTTPR cap is read as 0xFF
in some monitors while the LTTPR is actually present.
[how]
Remove PHY repeater counter check when configuring LTTPR mode.
Reviewed-by: Jun Lei
Acked-by: Rodrigo Siqueira
Signed-off-by: Sung
stream
attached to it.
[how]
revert back to previous code in set drive setting function then add an
empty link_resource structure, then assign link resource based on
current link resource if link resource is allocated to the current pipe.
Reviewed-by: Wayne Lin
Acked-by: Rodrigo Siqueira
Signed
From: Aric Cyr
This version brings along the following fixes:
- Z9 improvements
- Clocks management adjustments
- Code cleanup
- Improve DSC and MST code
Acked-by: Rodrigo Siqueira
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1
From: David Galiffi
[How & Why]
Disable physym clock when it's not in use.
Reviewed-by: Eric Yang
Acked-by: Rodrigo Siqueira
Signed-off-by: David Galiffi
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 8 ++-
.../gpu/drm/amd/display/dc/dcn31/dcn31_dc
From: Eric Yang
[Why]
To help triage issues and coordinate driver/bios release dependency
[How]
Only enable the new Z9 interface when debug option is set, otherwise
treat Z10 only support case as Zstate disallowed.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Rodrigo Siqueira
Signed-off-by
the supported PSR version and the PSR disable status instead.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Rodrigo Siqueira
Signed-off-by: Eric Yang
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd
From: Aric Cyr
Acked-by: Rodrigo Siqueira
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 5 -
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h | 3 ---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 2 +-
3 files changed, 1 insertion(+), 9
From: David Galiffi
[How & Why]
Updated procedure to match hardware programming guide.
Reviewed-by: Eric Yang
Acked-by: Rodrigo Siqueira
Signed-off-by: David Galiffi
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 7 +++
.../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
On 05/14, Mark Yacoub wrote:
> On Fri, May 14, 2021 at 12:31 PM Mark Yacoub wrote:
> >
> > On Fri, May 14, 2021 at 11:28 AM Harry Wentland
> > wrote:
> > >
> > > On 2021-05-14 7:47 a.m., Rodrigo Siqueira wrote:
> > > > A few weeks ago,
nclude "dcn10/dcn10_hw_sequencer.h"
>
> #define GAMMA_HW_POINTS_NUM 256
> --
> 2.20.1
>
lgtm,
Thanks
Reviewed-by: Rodrigo Siqueira
--
Rodrigo Siqueira
https://siqueira.tech
signature.asc
Description: PGP signature
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
t[k] != dm_444_16
> && v->SourcePixelFormat[k] != dm_444_8
> && v->SourcePixelFormat[k] != dm_rgbe) {
> if (v->ViewportWidthChroma[k] >
> v->SurfaceWidthC[k]
> --
> 2.20.1
>
+ A
modes")
commit d03ee581eee6 ("drm/amd/display: Add module parameter for freesync video
mode")
Nevertheless, we did not document it in detail in our driver. This
commit introduces a kernel-doc and expands the module parameter
description.
Cc: Aurabindo Pillai
Cc: Sean Paul
Cc: Harry We
- .pstate_enabled = true,
> .enable_mem_low_power = {
> .bits = {
> .vga = false,
> --
> 2.20.1
>
Reviewed-by: Rodrigo Siqueira
Thanks
--
Rodrigo Siqueira
https://siqueira.tech
signature.asc
Description: PGP signature
ChromeOS. For this reason, we decided to revert this
patch.
Cc: Nicholas Kazlauskas
Cc: Harry Wentland
Cc: Hersen Wu
Cc: Sean Paul
Cc: Mark Yacoub
Cc: Greg Kroah-Hartman
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 ++--
1 file changed, 2
unding_box_st dcn3_03_soc = {
>
> .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */
> .num_states = 1,
> - .sr_exit_time_us = 15.5,
> - .sr_enter_plus_exit_time_us = 20,
> + .sr_exit_time_us =
rride decision to its own function to maintain the
integrity of our specs compliant default behavior.
Signed-off-by: Wenjing Liu
Reviewed-by: George Shen
Acked-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 113 --
.../gpu/drm/amd/display/dc/inc/dc_link
From: Dmytro Laktyushkin
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Wenjing Liu
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd
: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 45640f1c26c4..b62d21131af2 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm
From: Stylon Wang
[Why]
Changes in DM needed to support Freesync HDMI on DMUB.
[How]
Change implementation to parse CEA blocks in case of DMUB-enabled ASICs.
Signed-off-by: Stylon Wang
Reviewed-by: Nicholas Kazlauskas
Acked-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/amdgpu_dm
From: Wesley Chalmers
This reverts commit 06a2bd7ae7238cf31faeb2216c0e8a3d9b1bedfb
Some displays are not lighting up when put in LTTPR Transparent Mode
Signed-off-by: Wesley Chalmers
Reviewed-by: Jun Lei
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 7
: Dmytro Laktyushkin
Acked-by: Rodrigo Siqueira
---
.../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c| 12 -
.../dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c | 4 +--
.../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 12 -
.../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 16
From: Anthony Koo
- Updated SCR definition for FW boot options for Separate DCN init
for DMUB FW loaded in VBL
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 11 +++
1 file changed, 7 insertions
From: Alvin Lee
Type adjustments and formatting fixes.
Signed-off-by: Alvin Lee
Reviewed-by: Dmytro Laktyushkin
Acked-by: Rodrigo Siqueira
---
.../display/dc/dml/dcn21/display_mode_vba_21.c | 11 ++-
.../display/dc/dml/dcn30/display_mode_vba_30.c | 18 ++
.../display
From: Wang
Added NULL checks before two problematic statements
Signed-off-by: Wang
Reviewed-by: Martin Leung
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc_stat.c | 24 +++
drivers/gpu/drm/amd/display/dc/dc_stat.h | 1 +
drivers/gpu/drm/amd/display/dc/irq_types.h| 2 +-
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 18 ++
.../gpu/drm/amd/display
From: Aric Cyr
[Why]
EDID CTS requires at least 2k (16 blocks) to be readable.
[How]
Increase EDID buffer size to 2k
Signed-off-by: Aric Cyr
Reviewed-by: Anthony Koo
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion
ff-by: Nicholas Kazlauskas
Reviewed-by: Eric Yang
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hw
301 - 400 of 1685 matches
Mail list logo
