[PATCH 4/6] drm/amd/display: Add check for forced_clocks debug option

[Rodrigo Siqueira]

From: Charlene Liu <charlene....@amd.com>

[why]
driver missed the check.

[how]
add the check.
add min display clock = 100mhz check based on dccg doc.

[note]
add SetPhyclkVoltageByFreq as confirmed with smu, but not enabled in
this change.

Reviewed-by: Dmytro Laktyushkin <dmytro.laktyush...@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.sique...@amd.com>
Signed-off-by: Charlene Liu <charlene....@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index 7c64317a56f7..40778c05f9b3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -1978,7 +1978,7 @@ static void dcn31_calculate_wm_and_dlg_fp(
                pipes[pipe_idx].clks_cfg.dispclk_mhz = 
get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
                pipes[pipe_idx].clks_cfg.dppclk_mhz = 
get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 
-               if (dc->config.forced_clocks) {
+               if (dc->config.forced_clocks || dc->debug.max_disp_clk) {
                        pipes[pipe_idx].clks_cfg.dispclk_mhz = 
context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
                        pipes[pipe_idx].clks_cfg.dppclk_mhz = 
context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
                }
-- 
2.25.1