On 2021-02-17 10:29 a.m., Rodrigo Siqueira wrote:
On 02/17, Aurabindo Pillai wrote:
On 2021-02-17 8:40 a.m., Rodrigo Siqueira wrote:
Hi,
Is this commit a direct revert from
be7af780ef3cbb8fe1004db48dc66caf2da595cd ?
If so, I recommend you to use the standard way to identify "r
(system_highpri_wq, &handler_data_add->work))
+ DRM_DEBUG("__func__: a work_struct is allocated and
queued, "
+ "src %d\n", irq_source);
+ else
+ DRM_ERROR("__func__: a new work_struct cannot be
queued, &qu
d03ee581eee6 drm/amd/display: Add module parameter for freesync video mode
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 12 -
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 369
Reviewed-by: Aurabindo Pillai
On 2021-03-16 11:15 a.m., Nikola Cornij wrote:
This reverts commit e9a777fc0c264542fbd6d51b8fe51739d09032c1
Sinc this is a "revert of a revert", the end effect is that freesync
video is back to its original state, the way it was before the fi
The buffer allocated is of 1024 bytes. Allocate this from
heap instead of stack.
Also remove check for stack size since we're allocating from heap
Signed-off-by: Aurabindo Pillai
Tested-by: Amber Lin
---
drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 26 +++--
1 file ch
On 05/20, Felix Kuehling wrote:
> Am 2020-05-20 um 9:53 a.m. schrieb Aurabindo Pillai:
> > The buffer allocated is of 1024 bytes. Allocate this from
> > heap instead of stack.
> >
> > Also remove check for stack size since we're allocating from heap
> &g
cided to be enabled on that
connector.
Signed-off-by: Eryk Brol
Signed-off-by: Mikita Lipski
Reviewed-by: Mikita Lipski
Acked-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
.../amd/display/amdg
From: Igor Kravchenko
[Why]
For ver.4.4 and higher VBIOS contains default setting table.
{How]
Read Golden Settings Table from VBIOS, apply Aux tuning parameters.
Signed-off-by: Igor Kravchenko
Reviewed-by: Aric Cyr
Acked-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/dc/bios
From: Eric Bernstein
Signed-off-by: Eric Bernstein
Reviewed-by: Chris Park
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm
From: Dmytro Laktyushkin
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Display Core version 3.2.97
* New firmware release
* DSC improvements
* Bug fixes across DML, pipe managment
* Regression fixes for DP
--
Alvin Lee (1):
drm/amd/display: Separate pipe disconnect from rest of p
From: Eric Bernstein
Signed-off-by: Eric Bernstein
Reviewed-by: Dmytro Laktyushkin
Acked-by: Aurabindo Pillai
---
.../amd/display/dc/virtual/virtual_stream_encoder.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/virtual
From: Harry Wentland
[Why&How]
use correct logger context
Signed-off-by: Harry Wentland
Reviewed-by: Roman Li
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm
decided to be enabled on that
connector.
Signed-off-by: Eryk Brol
Signed-off-by: Mikita Lipski
Reviewed-by: Mikita Lipski
Acked-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
.../amd/display/amdgpu_dm
]
Change the default swizzle mode from linear to 4kb_s and update pitch
accordingly.
Signed-off-by: George Shen
Reviewed-by: Dmytro Laktyushkin
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
rent synchornization state and grouping.
Example usage to force a resync (from an X based desktop):
echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
xset dpms force off && xset dpms force on
Signed-off-by: Victor Lu
Reviewed-by: Aurabindo Jayamohanan Pillai
Acked-by: Aurabi
From: Eryk Brol
[why]
Some of the DSC debugfs read enteries are missing comments
explaining how to use and how to comprehend the results.
Signed-off-by: Eryk Brol
Signed-off-by: Mikita Lipski
Reviewed-by: Mikita Lipski
Acked-by: Aurabindo Pillai
---
.../amd/display/amdgpu_dm
sum of
base dce_info offset and golden table offset
Signed-off-by: Igor Kravchenko
Reviewed-by: Aric Cyr
Acked-by: Aurabindo Pillai
---
.../drm/amd/display/dc/bios/bios_parser2.c| 4 +-
.../display/dc/dcn30/dcn30_dio_link_encoder.c | 53 ++-
.../display/dc/dcn30
From: Anthony Koo
| [Header Changes]
| - Reworked the FW versioning to include hotfix
| and test bits
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 15 ---
1 file changed, 12
ent this.
[How]
Move MPCC disconnect into separate operation than the
rest of the pipe programming.
Signed-off-by: Alvin Lee
Reviewed-by: Jun Lei
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 10 ++
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c
From: "JinZe.Xu"
[How]
Use dc_is_hdmi_signal to determine signal type.
Signed-off-by: JinZe.Xu
Reviewed-by: Charlene Liu
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/g
From: Aric Cyr
[Why]
Sink OUI supported cap is not set so driver skips programming it.
[How]
Revert the change the skips OUI programming if the cap is not set
Signed-off-by: Aric Cyr
Reviewed-by: Anthony Koo
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index ae0e27c67ef9
From: Eryk Brol
This reverts commit 39edb76689b8c9e41b1b9e2557da4897a405221b.
Reason for revert: Patch introduces performance issues and might
cause memory consistency problems with multiple connectors.
Signed-off-by: Eryk Brol
Acked-by: Aurabindo Pillai
---
.../gpu/drm/amd/display
From: Dmytro Laktyushkin
[Why&How]
Create a separate dcn21_fast_validate_bw function for dcn21.
Signed-off-by: Dmytro Laktyushkin
Acked-by: Aurabindo Pillai
---
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
.../drm/amd/display/dc/dcn20/dcn20_resource.h | 3 +
.../drm/amd/dis
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* DC version 3.2.108
* Firmware release 0.0.38
* Tracing additions
* Improvements & fixes across ODM, DSC, watermarks and others.
--
Alvin Lee (2):
drm/amd/display: Set WM set A to 0 if full pstate not supporte
From: Nikola Cornij
[Why] Can be used for debug purposes
[How] Add max target bpp override field and related handling
Signed-off-by: Nikola Cornij
Acked-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4
events
Signed-off-by: Anthony Koo
Acked-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 27 ---
1 file changed, 24 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
From: Ashley Thomas
[Why]
Some sink devices wish to have access to the minimum
HBlank supported by the ASIC.
[How]
Make the ASIC minimum HBlank available in Source
Device information address 0x340.
Signed-off-by: Ashley Thomas
Acked-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/dc/core
From: Martin Leung
why:
missing OEM data to control graphics card functions
how:
load it into init_data. copied over from dcn2 implementation.
copied destruction sequence as well.
Signed-off-by: Martin Leung
Acked-by: Aurabindo Pillai
---
.../drm/amd/display/dc/dcn30/dcn30_resource.c
From: Aric Cyr
[Why]
When ODM combine is in use we trigger multiple update events causing
issues with variable refresh rate.
[How]
Only trigger on a single ODM instance.
Signed-off-by: Aric Cyr
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 5 ++---
1 file changed
From: Anthony Koo
| [Header Changes]
|- Add GPINT to change timestamping mode for traces
Signed-off-by: Anthony Koo
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd
From: Martin Leung
why:
oem-related ddc read/write fails without these regs
how:
copy from hw_factory_dcn20.c
Signed-off-by: Martin Leung
Acked-by: Aurabindo Pillai
---
.../drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c | 12
1 file changed, 12 insertions(+)
diff --git a
From: Reza Amini
[why]
So we can track VSC SDP errors from display
[how]
Define the bit, and use it in driver logic
Signed-off-by: Reza Amini
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
From: Isabel Zhang
[Why]
Causes underflow regression
[How]
This reverts commit f61b3a065f129a90ca83bb214a507b29b9c15ba7
Signed-off-by: Isabel Zhang
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 11 +-
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 156
From: Yongqiang Sun
[Why]
right side visual confirm is too thick due to it is 4 times of
left side (16 lines).
[How]
Change factor from 4 to 2.
Signed-off-by: Yongqiang Sun
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 2 +-
1 file changed, 1
errors when
we try to reuse some of the existing structures. This commit decouples
part of the amdgpu_dm_trace from DC core to simplify the trace
enlargement in future changes.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 39
From: Aric Cyr
Signed-off-by: Aric Cyr
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index daa2589464fe..7622cd222d66 100644
From: Alvin Lee
[Why]
We should leave GSL if we're not doing immediate flip no matter if
we're doing pipe split or not
[How]
Check for updating GSL state whenever we're not doing
immediate flip
Signed-off-by: Aric Cyr
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/displ
From: Yu-Ting Shen
[WHY]
VBIOS will not enable VSC_SDP during pre-OS to lead
MISC1[6] wasn't matched with driver.
[HOW]
disabled seamless boot if sink supports VSC_SDP
Signed-off-by: Yu-Ting Shen
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4
1
is high. Watermarks
vlevel calculation logic was also udpated to assume
state 1 contains the new optimized state.
Signed-off-by: Sung Lee
Acked-by: Aurabindo Pillai
---
.../drm/amd/display/dc/dcn21/dcn21_resource.c | 71 ++-
1 file changed, 53 insertions(+), 18 deletions(-)
diff
From: Aric Cyr
Signed-off-by: Aric Cyr
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 3f888570ffad..daa2589464fe 100644
From: Taimur Hassan
[Why]
Underflow counter increases in AGM when performing some mode switches due
to timing sync, which is a known hardware issue.
[How]
Temporarily raise DPG height during timing sync so that underflow is not
reported.
Signed-off-by: Taimur Hassan
Acked-by: Aurabindo Pillai
: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 4 ++--
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
From: Brandon Syu
[Why]
For some monitors,
they can't display under BIOS with avmute enabled.
[How]
Add monitor patch for skip avmute action.
Signed-off-by: Brandon Syu
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 5 +++--
drivers/gpu/drm/amd/displ
From: jinlong zhang
[why]
Some platform has a limitation of 2ms for udelay
[how]
Add 1ms udelay for specific dongle.
Signed-off-by: jinlong zhang
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 7 +++
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
From: Sung Lee
[WHY & HOW]
Currently disable 48mhz debug option only disables on boot.
Need to put option check in update_clocks as well to make it
affect more areas.
Signed-off-by: Sung Lee
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 2 +
From: Rodrigo Siqueira
amdgpu_dc_rreg and amdgpu_dc_wreg are very similar, for this reason,
this commits abstract these two events by using DECLARE_EVENT_CLASS and
create an instance of it for each one of these events.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
---
.../amd
From: Dmytro Laktyushkin
Prevent null pointer access when checking odm tree.
Signed-off-by: Dmytro Laktyushkin
Acked-by: Aurabindo Pillai
Cc:
---
.../gpu/drm/amd/display/dc/dcn30/dcn30_resource.c| 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu
f 1.0.
Signed-off-by: Felipe Clark
Acked-by: Aurabindo Pillai
---
.../amd/display/modules/color/color_gamma.c | 110 ++
1 file changed, 89 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
b/drivers/gpu/drm/amd/display/modules/
From: Alvin Lee
[Why]
If full pstate is not supported, we should set WM set A
to 0 to prevent any hangs
[How]
If pstate is not supported, set watermark set A to 0
Signed-off-by: Alvin Lee
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 2 +-
1 file
, however, it
can be added to other DCN architecture.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
---
.../amd/display/amdgpu_dm/amdgpu_dm_trace.h | 108 ++
drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +
drivers/gpu/drm/amd/display/dc/dc_trace.h | 33
From: Rodrigo Siqueira
The clock state update is the source of many problems, and capturing
this sort of information helps debug. This commit introduces tracepoints
for capturing clock values and also add traces in DCE, DCN1, DCN2x, and
DCN3.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo
From: Rodrigo Siqueira
Debug amdgpu_dm could be a complicated task, therefore, this commit adds
tracepoints in some convenient functions such as plane and connector
check inside amdgpu_dm.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/amdgpu_dm
From: Dmytro Laktyushkin
[WHY & HOW]
Enable ODM Combine + Fullscreen MPO on DCN2.1
For lower power consumption in video use cases.
Signed-off-by: Dmytro Laktyushkin
Signed-off-by: Sung Lee
Acked-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 8 ++
.../drm
From: George Shen
Signed-off-by: George Shen
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/core/dc_sink.c | 1 -
drivers/gpu/drm/amd/display/dc/dc.h | 3 +--
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c
From: Derek Lai
[Why]
For user regamma we're missing this function call
to combine user regamma + OS for GAMMA_CS_TFM_1D type.
[How]
Applied 1D LUT in the mod_color_build_user_regamma.
And Set the regamma dirty as updateGamma.
Signed-off-by: Derek Lai
Acked-by: Aurabindo Pillai
---
..
From: David Galiffi
[why]
get_pixel_clk_frequency_100hz is undefined in clock_source_funcs.
[how]
set function pointer: ".get_pixel_clk_frequency_100hz =
get_pixel_clk_frequency_100hz"
Signed-off-by: David Galiffi
---
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 3 ++-
1 file chan
> [AMD Official Use Only - Internal Distribution Only]
>
>
>
>
>
>
>
> Reviewed-by: Bhawanpreet Lakha
Thanks for the review.
>
>
>
>
> From: Aurabindo Pillai
>
> Sent: October 23, 2020 1:09 PM
>
> To: amd-gfx@lists.freedes
Reviewed-by: Aurabindo Pillai
On 2020-11-18 2:19 p.m., Bhawanpreet Lakha wrote:
> dpcs reg are missing for dcn302 link encoder regs list, so add them.
> Just like dcn3
>
> Signed-off-by: Bhawanpreet Lakha
> ---
> drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 1 +
[Why&How]
Recent changes to upstream mst code remove the callback which
cleared the internal state for mst. Move the missing functionality
that was previously called through the destroy call back for mst connector
destroy
Signed-off-by: Aurabindo Pillai
Signed-off-by: Eryk Brol
---
...
On 2020-11-26 9:35 a.m., Kazlauskas, Nicholas wrote:
> On 2020-11-26 9:31 a.m., Aurabindo Pillai wrote:
>> [Why&How]
>> Recent changes to upstream mst code remove the callback which
>> cleared the internal state for mst. Move the missing functionality
>> that wa
[Why&How]
Set dpms off on the MST connector that was unplugged, for the side effect of
releasing some references held through deallocation of mst payload.
Signed-off-by: Aurabindo Pillai
Signed-off-by: Eryk Brol
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 63 ++
[Why&How]
Set dpms off on the MST connector that was unplugged, for the side effect of
releasing some references held through deallocation of mst payload.
Signed-off-by: Aurabindo Pillai
Signed-off-by: Eryk Brol
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
On 2020-11-26 3:11 p.m., Kazlauskas, Nicholas wrote:
> On 2020-11-26 2:50 p.m., Aurabindo Pillai wrote:
>> [Why&How]
>>
>> Set dpms off on the MST connector that was unplugged, for the side
>> effect of
>> releasing some references held through deallocatio
[Why&How]
Set dpms off on the MST connector that was unplugged, for the side effect of
releasing some references held through deallocation of mst payload.
Signed-off-by: Aurabindo Pillai
Signed-off-by: Eryk Brol
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
This DC patchset brings improvements in multiple areas. In summary, we have:
* DC 3.2.114
* DMUB firmware 0.0.44
* Power optimizations
* Bug fixes
--
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.44
Aric Cyr (1):
drm/amd/display: DC Release 3.2.114
Aurabindo Pillai (1
[Why&How]
Function definition was removed in earlier commit titled
"drm/amd/display: init soc bounding box for dcn3.01.". However
declaration did not get removed. This fixes a compile warning.
Fixes: fa7580010 ("drm/amd/display: init soc bounding box for dcn3.01.")
Signed-
From: Eric Bernstein
This reverts commit 15033eeab3f1b6177d87ae353c3d9b554b1d4b53.
It caused a regression in internal FPGA tests.
Signed-off-by: Eric Bernstein
Reviewed-by: Eric Yang
Acked-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c | 8
.../gpu
ry to shutdown
when SHAPER is not used.
Signed-off-by: Jacky Liao
Reviewed-by: Eric Yang
Acked-by: Yongqiang Sun
Acked-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c | 38 +++
.../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h | 14 ++-
2 files change
From: Brandon Syu
[Why]
While booting into OS, driver updates DPP/DISP CLKs.
But init clock value is zero which is invalid.
[How]
Get current clocks value to update init clocks.
To avoid underflow.
Signed-off-by: Brandon Syu
Reviewed-by: Tony Cheng
Acked-by: Aurabindo Pillai
---
.../drm
with short vblanks
such as on 1080p 360hz or 300hz panels.
[HOW]
Update latency from 23.84 to 11.72.
Signed-off-by: Sung Lee
Reviewed-by: Tony Cheng
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
cleared, which blocks
MST links from being re-enabled after a reinitialization.
[How]
- check for link_status->link_active instead, as it's the real intent
- clear cur_link_settings when we clear link_active
Signed-off-by: Joshua Aberback
Reviewed-by: Wenjing Liu
Acked-by: Aurabind
d-off-by: Jacky Liao
Reviewed-by: Eric Yang
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 8 +++
.../drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 24 ++-
.../gpu/drm/amd/display/dc/
From: Zhan Liu
[Why]
DPCS related info needs to be properly defined within code.
[How]
Add missing DPCS related info to code.
Signed-off-by: Zhan Liu
Reviewed-by: Nikola Cornij
Acked-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 11 +--
1 file
From: Aric Cyr
Signed-off-by: Aric Cyr
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 7400b0b449eb..54a829f95346 100644
: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e213246e3f04..f964cca5ad6e 100644
--- a/drivers/gpu/drm/amd
From: Anthony Koo
Add feature caps to allow way for driver to query what features
FW supports
Signed-off-by: Anthony Koo
Acked-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 54 ++-
1 file changed, 42 insertions(+), 12 deletions(-)
diff --git a
cted monitor's VRR range.
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 12
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 83a
to the driver
modelist, and also enables the optimization to skip modeset when using
one of these modes.
--
Aurabindo Pillai (3):
drm/amd/display: Add module parameter for freesync video mode
drm/amd/display: Add freesync video modes based on preferred modes
drm/amd/display: Skip modeset for
the base freesync mode
based off which timings have been generated for the rest of the freesync modes)
since these modes only differ from the base mode with front porch timing.
Signed-off-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 197 ++
1 file cha
same stream.
Signed-off-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 169 --
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
2 files changed, 153 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/dri
Hi Shashank,
Thanks for the review. Please see my inline responses.
On Thu, 2020-12-10 at 18:07 +0530, Shashank Sharma wrote:
> Hello Aurabindo,
>
>
> On 10/12/20 8:15 am, Aurabindo Pillai wrote:
>
> > [Why&How]
> > If experimental freesync video mode modul
On Thu, 2020-12-10 at 18:29 +0530, Shashank Sharma wrote:
> On 10/12/20 8:15 am, Aurabindo Pillai wrote:
> > [Why&How]
> > Inorder to enable freesync video mode, driver adds extra
> > modes based on preferred modes for common freesync frame rates.
> > When commi
a module parameter which is disabled by
default. Enabling this paramters adds additional modes to the driver
modelist, and also enables the optimization to skip modeset when using
one of these modes.
--
Aurabindo Pillai (3):
drm/amd/display: Add module parameter for freesync video mode
drm
cted monitor's VRR range.
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 12
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 83a
same stream.
Signed-off-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 163 --
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
2 files changed, 149 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/dri
the base freesync mode
based off which timings have been generated for the rest of the freesync modes)
since these modes only differ from the base mode with front porch timing.
Signed-off-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 167 ++
1 file cha
guarded by a module parameter which is disabled by
default. Enabling this paramters adds additional modes to the driver
modelist, and also enables the optimization to skip modeset when using
one of these modes.
--
Aurabindo Pillai (3):
drm/amd/display: Add module parameter for freesync video mode
cted monitor's VRR range.
Signed-off-by: Aurabindo Pillai
Acked-by: Christian König
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 12
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu
the base freesync mode
based off which timings have been generated for the rest of the freesync modes)
since these modes only differ from the base mode with front porch timing.
Signed-off-by: Aurabindo Pillai
Acked-by: Christian König
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_d
same stream.
Signed-off-by: Aurabindo Pillai
Acked-by: Christian König
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 210 +++---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
2 files changed, 179 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/dis
On Tue, 2020-12-15 at 08:32 +0530, Shashank Sharma wrote:
>
> On 15/12/20 3:50 am, Aurabindo Pillai wrote:
> > [Why&How]
> > If experimental freesync video mode module parameter is enabled,
> > add
> > few extra display modes into the driver's mode list corr
On Thu, Dec 17, 2020 at 14:11, Alex Deucher
wrote:
On Mon, Dec 14, 2020 at 5:21 PM Aurabindo Pillai
wrote:
[Why&How]
Adds a module parameter to enable experimental freesync video mode
modeset
optimization. Enabling this mode allows the driver to skip a full
modeset when
free
On Mon, 2021-01-04 at 11:16 -0500, Kazlauskas, Nicholas wrote:
> On 2020-12-09 9:45 p.m., Aurabindo Pillai wrote:
> > [Why&How]
> > Inorder to enable freesync video mode, driver adds extra
> > modes based on preferred modes for common freesync frame rates.
> > When
On Mon, 2021-01-04 at 11:06 -0500, Kazlauskas, Nicholas wrote:
> On 2020-12-11 12:54 a.m., Shashank Sharma wrote:
> >
> > On 11/12/20 12:18 am, Aurabindo Pillai wrote:
> > > [Why&How]
> > > If experimental freesync video mode module parameter is enabled,
&g
to this
mode does not trigger blanking.
This feature is guarded by a module parameter which is disabled by
default. Enabling this paramters adds additional modes to the driver
modelist, and also enables the optimization to skip modeset when using
one of these modes.
--
Aurabindo Pillai (3):
drm
cted monitor's VRR range.
Signed-off-by: Aurabindo Pillai
Acked-by: Christian König
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 12
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu
same stream.
Signed-off-by: Aurabindo Pillai
Acked-by: Christian König
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 219 +++---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
2 files changed, 188 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/dis
the base freesync mode
based off which timings have been generated for the rest of the freesync modes)
since these modes only differ from the base mode with front porch timing.
Signed-off-by: Aurabindo Pillai
Acked-by: Christian König
Reviewed-by: Shashank Sharma
---
.../gpu/drm/amd/display/
301 - 400 of 687 matches
Mail list logo
