From: Eryk Brol <eryk.b...@amd.com>
[Why]
We need to be able to specify slice height for any connector's DSC
[How]
Overwrite computed parameters in dsc_cfg, with the value needed/
Overwrites for both SST and MST connectors, but in different places, but the
process is identical. Overwrites only if DSC is decided to be enabled on that
connector.
Signed-off-by: Eryk Brol <eryk.b...@amd.com>
Signed-off-by: Mikita Lipski <mikita.lip...@amd.com>
Reviewed-by: Mikita Lipski <mikita.lip...@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pil...@amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 93 +++++++++++++++++++
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 7 ++
4 files changed, 107 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 346a6afd16ab..29570ce77967 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4743,9 +4743,14 @@ create_stream_for_sink(struct amdgpu_dm_connector
*aconnector,
/* Overwrite the stream flag if DSC is enabled through
debugfs */
if (aconnector->dsc_settings.dsc_clock_en)
stream->timing.flags.DSC = 1;
+
if (stream->timing.flags.DSC &&
aconnector->dsc_settings.dsc_slice_width)
stream->timing.dsc_cfg.num_slices_h =
DIV_ROUND_UP(stream->timing.h_addressable,
-
aconnector->dsc_settings.dsc_slice_width);
+
aconnector->dsc_settings.dsc_slice_width);
+
+ if (stream->timing.flags.DSC &&
aconnector->dsc_settings.dsc_slice_height)
+ stream->timing.dsc_cfg.num_slices_v =
DIV_ROUND_UP(stream->timing.v_addressable,
+
aconnector->dsc_settings.dsc_slice_height);
}
#endif
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 5b6f879a108c..333813ede0c7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -345,6 +345,7 @@ struct amdgpu_display_manager {
struct dsc_preferred_settings {
bool dsc_clock_en;
uint32_t dsc_slice_width;
+ uint32_t dsc_slice_height;
};
struct amdgpu_dm_connector {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index df8b84aecc4d..971b75a52e89 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -1292,6 +1292,22 @@ static ssize_t dp_dsc_slice_width_write(struct file *f,
const char __user *buf,
return size;
}
+/* function: read DSC slice height parameter on the connector
+ *
+ * The read function: dp_dsc_slice_height_read
+ * returns dsc slice height used in the current configuration
+ * The return is an integer: 0 or other positive number
+ *
+ * Access the status with the following command:
+ *
+ * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
+ *
+ * 0 - means that DSC is disabled
+ *
+ * Any other number more than zero represents the
+ * slice height currently used by DSC in pixels
+ *
+ */
static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf,
size_t size, loff_t *pos)
{
@@ -1349,6 +1365,82 @@ static ssize_t dp_dsc_slice_height_read(struct file *f,
char __user *buf,
return result;
}
+/* function: write DSC slice height parameter
+ *
+ * The write function: dp_dsc_slice_height_write
+ * overwrites automatically generated DSC configuration
+ * of slice height.
+ *
+ * The user has to write the slice height divisible by the
+ * picture height.
+ *
+ * Also the user has to write height in hexidecimal
+ * rather than in decimal.
+ *
+ * Writing DSC settings is done with the following command:
+ * - To force overwrite slice height (example sets to 128 pixels):
+ *
+ * echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
+ *
+ * - To stop overwriting and let driver find the optimal size,
+ * set the height to zero:
+ *
+ * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
+ *
+ */
+static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user
*buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
+ struct pipe_ctx *pipe_ctx;
+ int i;
+ char *wr_buf = NULL;
+ uint32_t wr_buf_size = 42;
+ int max_param_num = 1;
+ uint8_t param_nums = 0;
+ long param[1] = {0};
+
+ if (size == 0)
+ return -EINVAL;
+
+ wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
+
+ if (!wr_buf) {
+ DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
+ return -ENOSPC;
+ }
+
+ if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
+ (long *)param, buf,
+ max_param_num,
+ ¶m_nums)) {
+ kfree(wr_buf);
+ return -EINVAL;
+ }
+
+ if (param_nums <= 0) {
+ DRM_DEBUG_DRIVER("user data not be read\n");
+ kfree(wr_buf);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < MAX_PIPES; i++) {
+ pipe_ctx =
&aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+ if (pipe_ctx && pipe_ctx->stream &&
+ pipe_ctx->stream->link == aconnector->dc_link)
+ break;
+ }
+
+ if (!pipe_ctx || !pipe_ctx->stream)
+ goto done;
+
+ aconnector->dsc_settings.dsc_slice_height = param[0];
+
+done:
+ kfree(wr_buf);
+ return size;
+}
+
static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,
size_t size, loff_t *pos)
{
@@ -1659,6 +1751,7 @@ static const struct file_operations
dp_dsc_slice_width_debugfs_fops = {
static const struct file_operations dp_dsc_slice_height_debugfs_fops = {
.owner = THIS_MODULE,
.read = dp_dsc_slice_height_read,
+ .write = dp_dsc_slice_height_write,
.llseek = default_llseek
};
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 2c10352fa514..d433949fe53a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -473,6 +473,7 @@ struct dsc_mst_fairness_params {
struct drm_dp_mst_port *port;
bool clock_overwrite;
uint32_t slice_width_overwrite;
+ uint32_t slice_height_overwrite;
};
struct dsc_mst_fairness_vars {
@@ -511,6 +512,11 @@ static void set_dsc_configs_from_fairness_vars(struct
dsc_mst_fairness_params *p
params[i].timing->dsc_cfg.num_slices_h =
DIV_ROUND_UP(
params[i].timing->h_addressable,
params[i].slice_width_overwrite);
+
+ if (params[i].slice_height_overwrite)
+ params[i].timing->dsc_cfg.num_slices_v =
DIV_ROUND_UP(
+
params[i].timing->v_addressable,
+
params[i].slice_height_overwrite);
} else {
params[i].timing->flags.DSC = 0;
}
@@ -728,6 +734,7 @@ static bool compute_mst_dsc_configs_for_link(struct
drm_atomic_state *state,
if (params[count].clock_overwrite)
debugfs_overwrite = true;
params[count].slice_width_overwrite =
aconnector->dsc_settings.dsc_slice_width;
+ params[count].slice_height_overwrite =
aconnector->dsc_settings.dsc_slice_height;
params[count].compression_possible =
stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
dc_dsc_get_policy_for_timing(params[count].timing, &dsc_policy);
if (!dc_dsc_compute_bandwidth_range(
--
2.25.1
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