This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Investigate tool reported FCLK P-state deviations
* Fix null pointer issues found in emulation
* Add DSC delay factor workaround
* Round up DST_after_scaler to nearest int
* Use forced DSC bpp
From: Dillon Varone
[WHY]
DPG must be returned to initialized state when pipe is disabled.
[HOW]
Reinit DPG on unused pipes when exiting dynamic ODM.
Reviewed-by: Alvin Lee
Acked-by: Alex Hung
Signed-off-by: Dillon Varone
---
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 23
From: Eric Bernstein
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off-by: Eric Bernstein
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm
From: Alvin Lee
[Description]
Driver doesn't support ODM + MPO
Reviewed-by: Dillon Varone
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/
From: Charlene Liu
[why]
This is to update SW DML implementation.
Reviewed-by: Dmytro Laktyushkin
Reviewed-by: Ariel Bernstein
Acked-by: Alex Hung
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c | 3 ++-
.../gpu/drm/amd/display/dc/dml/dcn314
Acked-by: Alex Hung
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
From: Taimur Hassan
[Why]
This check is not needed, and can cause CRC mismatch.
[How]
Remove check and early exit from divider update.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Taimur Hassan
---
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c | 2 +-
1 file
From: Iswara Nagulendran
[HOW&WHY]
Checking if both DSC and FEC supported from sink and
source before going with TPS3 pattern during link
training.
Reviewed-by: Anthony Koo
Acked-by: Alex Hung
Signed-off-by: Iswara Nagulendran
---
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 6 +
and then re-add in this line. After that,
we will investigate what to do next for the compliance issue.
Reviewed-by: Alvin Lee
Acked-by: Alex Hung
Signed-off-by: Martin Leung
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm
From: Leo Chen
[Why & How] There are cases when we may need to override the hardcoded
TPS4 test pattern. Added parameters and config option to be able to
allow this.
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off-by: Leo Chen
---
drivers/gpu/drm/amd/display/dc/
From: Anthony Koo
- Add flag as a status read back that indicates back to back
flips detected during psr.
Reviewed-by: Aric Cyr
Acked-by: Alex Hung
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a
ed-by: Aric Cyr
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 43 +++-
1 file changed, 20 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index d446e609
From: George Shen
[Why]
DCN32 DSC delay calculation had an unintentional integer division,
resulting in a mismatch against the DML spreadsheet.
[How]
Cast numerator to double before performing the division.
Reviewed-by: Alvin Lee
Acked-by: Alex Hung
Signed-off-by: George Shen
---
.../gpu
: Alex Hung
Signed-off-by: George Shen
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 2 +-
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32
From: George Shen
[Why]
The DST_after_scaler value that DML spreadsheet outputs is
generally the driver value round up to the nearest int.
Reviewed-by: Alvin Lee
Acked-by: Alex Hung
Signed-off-by: George Shen
---
.../gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c | 4 ++--
1 file
this DSC delay factor configurable.
Reviewed-by: Alvin Lee
Acked-by: Alex Hung
Signed-off-by: George Shen
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 4 +++-
.../gpu/drm/amd/display/dc/dml/dcn32
From: Charlene Liu
[why]
fix null point issues found in emulation
Reviewed-by: Chris Park
Acked-by: Alex Hung
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd
for these configurations.
Reviewed-by: Chaitanya Dhere
Acked-by: Jasdeep Dhillon
Acked-by: Alex Hung
Signed-off-by: Nevenko Stupar
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display
- Update DML formula
- Don't enable ODM + MPO
- Include virtual signal to set k1 and k2 values
- Reinit DPG when exiting dynamic ODM
Acked-by: Alex Hung
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/driver
This is a copy-and-paste error. Fix the comment to match the macro
definition.
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.h
b/drivers
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* HDCP SEND AKI INIT error
* fix audio format not updated after edid updated
* Reduce stack size
* FEC check in timing validation
* Add fSMC_MSG_SetDtbClk support
* Update VTEM Infopacket definition
* [FW Promotion]
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* HDCP SEND AKI INIT error
* fix audio format not updated after edid updated
* Reduce stack size
* FEC check in timing validation
* Add fSMC_MSG_SetDtbClk support
* Update VTEM Infopacket definition
* [FW Promotion]
From: Ahmad Othman
[why]
HDCP sends AKI INIT error in case of multiple display on dock
[how]
Added new checks and method to handfle display adjustment
for multiple display cases
Reviewed-by: Wenjing Liu
Acked-by: Alex Hung
Signed-off-by: Ahmad Othman
---
.../gpu/drm/amd/display/modules
From: Charlene Liu
[why]
for the case edid change only changed audio format.
driver still need to update stream.
Reviewed-by: Alvin Lee
Reviewed-by: Aric Cyr
Acked-by: Alex Hung
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 4 ++--
1 file changed, 2
: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10
From: Chiawen Huang
[Why]
disable/enable leads fec mismatch between hw/sw fec state.
[How]
check fec status to fastboot on/off.
Reviewed-by: Anthony Koo
Acked-by: Alex Hung
Signed-off-by: Chiawen Huang
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4
1 file changed, 4 insertions
From: Oliver Logush
[why]
Needed to support dcn315
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off-by: Oliver Logush
---
.../display/dc/clk_mgr/dcn315/dcn315_smu.c| 19 +++
.../display/dc/clk_mgr/dcn315/dcn315_smu.h| 4 +++-
2 files changed, 18 insertions
From: "Leo (Hanghong) Ma"
[Why & How]
The latest HDMI SPEC has updated the VTEM packet structure,
so change the VTEM Infopacket defined in the driver side to align
with the SPEC.
Reviewed-by: Chris Park
Acked-by: Alex Hung
Signed-off-by: Leo (Hanghong) Ma
---
.../gpu/drm/amd/d
From: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Alex Hung
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display
Acked-by: Alex Hung
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 4ffab7bb1098..116967b96b01 100644
--- a/drivers/gpu/drm/amd/display
values are restored.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Gabe Teeger
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 19 +++
drivers/gpu/drm/amd/display/dc/dc.h | 6 +-
drivers/gpu/drm/amd/display/dc/dc_stream.h| 2 ++
.../drm
From: Charlene Liu
[why and how]
TMDS not need destructive verify link
Reviewed-by: Aric Cyr
Acked-by: Alan Liu
Acked-by: Alex Hung
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers
()
- dcn31_update_bw_bounding_box()
adding dc_assert_fp_enabled to them and drop DC_FP_START/END inside
functions that was moved to dml folder, as required.
Signed-off-by: Melissa Wen
Reviewed-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/dcn31/Makefile | 26 --
.../drm/amd/display/dc/dcn31
From: Melissa Wen
Moves related structs and dcn315_update_bw_bounding_box from dcn315
driver code to dml/dcn31_fpu that centralizes FPU code for DCN 3.1x.
Signed-off-by: Melissa Wen
Reviewed-by: Alex Hung
---
.../gpu/drm/amd/display/dc/dcn315/Makefile| 26 --
.../amd/display/dc/dcn315
From: Melissa Wen
Moves FPU-related structs and dcn316_update_bw_bounding_box from dcn316
driver to dml/dcn31 that centralize FPU operations for DCN 3.1x
Signed-off-by: Melissa Wen
Reviewed-by: Alex Hung
---
.../gpu/drm/amd/display/dc/dcn316/Makefile| 26 --
.../amd/display/dc/dcn316
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Fix allocate_mst_payload assert on resume
* [FW Promotion] Release 0.0.110.0
* Revert FEC check in validation
* Update LTTPR UHBR link rate support struct
* Add support for USBC connector
* Add work around for AUX
From: Angus Wang
[WHY]
We want another entry in IRQ type that can be used to
help find the underflow interrupt source.
[HOW]
Added another mapping in IRQ type enum.
Reviewed-by: Jun Lei
Acked-by: Alex Hung
Signed-off-by: Angus Wang
---
drivers/gpu/drm/amd/display/dc/irq_types.h | 1 +
1
From: Oliver Logush
[why]
W/a no longer needed
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off-by: Oliver Logush
---
drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c | 3 +--
drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c | 3 +--
2 files changed, 2 insertions(+), 4
From: Jingwen Zhu
[Why]
We don't include this eDP FEC init on fastboot.
[How]
Set the fec to init value when stopping driver &get the fec register value to
check should enable FEC.
Co-authored-by: Jingwen Zhu
Reviewed-by: Wenjing Liu
Acked-by: Alex Hung
Signed-off-by: Ji
From: Krunoslav Kovac
[WHY&HOW]
It can be enabled by users, but proper way is to report max_slave_planes
in DC caps for each ASIC.
Some structures use hardcoded max_plane=2, this is also addressed here.
Reviewed-by: Nevenko Stupar
Reviewed-by: Aric Cyr
Acked-by: Alex Hung
Signed-of
and max
slices cannot fit pixel clock per slice.
Reviewed-by: Wenjing Liu
Acked-by: Alex Hung
Signed-off-by: Chris Park
---
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
b/drivers
SetPowerState to D3, power down hardware.
Reviewed-by: Eric Yang
Acked-by: Alex Hung
Signed-off-by: Paul Hsieh
---
.../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 26 ++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31
power off sequence during
Driver PnP")
Reviewed-by: Anthony Koo
Reviewed-by: Eric Yang
Acked-by: Alex Hung
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/displa
tries - dcn20_dsc_pg_control"
"REG_WAIT timeout 1us * 1000 tries - dcn20_dpp_pg_control"
"REG_WAIT timeout 1us * 1000 tries - dcn20_hubp_pg_control"
[How]
Move enable_power_gating_plane() before init_pipes() in init_hw()
Reviewed-by: Anthony Koo
Reviewed-by: Eric Yang
Acke
From: Charlene Liu
[why]
when disable optc, need to clear the underflow status as well.
Reviewed-by: Chris Park
Acked-by: Alex Hung
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c | 14 +++---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c | 5
From: Jimmy Kizito
[Why]
When waking from low-power states, a DP sink may remain unresponsive to
AUX transactions.
[How]
Try to toggle DPCD SET_POWER register repeatedly (up to a maximum
timeout value) until DP sink becomes responsive.
Reviewed-by: Mustapha Ghaddar
Acked-by: Alex Hung
Signed
From: Samson Tam
[Why]
Add support for CONNECTOR_ID_USBC
Reviewed-by: Alvin Lee
Acked-by: Alex Hung
Signed-off-by: Samson Tam
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c | 3 +++
drivers/gpu/drm/amd/display/dc/bios/command_table.c | 3 ++-
drivers/gpu/drm/amd/display
From: Michael Strauss
[WHY]
Update field order to match DP2.0 spec SCR
Reviewed-by: George Shen
Acked-by: Alex Hung
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display
From: Martin Leung
why and how:
causes failure on install on certain machines
Reviewed-by: George Shen
Acked-by: Alex Hung
Signed-off-by: Martin Leung
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
From: Anthony Koo
- Revert save/restore PANEL_PWRSEQ_REF_DIV2 and
other psr phy optimizations
Reviewed-by: Aric Cyr
Acked-by: Alex Hung
Signed-off-by: Anthony Koo
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 90 +--
1 file changed, 4 insertions(+), 86 deletions
redundant dsc power gating from init_hw
- Power down hardware if timer not trigger
- Correct Slice reset calculation
- Enable 3-plane MPO for DCN31
- Set fec register init value
- Remove SW w/a for HDCP 1.4 1A-07 failure based on ECO fix
- Create underflow interrupt IRQ type
Acked-by: Alex Hung
dc_link_allocate_mst_payload()
[How]
Use link type as indicator for mst link.
Reviewed-by: Wayne Lin
Acked-by: Alex Hung
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Copy crc_skip_count when duplicating CRTC state
* Add debug option for idle optimizations on cursor updates
* Disable MPC split for DCN32/321
* Add missing ODM 2:1 policy logic
* Update DCN32 and DCN321 SR latenci
: Josip Pavic
Reviewed-by: Jun Lei
Acked-by: Alex Hung
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
index
pport USB4 and dynamic link
remapping we'll need to add this to driver in the equivalent paths.
New optional callbacks were created in the stream encoder interface and
implementations were added for DCN314.
Reviewed-by: Michael Strauss
Acked-by: Alex Hung
Signed-off-by: Nicholas
e the same:
- immediate_disable_crtc
- configure_crc
Reviewed-by: Michael Strauss
Acked-by: Alex Hung
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h | 2 ++
drivers/gpu/drm/amd/display
From: Alvin Lee
[Description]
- For any DRR cases in SubVP, don't lock for VSYNC flips
- For DCN32/321 use FW to do DRR manual trigger programming
- Add bit in SubVP cmd to indicate if the SubVP pipe is DRR
Reviewed-by: Jun Lei
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
driver
ow an ASSERT for future developers to look into.
Reviewed-by: Michael Strauss
Acked-by: Alex Hung
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/displ
os in dc_add_plane_to_context().
Don't allow both videos to be on the same side of the
display.
Add extra check when fetching free pipe for two MPO videos.
Reviewed-by: Alvin Lee
Acked-by: Alex Hung
Signed-off-by: Samson Tam
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 136 +---
.../drm/a
From: Taimur Hassan
[Why]
Coding error in DET allocation was resulting in too few DET segments
being allocated, causing underflow.
[How]
Reset pipe count each time we begin iterating through pipes for a stream.
Reviewed-by: Alvin Lee
Acked-by: Alex Hung
Signed-off-by: Taimur Hassan
From: Rodrigo Siqueira
We already isolated the DCN302 code in the DML folder, but we forgot to
drop the FPU flags from the Makefile. This commit drops those flags.
Reviewed-by: Harry Wentland
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/dc/dcn302/Makefile
From: hersen wu
[Why]
event_property_update does not check NULL pointer
[How]
check aconnector->base.state equals NULL
Reviewed-by: Bhawanpreet Lakha
Acked-by: Alex Hung
Signed-off-by: hersen wu
---
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 34 ---
1 file changed,
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 6752ca44e6e0..f62d50901d92 100644
--- a
From: Rodrigo Siqueira
We have some FPU operations on the resource part of the DCN201. This
commit drops FPU flags and moves any required FPU code to the DML
folder.
Reviewed-by: Harry Wentland
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/dc/dcn201
From: Rodrigo Siqueira
The function responsible for calculating the MCLK switching has FPU
operations. This commit moves it to the dcn30_fpu file.
Reviewed-by: Harry Wentland
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 38
From: Rodrigo Siqueira
At this stage, we must have all the FPU code for DCN30 isolated in the
DML folder. Drop FPU flags from Makefile.
Reviewed-by: Harry Wentland
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn30/Makefile | 30
From: Rodrigo Siqueira
In the DCN30 resource, we have a small patch to the bounding box struct;
this patch uses FPU operations. This commit moves that specific part to
its function under the DML folder.
Reviewed-by: Harry Wentland
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
From: Michael Strauss
[WHY/HOW]
Need to calculate and set some pixel rate divisors on correct otg_inst
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Michael Strauss
---
.../drm/amd/display/dc/dcn314/dcn314_dccg.c | 17 +
.../drm/amd/display/dc/dcn314
From: Michael Strauss
[WHY]
DP DTO isn't used for 128b/132b encoding
[HOW]
Check current link rate to determine whether using 8b/10b or 128/132b encoding
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Michael Strauss
---
.../gpu/drm/amd/display/dc/core/dc_link
From: Michael Strauss
[WHY]
Previously was pointing to DCN3 clock constructor rather than DCN31's
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 2 +-
1 file changed, 1 insertion(
From: Michael Strauss
[WHY]
Required for correct OTG_H_TIMING_CNTL programming
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Michael Strauss
---
.../drm/amd/display/dc/dcn314/dcn314_optc.c | 34 +++
1 file changed, 34 insertions(+)
diff --git a
From: Michael Strauss
[WHY]
Currently programming incorrect hpo inst as well as selecting incorrect source
[HOW]
Use hpo inst instead of otg inst to select dpstreamclk inst
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display
From: Michael Strauss
[WHY]
Needed to program audio dto
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd
from taking place
Acked-by: Alex Hung
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index
From: Alvin Lee
[Description]
- Calculation for NumWays in MALL should be based on
number of MBlks
Reviewed-by: Jun Lei
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
.../gpu/drm/amd/display/dc/dcn32/dcn32_resource.h | 1 +
.../amd/display/dc/dcn32/dcn32_resource_helpers.c | 15
From: Chris Park
[Why]
When Static screen from MALL, the cursor needs to be
cached if cursor exceeds 64x64 size.
[How]
Program the bit that cache cursor in MALL when size
of the cursor exceeds 64x64.
Reviewed-by: Jun Lei
Acked-by: Alan Liu
Acked-by: Alex Hung
Signed-off-by: Chris Park
Liu
Acked-by: Alex Hung
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/dc
From: Rodrigo Siqueira
In order to handle FPO correctly, we need to reinstate the dram values.
This function adds the required code to handle the vblank stretch and
the dram calculation.
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/dcn30/dcn30_resource.h
From: Alvin Lee
Update worst case SR latencies according to values measured by hardware
team.
Reviewed-by: Rodrigo Siqueira
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 4 ++--
drivers/gpu/drm/amd/display/dc/dml/dcn321
From: Samson Tam
Phantom pipes must use the same configuration used in main pipes. This
commit add this check.
Reviewed-by: Rodrigo Siqueira
Acked-by: Alex Hung
Signed-off-by: Samson Tam
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 1 -
drivers/gpu/drm/amd/display/dc/dcn32
From: Alvin Lee
Due to CRB, no need to rely on MPC splitting to maximize use of DET
anymore.
Reviewed-by: Rodrigo Siqueira
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
From: Alvin Lee
For optimizations and debug purposes we added an option to exit idle
operations on cursor updates.
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 1 +
2
fore, when this state is committed, we will
needlessly wait 2 frames before outputing CRC values. Even if the CRC
engine is already warmed up.
[How]
Copy the crc_skip_count as part of dm_crtc_duplicate_state.
Acked-by: Alex Hung
Signed-off-by: Leo Li
---
drivers/gpu/drm/amd/display
channels
- Updates SubVP + SubVP DRR cases updates
- Fix OPTC function pointers for DCN314
- Add enable/disable FIFO callbacks to stream setup
- Avoid MPC infinite loop
Acked-by: Alex Hung
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Block SubVP on displays that have pixclk > 1800Mhz
* Block SubVP high refresh when VRR active fixed
* Enforce 60us prefetch for 200Mhz DCFCLK modes
* Check Vactive for VRR active for FPO + Vactive
* Add symclk wor
From: Sung Lee
[WHY]
These registers would be useful to know when debugging pstate issues.
[HOW]
Add additional registers to hw state query.
Reviewed-by: Aric Cyr
Reviewed-by: Jun Lei
Acked-by: Alex Hung
Signed-off-by: Sung Lee
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 2
Mahfooz
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +-
drivers/gpu/drm/amd/display/dc/dc_helper.c| 56 +++
drivers/gpu/drm/amd/display/dc/dm_services.h | 2 +
3 files changed, 60 insertions(+), 1 deletion
uot;)
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Leo Chen
---
.../drm/amd/display/dc/dcn314/dcn314_hwseq.c | 65 +++
.../drm/amd/display/dc/dcn314/dcn314_hwseq.h | 2 +
.../drm/amd/display/dc/dcn314/dcn314_init.c | 2 +-
3 files changed, 68 in
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 5 -
drivers/gpu/drm/amd/display/dc/dc_stream.h | 2 ++
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 7 ++-
3 files changed, 12 insertions(+), 2 deletions(-)
di
DPM1, in
theory there should not be any UCLK DPM regressions by
enforcing greater prefetch
Reviewed-by: Nevenko Stupar
Reviewed-by: Jun Lei
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
.../gpu/drm/amd/display/dc/d
-by: Alex Hung
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 46fd7b68857c
des
8K60 displays)
Reviewed-by: Jun Lei
Reviewed-by: Nevenko Stupar
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h | 1 +
drivers/gpu/drm/amd/display/dc/dml/dc
ble link output
- Show the DCN/DCE version in the log
- Add additional pstate registers to HW state query
Acked-by: Alex Hung
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
On 2022-12-14 13:48, Alex Deucher wrote:
On Wed, Dec 14, 2022 at 3:22 PM Aurabindo Pillai
wrote:
From: Alex Hung
[Why]
When running IGT kms_bw test with DP monitor, some systems crash from
msleep no matter how long or short the time is.
[How]
To replace msleep with mdelay.
Can you
On 2022-12-14 14:54, Alex Deucher wrote:
On Wed, Dec 14, 2022 at 4:50 PM Alex Hung wrote:
On 2022-12-14 13:48, Alex Deucher wrote:
On Wed, Dec 14, 2022 at 3:22 PM Aurabindo Pillai
wrote:
From: Alex Hung
[Why]
When running IGT kms_bw test with DP monitor, some systems crash from
On 2022-12-14 15:35, Alex Deucher wrote:
On Wed, Dec 14, 2022 at 5:25 PM Alex Hung wrote:
On 2022-12-14 14:54, Alex Deucher wrote:
On Wed, Dec 14, 2022 at 4:50 PM Alex Hung wrote:
On 2022-12-14 13:48, Alex Deucher wrote:
On Wed, Dec 14, 2022 at 3:22 PM Aurabindo Pillai
wrote
On 2022-12-14 16:06, Alex Deucher wrote:
On Wed, Dec 14, 2022 at 5:56 PM Alex Hung wrote:
On 2022-12-14 15:35, Alex Deucher wrote:
On Wed, Dec 14, 2022 at 5:25 PM Alex Hung wrote:
On 2022-12-14 14:54, Alex Deucher wrote:
On Wed, Dec 14, 2022 at 4:50 PM Alex Hung wrote:
On
On 2022-12-15 08:17, Harry Wentland wrote:
On 12/15/22 05:29, Michel Dänzer wrote:
On 12/15/22 09:09, Christian König wrote:
Am 15.12.22 um 00:33 schrieb Alex Hung:
On 2022-12-14 16:06, Alex Deucher wrote:
On Wed, Dec 14, 2022 at 5:56 PM Alex Hung wrote:
On 2022-12-14 15:35, Alex
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- Fix linux dp link lost handled only one time
- Reset DMUB mailbox SW state after HW reset
- Unassign does_plane_fit_in_mall function from dcn3.2
- Add Function delaration in dc_link
- Fix crash when connecting 2 d
From: Sung Joon Kim
[why]
Enable Freesync over PCon on Linux environment.
[how]
Adding Freesync over PCon support in amdgpu_dm
- Read DPCD for Freesync over PCon capabilitiy
- Add whitelist for compatible branch devices
Reviewed-by: Chao-kai Wang
Acked-by: Alex Hung
Signed-off-by: Sung Joon
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