[PATCH 12/18] drm/amd/display: Fix DCN32 DSC delay calculation

[Alex Hung]

From: George Shen <george.s...@amd.com>

[Why]
DCN32 DSC delay calculation had an unintentional integer division,
resulting in a mismatch against the DML spreadsheet.

[How]
Cast numerator to double before performing the division.

Reviewed-by: Alvin Lee <alvin.l...@amd.com>
Acked-by: Alex Hung <alex.h...@amd.com>
Signed-off-by: George Shen <george.s...@amd.com>
---
 .../gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git 
a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index ad66e241f9ae..4a3e7a5d2758 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -1746,7 +1746,7 @@ unsigned int dml32_DSCDelayRequirement(bool DSCEnabled,
                }
 
                DSCDelayRequirement_val = DSCDelayRequirement_val + (HTotal - 
HActive) *
-                               dml_ceil(DSCDelayRequirement_val / HActive, 1);
+                               dml_ceil((double)DSCDelayRequirement_val / 
HActive, 1);
 
                DSCDelayRequirement_val = DSCDelayRequirement_val * PixelClock 
/ PixelClockBackEnd;
 
-- 
2.38.1