[PATCH 6.1.y] drm/amd/display: fixed integer types and null check locations

From: Sohaib Nadeem [ Upstream commit 0484e05d048b66d01d1f3c1d2306010bb57d8738 ] [why]: issues fixed: - comparison with wider integer type in loop condition which can cause infinite loops - pointer dereference before null check Cc: Mario Limonciello Cc: Alex Deucher Cc: sta...@vger.kernel.org

[PATCH 3/3] drm/amdgpu/sdma_v4_4_2: update VM flush implementation for SDMA

This commit updates the VM flush implementation for the SDMA engine. - Added a new function `sdma_v4_4_2_get_invalidate_req` to construct the VM_INVALIDATE_ENG0_REQ register value for the specified VMID and flush type. This function ensures that all relevant page table cache levels (L1 PTEs,

[PATCH 2/3 v5] drm/amdgpu: Optimize VM invalidation engine allocation and synchronize GPU TLB flush

From: "jesse.zh...@amd.com" - Modify the VM invalidation engine allocation logic to handle SDMA page rings. SDMA page rings now share the VM invalidation engine with SDMA gfx rings instead of allocating a separate engine. This change ensures efficient resource management and avoids the is

[PATCH 1/3 v5] drm/amd/amdgpu: Increase max rings to enable SDMA page ring

From: "jesse.zh...@amd.com" Increase the maximum number of rings supported by the AMDGPU driver from 132 to 148. This change is necessary to enable support for the SDMA page ring. Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 +- 1 file changed, 1 insertion(+), 1

[PATCH] amdgpu: add env support for amdgpu.ids path

In some cases, like when building a Snap application that uses libdrm, the `amdgpu.ids` file isn't directly available at the compiling place, but inside a mounted folder. This forces each application to link/bind the file from the current place (usually at the $SNAP/gnome-platform/usr/share/libdrm/

RE: [PATCH v2 4/4] drm/amdgpu/gfx12: Implement the GFX12 KCQ pipe reset

[AMD Official Use Only - AMD Internal Distribution Only] Please review the series patch to catch up the gfx latest base and to avoid the commit merged problem. Regards, Prike > -Original Message- > From: Liang, Prike > Sent: Friday, February 21, 2025 9:01 PM > To: amd-gfx@lists.f

[PATCH] drm/amdgpu: Set PG state to gating for vcn_v_5_0_1

For vcn_v_5_0_1, set power state to gating during hw fini. Also there may be scenario where VCN engine hangs during a job execution, then it's not safe to assume that set_pg_state works fine during hw_fini to put the state to gated. After a reset, we can assume that it's in the default state, there

RE: [PATCH 2/2] drm/amdgpu: Add support for CPERs on virtualization

[AMD Official Use Only - AMD Internal Distribution Only] + @Liu, Xiang(Dean)/@Zhou1, Tao for the code review + if (amdgpu_sriov_vf(adev)) + debugfs_create_file_size(name, S_IFREG | 0444, root, ring, +

RE: [PATCH] drm/amdgpu: Free CPER entry after committing to ring

[AMD Official Use Only - AMD Internal Distribution Only] Reviewed-by: Hawking Zhang Regards, Hawking -Original Message- From: Liu, Xiang(Dean) Sent: Friday, February 28, 2025 11:12 To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking ; Zhou1, Tao ; Chai, Thomas ; Liu, Xiang(Dean) Subj

Re: [PATCH 1/2] drm/amdgpu: Use the right struct for VCN v5.0.1

On 2/26/2025 1:01 PM, Lijo Lazar wrote: > VCN IP versions >= 5.0 uses VCN5 fw shared struct. > > Signed-off-by: Lijo Lazar > --- > drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 12 ++-- > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_

[PATCH] drm/amdgpu: Free CPER entry after committing to ring

Free CPER entry when it's committed to CPER ring to avoid memory leak. Signed-off-by: Xiang Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c index 15cd0a007

RE: [PATCH 1/2] drm/amdgpu: Use the right struct for VCN v5.0.1

[AMD Official Use Only - AMD Internal Distribution Only] The series is Reviewed-by: Hawking Zhang Regards, Hawking -Original Message- From: Lazar, Lijo Sent: Wednesday, February 26, 2025 15:32 To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking ; Deucher, Alexander ; Liu, Leo ; Jiang

[PATCH] drm/amdkfd: remove unused debug gws support status variable

Remove unused declaration of gws_debug_workaround. Signed-off-by: Jonathan Kim --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 59619f794b6b..43950f3e6672 100644 --- a

Re: [PATCH 2/6] drm/amdgpu: add dce_v6_0_soft_reset() to DCE6

On Thu, Feb 27, 2025 at 2:01 PM Alex Deucher wrote: > > On Thu, Feb 27, 2025 at 1:52 PM Alexandre Demers > wrote: > > > > On Thu, Feb 27, 2025 at 9:23 AM Alex Deucher wrote: > > > > > > On Thu, Feb 27, 2025 at 12:49 AM Alexandre Demers > > > wrote: > > > > > > > > DCE6 was missing soft reset, b

Re: [PATCH 2/6] drm/amdgpu: add dce_v6_0_soft_reset() to DCE6

On Thu, Feb 27, 2025 at 2:05 PM Alex Deucher wrote: > > On Thu, Feb 27, 2025 at 2:01 PM Alex Deucher wrote: > > > > On Thu, Feb 27, 2025 at 1:52 PM Alexandre Demers > > wrote: > > > > > > On Thu, Feb 27, 2025 at 9:23 AM Alex Deucher > > > wrote: > > > > > > > > On Thu, Feb 27, 2025 at 12:49 AM

Re: [PATCH v2] drm/amdkfd: Fix instruction hazard in gfx12 trap handler

On Fri, Feb 7, 2025 at 6:57 PM Jay Cornwall wrote: > > VALU instructions with SGPR source need wait states to avoid hazard > with SALU using different SGPR. > > v2: Eliminate some hazards to reduce code explosion > > Signed-off-by: Jay Cornwall > Cc: Lancelot Six Acked-by: Alex Deucher > ---

[PATCH] drm/amdkfd: remove unused debug gws support status variable

Remove unused declaration of gws_debug_workaround. Signed-off-by: Jonathan Kim --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 59619f794b6b..43950f3e6672 100644 --- a

RE: [PATCH] amdkfd: initialize svm lists at where they are defined

[Public] Ping -Original Message- From: Zhu, Lingshan Sent: Friday, February 21, 2025 5:24 PM To: Kuehling, Felix ; Deucher, Alexander Cc: Huang, Ray ; amd-gfx@lists.freedesktop.org; Zhu, Lingshan Subject: [PATCH] amdkfd: initialize svm lists at where they are defined This commit ini

[PATCH 0/4] drm/amd/display: move from kzalloc(size * nr, ...) to kcalloc(nr, size, ...)

++- 4 files changed, 8 insertions(+), 4 deletions(-) --- base-commit: be5c7bbb3a64baf884481a1ba0c2f8fb2f93f7c3 change-id: 20250227-amd-display-a8342c55a9a0 Best regards, -- Ethan Carter Edwards

[PATCH 2/4] drm/amd/display: change kzalloc to kcalloc in dcn31_validate_bandwidth()

We are trying to get rid of all multiplications from allocation functions to prevent integer overflows. Here the multiplication is probably safe, but using kcalloc() is more appropriate and improves readability. This patch has no effect on runtime behavior. Signed-off-by: Ethan Carter Edwards ---

[PATCH 1/4] drm/amd/display: change kzalloc to kcalloc in dcn30_validate_bandwidth()

We are trying to get rid of all multiplications from allocation functions to prevent integer overflows. Here the multiplication is probably safe, but using kcalloc() is more appropriate and improves readability. This patch has no effect on runtime behavior. Signed-off-by: Ethan Carter Edwards ---

[PATCH 4/4] drm/amd/display: change kzalloc to kcalloc in dml1_validate()

We are trying to get rid of all multiplications from allocation functions to prevent integer overflows. Here the multiplication is probably safe, but using kcalloc() is more appropriate and improves readability. This patch has no effect on runtime behavior. Signed-off-by: Ethan Carter Edwards ---

[PATCH 3/4] drm/amd/display: change kzalloc to kcalloc in dcn314_validate_bandwidth()

We are trying to get rid of all multiplications from allocation functions to prevent integer overflows. Here the multiplication is probably safe, but using kcalloc() is more appropriate and improves readability. This patch has no effect on runtime behavior. Signed-off-by: Ethan Carter Edwards ---

Re: [PATCH 3/3] drm/amdgpu: fix typos in SI

Applied this series with some minor changes. Thanks! Alex On Thu, Feb 27, 2025 at 12:14 AM Alexandre Demers wrote: > > Fix typos > > Signed-off-by: Alexandre Demers > --- > drivers/gpu/drm/amd/amdgpu/si.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/g

Re: [V7 07/45] drm/colorop: Add 1D Curve subtype

On 2/25/25 03:13, Louis Chauvet wrote: Le 20/12/2024 à 05:33, Alex Hung a écrit : From: Harry Wentland Add a new drm_colorop with DRM_COLOROP_1D_CURVE with two subtypes: DRM_COLOROP_1D_CURVE_SRGB_EOTF and DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF. Signed-off-by: Harry Wentland Co-developed-by:

Re: [PATCH 2/6] drm/amdgpu: add dce_v6_0_soft_reset() to DCE6

On Thu, Feb 27, 2025 at 1:52 PM Alexandre Demers wrote: > > On Thu, Feb 27, 2025 at 9:23 AM Alex Deucher wrote: > > > > On Thu, Feb 27, 2025 at 12:49 AM Alexandre Demers > > wrote: > > > > > > DCE6 was missing soft reset, but it was easily identifiable under radeon. > > > This should be it, pret

Re: [PATCH 2/6] drm/amdgpu: add dce_v6_0_soft_reset() to DCE6

On Thu, Feb 27, 2025 at 9:23 AM Alex Deucher wrote: > > On Thu, Feb 27, 2025 at 12:49 AM Alexandre Demers > wrote: > > > > DCE6 was missing soft reset, but it was easily identifiable under radeon. > > This should be it, pretty much as it is done under DCE8 and DCE10. > > > > Signed-off-by: Alexan

Re: [PATCH 2/6] drm/amdgpu: add dce_v6_0_soft_reset() to DCE6

On Thu, Feb 27, 2025 at 2:01 PM Alex Deucher wrote: > > On Thu, Feb 27, 2025 at 1:52 PM Alexandre Demers > wrote: > > > > On Thu, Feb 27, 2025 at 9:23 AM Alex Deucher wrote: > > > > > > On Thu, Feb 27, 2025 at 12:49 AM Alexandre Demers > > > wrote: > > > > > > > > DCE6 was missing soft reset, b

RE: [PATCH 1/2] drm/amdkfd: Add pm_config_dequeue_wait_counts API

[Public] Overall lgtm. A comment and nitpick below. > -Original Message- > From: amd-gfx On Behalf Of Harish > Kasiviswanathan > Sent: Wednesday, February 26, 2025 2:23 PM > To: amd-gfx@lists.freedesktop.org > Cc: Kasiviswanathan, Harish > Subject: [PATCH 1/2] drm/amdkfd: Add pm_config_

RE: [PATCH 2/2] drm/amdgpu: validate user queue parameters

[Public] It seems that invalid input parameters happen rarely. Using the `unlikely()` function in the validation condition can optimize the code execution path. Anyway, the patch series is Reviewed-by: Prike Liang Regards, Prike > -Original Message- > From: amd-gfx On Behalf Of

[PATCH] drm/amd/pm: Fix indentation issue

Fix indentation issue for smu_v_13_0_12 get_gpu_metrics Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202502272246.oisqunc1-...@intel.com Signed-off-by: Asad Kamal --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 2 +- 1 file changed, 1 insertion(+),

Re: [PATCH v3] drm/amdgpu: fix the memleak caused by fence not released

On 2/27/2025 7:55 PM, Christian König wrote: Am 18.02.25 um 15:53 schrieb Arvind Yadav: Encountering a taint issue during the unloading of gpu_sched due to the fence not being released/put. In this context, amdgpu_vm_clear_freed is responsible for creating a job to update the page table (PT).

Re: [PATCH 3/6] drm/amdgpu: complete dce_v6_0_set_crtc_vline_interrupt_state() in DCE6

On Thu, Feb 27, 2025 at 12:23 AM Alexandre Demers wrote: > > dce_v6_0_set_crtc_vline_interrupt_state() was empty without any info to > inform the user. Doesn't hurt to fill it in, but nothing uses the vline interrupt at the moment. Might be better to just remove it from all of the non-DC display

Re: [PATCH v2 4/4] drm/amdgpu/gfx12: Implement the GFX12 KCQ pipe reset

On Thu, Feb 27, 2025 at 7:36 AM Liang, Prike wrote: > > [AMD Official Use Only - AMD Internal Distribution Only] > > Please review the series patch to catch up the gfx latest base and to avoid > the commit merged problem. See my comment on patch 1: #define RS64_FW_UC_START_ADDR_LO 0x3000 Will

[PATCH 2/2] drm/amdgpu: Add support for CPERs on virtualization

Add support for CPERs on VFs. VFs do not receive PMFW messages directly; as such, they need to query them from the host. To avoid hitting host event guard, CPER queries need to be rate limited. CPER queries share the same RAS telemetry buffer as error count query, so a mutex protecting the shared

[PATCH 1/2] drm/amdgpu: Update headers for CPER support on SRIOV

Update amdgv_sriovmsg.h and mxgpu_nv.h to add new definitions for CPER support on VFs. PMFW ACA messages are not available on VFs, and VFs must query CPERs from host. Signed-off-by: Tony Yi --- drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 40 ++--- drivers/gpu/drm/amd/amdgpu/mxg

Re: [PATCH 2/6] drm/amdgpu: add dce_v6_0_soft_reset() to DCE6

On Thu, Feb 27, 2025 at 12:49 AM Alexandre Demers wrote: > > DCE6 was missing soft reset, but it was easily identifiable under radeon. > This should be it, pretty much as it is done under DCE8 and DCE10. > > Signed-off-by: Alexandre Demers > --- > drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 62 +

Re: [PATCH v3] drm/amdgpu: fix the memleak caused by fence not released

Am 18.02.25 um 15:53 schrieb Arvind Yadav: > Encountering a taint issue during the unloading of gpu_sched > due to the fence not being released/put. In this context, > amdgpu_vm_clear_freed is responsible for creating a job to > update the page table (PT). It allocates kmem_cache for > drm_sched

Re: [PATCH] drm/amdgpu: Fix parameter annotation in vcn_v5_0_0_is_idle

Reviewed-by: Alex Deucher On Tue, Feb 25, 2025 at 8:52 PM Srinivasan Shanmugam wrote: > > Update parameter description in the vcn_v5_0_0_is_idle function > > Fixes the below with gcc W=1: > drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c:1231: warning: Function parameter or > struct member 'ip_block' n

Re: [PATCH] drm/amdgpu: Fix parameter annotations for VCN clock gating functions

Reviewed-by: Alex Deucher On Tue, Feb 25, 2025 at 8:43 PM Srinivasan Shanmugam wrote: > > The previous references to a non-existent `adev` parameter have been > removed & corrected to reflect the use of the `vinst` pointer, which > points to the VCN instance structure, in the below files: > > -

Re: [PATCH v3] drm/amdgpu: fix the memleak caused by fence not released

Am 27.02.25 um 16:08 schrieb Yadav, Arvind: > > On 2/27/2025 7:55 PM, Christian König wrote: >> >> Am 18.02.25 um 15:53 schrieb Arvind Yadav: >>> Encountering a taint issue during the unloading of gpu_sched >>> due to the fence not being released/put. In this context, >>> amdgpu_vm_clear_freed is r

Re: [PATCH v3] drm/amdgpu: fix the memleak caused by fence not released

On 2/27/2025 9:12 PM, Christian König wrote: No, no that's wrong. That timeline_syncobj is NULL is not an error. In other words when args->vm_timeline_syncobj_out == 0 then amdgpu_gem_update_timeline_node() should just set timeline_syncobj=NULL and return 0. The error happens only if either

Re: [PATCH 3/3] drm/amdgpu/sdma_v4_4_2: update VM flush implementation for SDMA

Am 27.02.25 um 12:47 schrieb jesse.zh...@amd.com: > This commit updates the VM flush implementation for the SDMA engine. > > - Added a new function `sdma_v4_4_2_get_invalidate_req` to construct the > VM_INVALIDATE_ENG0_REQ > register value for the specified VMID and flush type. This function ens

Re: [PATCH 2/3 v5] drm/amdgpu: Optimize VM invalidation engine allocation and synchronize GPU TLB flush

Am 27.02.25 um 12:47 schrieb jesse.zh...@amd.com: > From: "jesse.zh...@amd.com" > > - Modify the VM invalidation engine allocation logic to handle SDMA page > rings. > SDMA page rings now share the VM invalidation engine with SDMA gfx rings > instead of > allocating a separate engine. This c

Re: [PATCH v2] drm/amdkfd: Fix instruction hazard in gfx12 trap handler

On 2/7/2025 17:38, Jay Cornwall wrote: VALU instructions with SGPR source need wait states to avoid hazard with SALU using different SGPR. v2: Eliminate some hazards to reduce code explosion Signed-off-by: Jay Cornwall Cc: Lancelot Six Ping.