[why]
How we determine the dsc_aux used for dsc decompression in
drm_dp_mst_dsc_aux_for_port() today has defects:
1. The method how we determine a connected peer device is virtual or not
in drm_dp_mst_is_virtual_dpcd() is not always correct. There are DP1.4
products
in the market which don'
On 11/1/2024 14:48, Mohamed, Zaeem wrote:
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Mario,
Do I need to re-send the patch to amd-gfx after the tags have been added or is
sending upstream enough?
Zaeem
Zaeem,
No need to resend to amd-gfx, they can be added when they're com
From: Fangzhi Zuo
[Why]
1. HDMI does not have 6 bpc support. Having 6 bpc pass validation
does not comply with spec.
2. Validate 420 only for native HDMI, but not apply to pcon use
case.
3. Current mode validation log is not readable.
[how]
1. Cap 8 bpc for dp-hdmi converter.
2. Validate yuv420
From: Samson Tam
[Why & How]
Move from pointer to callback to reference callback directly
Missed renaming fixpt functions with spl prefix
Reviewed-by: Navid Assadian
Signed-off-by: Samson Tam
Signed-off-by: Zaeem Mohamed
---
.../gpu/drm/amd/display/dc/dc_spl_translate.c | 14
driver
This DC patchset brings improvements in multiple areas. In summary, we have:
- Prune Invalid Modes for HDMI Output
- SPL Cleanup
- Fix brightness level not retained over reboot
- Remove inaccessible registers from DMU diagnostics
Cc: Daniel Wheeler
Aric Cyr (1):
drm/amd/display: 3.2.308
Au
From: Dominik Kaszewski
[Why]
Code reading rxstatus message size was incorrectly assigning it to
uint8_t, despite the value being 10 bits long (lower byte plus lowest
2 bits from upper byte). This caused the highest 2 bits to be ignored,
potentially missing invalid values.
[How]
Change all local
From: Ausef Yousof
This reverts commit f767e41a6f6b70cd222edd24549c1fa753c550fc.
[why & how]
The offending commit caused a lighting issue for Samsung Odyssey G9
monitors when connecting via USB-C. The commit was intended to block certain
UHBR rates.
Reviewed-by: Charlene Liu
Signed-off-by: Au
From: Aurabindo Pillai
An upstream bug report suggests that there are production dGPUs that are
older than DCN401 but still have a umc_info in VBIOS tables with the
same version as expected for a DCN401 product. Hence, reading this
tables should be guarded with a version check.
Closes: https://g
From: Ausef Yousof
[why&how]
Adjust otg w/a disable condition to include HPO explicitly rather than
assuming it is implicitly used through DP2.
Reviewed-by: Charlene Liu
Signed-off-by: Ausef Yousof
Signed-off-by: Zaeem Mohamed
---
.../drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 10 +
Currently, DRM atomic uAPI allows only primary planes to be flipped
asynchronously. However, each driver might be able to perform async
flips in other different plane types. To enable drivers to set their own
restrictions on which type of plane they can or cannot flip, use the
existing atomic_async
amdgpu can handle async flips on overlay planes, so allow it for atomic
async checks.
Signed-off-by: André Almeida
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pla
Hi,
As per my previous patchsets, the goal of this work is to find a nice way to
allow amdgpu to perform async page flips in the overlay plane as well, not
only on the primary one. Currently, when using the atomic uAPI, this is the only
type of plane allowed to do async flips, and every driver acc
On 11/1/2024 08:49, Zaeem Mohamed wrote:
From: Tom Chung
[Why]
During boot up and resume the DC layer will reset the panel
brightness to fix a flicker issue.
It will cause the dm->actual_brightness is not the current panel
brightness level. (the dm->brightness is the correct panel level)
[How
From: Ausef Yousof
[why&how]
Applying a hw w/a only relevant to DIG FIFO causing corruption
using HPO, do not apply the w/a if on DP2/HPO
Reviewed-by: Charlene Liu
Signed-off-by: Ausef Yousof
Signed-off-by: Zaeem Mohamed
---
.../drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 11
On 10/31/2024 15:50, Antonio Quartulli wrote:
On 31/10/2024 20:37, Mario Limonciello wrote:
On 10/31/2024 10:28, Antonio Quartulli wrote:
acpi_evaluate_object() may return AE_NOT_FOUND (failure), which
would result in dereferencing buffer.pointer (obj) while being NULL.
Although this case may
Add a mising reg field to the autogenerated header for future use
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h
b/drivers/gpu/drm
[Public]
Reviewed-by: Dillon Varone
-Original Message-
From: Aurabindo Pillai
Sent: Friday, November 1, 2024 12:24 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wentland, Harry ; Siqueira, Rodrigo
; Li, Sun peng (Leo) ; Varone,
Dillon ; Pillai, Aurabindo
Subject: [PATCH] drm/amd/display:
From: Nicholas Kazlauskas
[Why]
SEC_CNTL isn't readable by x86 and can block Z8 entry if read.
[How]
Remove the read.
Reviewed-by: Ovidiu Bunea
Reviewed-by: Charlene Liu
Signed-off-by: Nicholas Kazlauskas
Signed-off-by: Zaeem Mohamed
---
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c |
From: Austin Zheng
[Why/How]
Tearing can occur if there is a flip immediate plane and SW cursor.
check_subvp_sw_cursor_fallback_req falls back to SW cursor if the
stream has the potential to use subVP.
Check for fallback not needed if HW cursor is required.
e.g. Fullscreen gaming
Reviewed-by: Di
From: Samson Tam
[Why]
During mode validation, there maybe modes that fail
max_downscale_src_width check and scaling_quality
taps are 0. This will cause an assert to trigger
in spl_set_filters_data() because taps are 0.
[How]
Move taps calculation for non-adaptive scaling mode
to separate f
From: Aric Cyr
This version brings along following fixes:
- Prune Invalid Modes for HDMI Output
- SPL Cleanup
- Fix brightness level not retained over reboot
- Remove inaccessible registers from DMU diagnostics
Signed-off-by: Aric Cyr
Signed-off-by: Zaeem Mohamed
---
drivers/gpu/drm/amd/displ
From: Wayne Lin
[Why]
Observe after suspend/resme, we can't light up mst monitors under specific
mst hub. The reason is that driver still writes DPCD DP_MSTM_CTRL after LT.
It's forbidden even we write the same value for that dpcd register.
[How]
We already resume the mst branch device dpcd sett
From: Ilya Bakoulin
[Why/How]
Move the wait for pending updates past prepare_bandwidth if the previous
update was not a full update to reduce the average time it takes to
complete a full update.
Reviewed-by: Dillon Varone
Reviewed-by: Alvin Lee
Signed-off-by: Ilya Bakoulin
Signed-off-by: Zaee
From: Tom Chung
[Why]
During boot up and resume the DC layer will reset the panel
brightness to fix a flicker issue.
It will cause the dm->actual_brightness is not the current panel
brightness level. (the dm->brightness is the correct panel level)
[How]
Set the backlight level after do the set
From: Charlene Liu
[why]
insert divided by zero protection
Reviewed-by: Alvin Lee
Signed-off-by: Charlene Liu
Signed-off-by: Zaeem Mohamed
---
drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/modules/fr
From: Taimur Hassan
- Add DPCS health check
- Update USB4 PHY SSC
- Fix FAMS2 SubVP Close to VBlank changes
- Create VESA Aux-based backlight control path
- Fix PSR1 CRC error during CTS test
Signed-off-by: Taimur Hassan
Signed-off-by: Zaeem Mohamed
---
drivers/gpu/drm/amd/display/dmub/inc/dm
From: Kaitlyn Tse
[Why]
Implement the new backlight_level_params structure as part of the VBAC
framework, the information in this structure is needed to be passed down
to the DMCUB to identify the backlight control type, to adjust the
backlight of the panel and to perform any required conversions
On Wed, Oct 30, 2024 at 9:17 PM Kenneth Feng wrote:
>
> Correct the workload setting in order not to mix the setting
> with the end user. Update the workload mask accordingly.
>
> v2: changes as below:
> 1. the end user can not erase the workload from driver except default
> workload.
> 2. always
[AMD Official Use Only - AMD Internal Distribution Only]
Hi all,
This week this patchset was tested on 4 systems, two dGPU and two APU based,
and tested across multiple display and connection types.
APU
* Single Display eDP -> 1080p 60hz, 2560x1600 120hz, 1920x1200 165hz
* Singl
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Mario,
Do I need to re-send the patch to amd-gfx after the tags have been added or is
sending upstream enough?
Zaeem
-Original Message-
From: Limonciello, Mario
Sent: Friday, November 1, 2024 11:43 AM
To: Mohamed, Zaeem ; amd
[why]
Starting from dp2 where dsc passthrough is introduced, it is required to
identify
the dsc passthrough aux, apart from dsc decompression aux. Existing
drm_dp_mst_port function
that returns dsc_aux alone is not sufficient.
[how]
1. Interface change in drm_dp_mst_dsc_aux_for_port, and depende
The patch series is to refactor existing dsc determination policy for
dsc decompression and dsc passthrough given a mst output port.
Original routine was written based on different peer device types
which is not accurate and shows difficulty when expanding support of
products that do not fully com
On Tue, Oct 29, 2024 at 10:51:34AM +0100, Christian König wrote:
> Am 25.10.24 um 10:48 schrieb Raag Jadav:
> > Add documentation for device wedged event in a new 'Device wedging'
> > chapter. The describes basic definitions and consumer expectations
> > along with an example.
> >
> > v8: Improve
On 31/10/2024 20:37, Mario Limonciello wrote:
On 10/31/2024 10:28, Antonio Quartulli wrote:
acpi_evaluate_object() may return AE_NOT_FOUND (failure), which
would result in dereferencing buffer.pointer (obj) while being NULL.
Although this case may be unrealistic for the current code, it is
stil
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Asad Kamal
Thanks & Regards
Asad
-Original Message-
From: amd-gfx On Behalf Of Lijo Lazar
Sent: Wednesday, October 30, 2024 2:00 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Kamal,
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