[Public]
Reviewed-by: Dillon Varone <dillon.var...@amd.com>
-----Original Message-----
From: Aurabindo Pillai <aurabindo.pil...@amd.com>
Sent: Friday, November 1, 2024 12:24 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wentland, Harry <harry.wentl...@amd.com>; Siqueira, Rodrigo
<rodrigo.sique...@amd.com>; Li, Sun peng (Leo) <sunpeng...@amd.com>; Varone,
Dillon <dillon.var...@amd.com>; Pillai, Aurabindo <aurabindo.pil...@amd.com>
Subject: [PATCH] drm/amd/display: Add a missing DCN401 reg definition
Add a mising reg field to the autogenerated header for future use
Signed-off-by: Aurabindo Pillai <aurabindo.pil...@amd.com>
---
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h
b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h
index f42a276499cd..5d9d5fea6e06 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h
@@ -6199,10 +6199,12 @@
#define DCHUBBUB_CTRL_STATUS__ROB_UNDERFLOW_STATUS__SHIFT
0x1
#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS__SHIFT
0x2
#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR__SHIFT
0x3
+#define DCHUBBUB_CTRL_STATUS__DCHUBBUB_HW_DEBUG__SHIFT
0x4
#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE__SHIFT
0x1f
#define DCHUBBUB_CTRL_STATUS__ROB_UNDERFLOW_STATUS_MASK
0x00000002L
#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS_MASK
0x00000004L
#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR_MASK
0x00000008L
+#define DCHUBBUB_CTRL_STATUS__DCHUBBUB_HW_DEBUG_MASK
0x3FFFFFF0L
#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE_MASK
0x80000000L
//DCHUBBUB_TIMEOUT_DETECTION_CTRL1
#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS__SHIFT
0x0
--
2.39.5
