Hi Maxime,
On 26/09/24 12:56, Maxime Ripard wrote:
On Thu, Sep 26, 2024 at 12:36:49PM GMT, Vignesh Raman wrote:
Update the documentation to require linking to a relevant GitLab
issue for each new flake entry instead of an email report. Added
specific GitLab issue URLs for i915, xe and other dri
On 9/25/2024 1:24 PM, Pierre-Eric Pelloux-Prayer wrote:
> Reading pm values from the GPU shouldn't prevent it to be suspended
> by resetting the last active timestamp (eg: if an background app
> monitors GPU sensors every second, it would prevent the autosuspend
> sequence to trigger).
>
> Test
Follow-up, qla2xxx appears to be fixed, most recent test was with:
commit 684a64bf32b6e488004e0ad7f0d7e922798f65b6 (HEAD -> master,
origin/master, origin/HEAD)
Merge: f7fccaa77271 68898131d2df
Author: Linus Torvalds
Date: Tue Sep 24 15:44:18 2024 -0700
Merge tag 'nfs-for-6.12-1' of
git://g
[AMD Official Use Only - AMD Internal Distribution Only]
>>+ refresh = (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) &&
>>+ (adev->gmc.reset_flags & AMDGPU_GMC_INIT_RESET_NPS);
Is there a corner case that reloading with a different version tos and
refreshing nps cha
Am 26.09.24 um 11:31 schrieb Paneer Selvam, Arunpravin:
Hi Christian,
On 9/26/2024 2:57 PM, Christian König wrote:
Am 25.09.24 um 21:59 schrieb Arunpravin Paneer Selvam:
[SNIP]
+int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *filp)
+{
+ stru
On Mon, 2024-09-23 at 15:35 +0100, Tvrtko Ursulin wrote:
>
> Ping Christian and Philipp - reasonably happy with v2? I think it's
> the
> only unreviewed patch from the series.
Howdy,
sry for the delay, I had been traveling.
I have a few nits below regarding the commit message. Besides, I'm OK
On Tue, 2024-09-24 at 14:02 +0200, Christian König wrote:
> Am 24.09.24 um 11:58 schrieb Tvrtko Ursulin:
> >
> > On 24/09/2024 10:45, Tvrtko Ursulin wrote:
> > >
> > > On 24/09/2024 09:20, Christian König wrote:
> > > > Am 16.09.24 um 19:30 schrieb Tvrtko Ursulin:
> > > > > From: Tvrtko Ursulin
[AMD Official Use Only - AMD Internal Distribution Only]
From: Frank Min
Without setting dcc bit, there is ramdon PTE copy corruption on sdma 7.
so add this bit and update the packet format accordingly.
Signed-off-by: Frank Min
---
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 7 +--
1 file c
On 9/25/2024 8:02 PM, Pierre-Eric Pelloux-Prayer wrote:
>
>
> Le 25/09/2024 à 15:35, Lazar, Lijo a écrit :
>>
>>
>> On 9/25/2024 1:24 PM, Pierre-Eric Pelloux-Prayer wrote:
>>> Don't wake up the GPU for reading pm values. Instead, take a runtime
>>> powermanagement ref when trying to read it if
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Feifei Xu
-Original Message-
From: amd-gfx On Behalf Of Lijo Lazar
Sent: Tuesday, September 24, 2024 1:57 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Koenig, Christian ;
Bhardwaj,
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Feifei Xu
-Original Message-
From: amd-gfx On Behalf Of Lijo Lazar
Sent: Tuesday, September 24, 2024 1:57 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Koenig, Christian ;
Bhardwaj,
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Feifei Xu
-Original Message-
From: amd-gfx On Behalf Of Lijo Lazar
Sent: Tuesday, September 24, 2024 1:57 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Koenig, Christian ;
Bhardwaj,
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Feifei Xu
-Original Message-
From: amd-gfx On Behalf Of Lijo Lazar
Sent: Tuesday, September 24, 2024 1:57 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Koenig, Christian ;
Bhardwaj,
Am 26.09.24 um 10:18 schrieb Philipp Stanner:
On Tue, 2024-09-24 at 14:02 +0200, Christian König wrote:
Am 24.09.24 um 11:58 schrieb Tvrtko Ursulin:
On 24/09/2024 10:45, Tvrtko Ursulin wrote:
On 24/09/2024 09:20, Christian König wrote:
Am 16.09.24 um 19:30 schrieb Tvrtko Ursulin:
From: Tvrtk
Le 26/09/2024 à 10:55, Lazar, Lijo a écrit :
On 9/25/2024 1:24 PM, Pierre-Eric Pelloux-Prayer wrote:
Reading pm values from the GPU shouldn't prevent it to be suspended
by resetting the last active timestamp (eg: if an background app
monitors GPU sensors every second, it would prevent the a
On 9/25/2024 1:24 PM, Pierre-Eric Pelloux-Prayer wrote:
> Don't wake up the GPU for reading pm values. Instead, take a runtime
> powermanagement ref when trying to read it iff the GPU is already
> awake.
>
> This avoids spurious wake ups (eg: from applets).
>
> We use pm_runtime_get_if_in_acti
Am 25.09.24 um 21:59 schrieb Arunpravin Paneer Selvam:
[SNIP]
+int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *filp)
+{
+ struct drm_amdgpu_userq_fence_info *fence_info = NULL;
+ struct drm_amdgpu_userq_wait *wait_info = dat
Hi Christian,
On 9/26/2024 2:57 PM, Christian König wrote:
Am 25.09.24 um 21:59 schrieb Arunpravin Paneer Selvam:
[SNIP]
+int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *filp)
+{
+ struct drm_amdgpu_userq_fence_info *fence_info = NULL;
+ s
On 9/26/2024 2:31 PM, Xu, Feifei wrote:
> [AMD Official Use Only - AMD Internal Distribution Only]
>
>>> + refresh = (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) &&
>>> + (adev->gmc.reset_flags & AMDGPU_GMC_INIT_RESET_NPS);
>
> Is there a corner case that reloadi
On 9/25/2024 7:59 PM, Pierre-Eric Pelloux-Prayer wrote:
>
>
> Le 25/09/2024 à 15:37, Lazar, Lijo a écrit :
>>
>>
>> On 9/25/2024 1:24 PM, Pierre-Eric Pelloux-Prayer wrote:
>>> pm_runtime_get_if_in_use already checks if the GPU is active,
>>> so there's no need for manually checking runtimepm s
Hi Christian,
On 9/26/2024 3:04 PM, Christian König wrote:
Am 26.09.24 um 11:31 schrieb Paneer Selvam, Arunpravin:
Hi Christian,
On 9/26/2024 2:57 PM, Christian König wrote:
Am 25.09.24 um 21:59 schrieb Arunpravin Paneer Selvam:
[SNIP]
+int amdgpu_userq_wait_ioctl(struct drm_device *dev, voi
On 25/09/2024 14:55, Mario Limonciello wrote:
Alex,
Unfortunately I can't reproduce the regression on the APU I tried.
However I do have a suspicion on a fix.
Can you see if this helps? If it does, we can squash it in.
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/dr
On 9/25/2024 11:50 PM, Alex Deucher wrote:
> SR-IOV fetches the vbios from VRAM in some cases.
> Re-enable the VRAM path for dGPUs and rename the function
> to make it clear that it is not IGP specific.
>
> Fixes: 042658d17a54 ("drm/amdgpu: clean up vbios fetching code")
> Signed-off-by: Alex D
Am 26.09.24 um 12:26 schrieb Paneer Selvam, Arunpravin:
Hi Christian,
On 9/26/2024 3:04 PM, Christian König wrote:
Am 26.09.24 um 11:31 schrieb Paneer Selvam, Arunpravin:
Hi Christian,
On 9/26/2024 2:57 PM, Christian König wrote:
Am 25.09.24 um 21:59 schrieb Arunpravin Paneer Selvam:
[SNIP]
Update the documentation to require linking to a relevant GitLab
issue for each new flake entry instead of an email report. Added
specific GitLab issue URLs for i915, xe and other drivers.
Signed-off-by: Vignesh Raman
---
v2:
- Add gitlab issue link for msm driver.
---
Documentation/gpu/automa
On Thu, Sep 26, 2024 at 12:36:49PM GMT, Vignesh Raman wrote:
> Update the documentation to require linking to a relevant GitLab
> issue for each new flake entry instead of an email report. Added
> specific GitLab issue URLs for i915, xe and other drivers.
>
> Signed-off-by: Vignesh Raman
> ---
>
On Thu, Sep 26, 2024 at 12:36:49PM GMT, Vignesh Raman wrote:
> Update the documentation to require linking to a relevant GitLab
> issue for each new flake entry instead of an email report. Added
> specific GitLab issue URLs for i915, xe and other drivers.
>
> Signed-off-by: Vignesh Raman
> ---
>
From: Jiadong Zhu
Extract the resume sequence from sdma_v5_0_gfx_resume for
starting/restarting an individual instance.
Signed-off-by: Jiadong Zhu
Acked-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 253 ++---
1 file changed, 138 insertions(+), 115 deletion
From: Jiadong Zhu
Implement sdma queue reset callback via MMIO.
v2: enter/exit safemode when sdma queue reset.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 88 ++
1 file changed, 88 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_
From: Jiadong Zhu
Extract the resume sequence from sdma_v5_2_gfx_resume for
starting/restarting an individual instance.
Signed-off-by: Jiadong Zhu
Acked-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 247 ++---
1 file changed, 136 insertions(+), 111 deletion
From: Jiadong Zhu
Implement sdma queue reset callback via MMIO.
v2: enter/exit safemode for mmio queue reset.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 91 ++
1 file changed, 91 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v
On 24/09/2024 10:12, Thomas Zimmermann wrote:
Call drm_client_setup() to run the kernel's default client setup
for DRM. Set fbdev_probe in struct drm_driver, so that the client
setup can start the common fbdev client.
The tidss driver specifies a preferred color mode of 32. As this
is the defaul
On Thu, Sep 26, 2024 at 3:58 AM wrote:
>
> From: Jiadong Zhu
>
> Implement sdma queue reset callback via MMIO.
>
> v2: enter/exit safemode when sdma queue reset.
>
> Signed-off-by: Jiadong Zhu
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 88 +
[AMD Official Use Only - AMD Internal Distribution Only]
-Original Message-
From: Alex Deucher
Sent: Thursday, September 26, 2024 1:17 AM
To: Zhang, Yifan
Cc: amd-gfx@lists.freedesktop.org; Yang, Philip ;
Kuehling, Felix
Subject: Re: [PATCH] drm/amdgpu: simplify vram alloc logic since
On 9/26/2024 5:56 PM, Pierre-Eric Pelloux-Prayer wrote:
>
>
> Le 26/09/2024 à 11:27, Lazar, Lijo a écrit :
>>
>>
>> On 9/25/2024 1:24 PM, Pierre-Eric Pelloux-Prayer wrote:
>>> Don't wake up the GPU for reading pm values. Instead, take a runtime
>>> powermanagement ref when trying to read it if
On Thu, Sep 26, 2024 at 7:18 AM Lazar, Lijo wrote:
>
>
>
> On 9/25/2024 11:50 PM, Alex Deucher wrote:
> > SR-IOV fetches the vbios from VRAM in some cases.
> > Re-enable the VRAM path for dGPUs and rename the function
> > to make it clear that it is not IGP specific.
> >
> > Fixes: 042658d17a54 ("
On Thu, Sep 26, 2024 at 3:48 AM wrote:
>
> From: Jiadong Zhu
>
> Implement sdma queue reset callback via MMIO.
>
> v2: enter/exit safemode for mmio queue reset.
>
> Signed-off-by: Jiadong Zhu
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 91 ++
[Public]
Reviewed-by: Roman Li
> -Original Message-
> From: SHANMUGAM, SRINIVASAN
> Sent: Wednesday, September 25, 2024 11:10 AM
> To: Siqueira, Rodrigo ; Pillai, Aurabindo
>
> Cc: amd-gfx@lists.freedesktop.org; SHANMUGAM, SRINIVASAN
> ; Chung, ChiaHsuan (Tom)
> ; Li, Roman ; Hung, Ale
Reviewed-by: Marek Olšák
Marek
On Thu, Sep 26, 2024 at 10:02 AM Alex Deucher wrote:
>
> On Thu, Sep 26, 2024 at 10:00 AM Marek Olšák wrote:
> >
> > Is GTT cleared too?
>
> GTT has always been cleared since it's system memory.
>
> Alex
>
>
> >
> > Marek
> >
> > On Thu, Sep 26, 2024, 09:53 Alex
Am 25.09.24 um 21:59 schrieb Arunpravin Paneer Selvam:
Add user fence wait IOCTL timeline syncobj support.
v2:(Christian)
- handle dma_fence_wait() return value.
- shorten the variable name syncobj_timeline_points a bit.
- move num_points up to avoid padding issues.
Signed-off-by: Arun
Le 26/09/2024 à 11:27, Lazar, Lijo a écrit :
On 9/25/2024 1:24 PM, Pierre-Eric Pelloux-Prayer wrote:
Don't wake up the GPU for reading pm values. Instead, take a runtime
powermanagement ref when trying to read it iff the GPU is already
awake.
This avoids spurious wake ups (eg: from applets
Am 25.09.24 um 21:59 schrieb Arunpravin Paneer Selvam:
Add few optimizations to userq fence driver.
"Few optimization and fixes for userq fence driver".
v1:(Christian):
- Remove unnecessary comments.
- In drm_exec_init call give num_bo_handles as last parameter it would
making all
Am 25.09.24 um 21:59 schrieb Arunpravin Paneer Selvam:
Add the missing error handling for xa_store() call in the function
amdgpu_userq_fence_driver_alloc().
Signed-off-by: Arunpravin Paneer Selvam
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 6 --
Am 25.09.24 um 21:59 schrieb Arunpravin Paneer Selvam:
Add a vm root BO lock before accessing the userqueue VM.
Signed-off-by: Arunpravin Paneer Selvam
---
.../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/d
Am 25.09.24 um 21:59 schrieb Arunpravin Paneer Selvam:
Screen freeze and userq fence driver crash while playing Xonotic
v2: (Christian)
- There is change that fence might signal in between testing
and grabbing the lock. Hence we can move the lock above the
if..else check and u
Ping?
On Fri, Sep 6, 2024 at 2:04 PM Alex Deucher wrote:
>
> Driver now clears VRAM on allocation. Bump the
> driver version so mesa knows when it will get
> cleared vram by default.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
> 1 file changed, 2 in
[Public]
Reviewed-by: Rajneesh Bhardwaj
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Thursday, September 26, 2024 9:46 AM
To: Deucher, Alexander ; Olsak, Marek
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: bump driver version for cleared VRAM
Is GTT cleared too?
Marek
On Thu, Sep 26, 2024, 09:53 Alex Deucher wrote:
> Ping?
>
> On Fri, Sep 6, 2024 at 2:04 PM Alex Deucher
> wrote:
> >
> > Driver now clears VRAM on allocation. Bump the
> > driver version so mesa knows when it will get
> > cleared vram by default.
> >
> > Signed-off-b
On Thu, Sep 26, 2024 at 10:00 AM Marek Olšák wrote:
>
> Is GTT cleared too?
GTT has always been cleared since it's system memory.
Alex
>
> Marek
>
> On Thu, Sep 26, 2024, 09:53 Alex Deucher wrote:
>>
>> Ping?
>>
>> On Fri, Sep 6, 2024 at 2:04 PM Alex Deucher
>> wrote:
>> >
>> > Driver now c
On Thu, Sep 26, 2024 at 10:45 AM Zhang, Yifan wrote:
>
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> -Original Message-
> From: Alex Deucher
> Sent: Thursday, September 26, 2024 1:17 AM
> To: Zhang, Yifan
> Cc: amd-gfx@lists.freedesktop.org; Yang, Philip ;
> Kuehling, F
Mario and Melissa,
Another regression identified on this patch - DP Display is not listed
as an audio device after this patch is applied.
Cheers,
Alex Hung
On 9/18/24 15:38, Mario Limonciello wrote:
From: Melissa Wen
drm_edid_connector_update() updates display info, filling ELD with audio
>>I guess you are referring to the below corner case
1) Place NPS request
2) Unload Driver
3) Reinstall driver with a different TOS (possible but quite unlikely)
4) Driver reload
5) Driver checks TOS version first and goes for a reset
6) reset_flag of GMC is not set, hence it d
Update the documentation to specify linking to a relevant GitLab
issue or email report for each new flake entry. Added specific
GitLab issue urls for i915, msm and amdgpu driver.
Acked-by: Abhinav Kumar # msm
Acked-by: Dmitry Baryshkov # msm
Signed-off-by: Vignesh Raman
---
v2:
- Add gitlab is
On 9/26/2024 12:06 AM, Vignesh Raman wrote:
Update the documentation to require linking to a relevant GitLab
issue for each new flake entry instead of an email report. Added
specific GitLab issue URLs for i915, xe and other drivers.
Signed-off-by: Vignesh Raman
---
v2:
- Add gitlab issue li
On 9/27/2024 9:26 AM, Xu, Feifei wrote:
>>>I guess you are referring to the below corner case
>
>>> 1) Place NPS request
>
>>> 2) Unload Driver
>
>>> 3) Reinstall driver with a different TOS (possible but quite
> unlikely)
>
>>> 4) Driver reload
>
>
This series adds supports for dynamic NPS switch on GC v9.4.3/9.4.4 SOC
variants.
In order to do dynamic NPS switch a sysfs interface is provided to request a new
NPS mode. If the device is part of a hive, all hive devices are required to be
in the same NPS mode. Hence a hive device request is sa
Implement PSP ring command interface for memory partitioning on the fly
on the supported asics.
Signed-off-by: Rajneesh Bhardwaj
Reviewed-by: Feifei Xu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 25 +
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 +
drivers/gpu/drm/amd
In certain use cases, NPS data needs to be refreshed again from
discovery table. Add API parameter to refresh NPS data from discovery
table.
Signed-off-by: Lijo Lazar
Reviewed-by: Rajneesh Bhardwaj
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 68 +++
drivers/gpu/drm/amd/a
If a user has requested NPS mode switch, place the request through PSP
during unload of the driver. For devices which are part of a hive, all
requests are placed together. If one of them fails, revert back to the
current NPS mode.
Signed-off-by: Lijo Lazar
Signed-off-by: Rajneesh Bhardwaj
Review
Add a callback to check if there is any condition detected by GMC block
for reset on init. One case is if a pending NPS change request is
detected. If reset is done because of NPS switch, refresh NPS info from
discovery table.
Signed-off-by: Lijo Lazar
---
v2:
Move NPS request check ahead of TOS
Add a sysfs interface to see available NPS modes to switch to -
cat /sys/bus/pci/devices/../available_memory_paritition
Make the current_memory_partition sysfs node read/write for requesting a
new NPS mode. The request is only cached and at a later point a driver
unload/reload is required
Implement PSP ring command interface for memory partitioning on the fly
on the supported asics.
Signed-off-by: Rajneesh Bhardwaj
Reviewed-by: Feifei Xu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 25 +
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 +
drivers/gpu/drm/amd
This series adds supports for dynamic NPS switch on GC v9.4.3/9.4.4 SOC
variants.
In order to do dynamic NPS switch a sysfs interface is provided to request a new
NPS mode. If the device is part of a hive, all hive devices are required to be
in the same NPS mode. Hence a hive device request is sa
In certain use cases, NPS data needs to be refreshed again from
discovery table. Add API parameter to refresh NPS data from discovery
table.
Signed-off-by: Lijo Lazar
Reviewed-by: Rajneesh Bhardwaj
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 68 +++
drivers/gpu/drm/amd/a
Add dynamic NPS switch support for GC 9.4.3 variants. Only GC v9.4.3 and
GC v9.4.4 currently support this. NPS switch is only supported if an SOC
supports multiple NPS modes.
Signed-off-by: Lijo Lazar
Signed-off-by: Rajneesh Bhardwaj
Reviewed-by: Feifei Xu
---
drivers/gpu/drm/amd/amdgpu/amdgpu
Add a common interface in GMC to request NPS mode through PSP. Also add
a variable in hive and gmc control to track the last requested mode.
Signed-off-by: Rajneesh Bhardwaj
Signed-off-by: Lijo Lazar
Reviewed-by: Feifei Xu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 16
dri
This is a followup of commit b2dba064c9bd ("drm/amdgpu: Handle
sg size limit for contiguous allocation").
2GB limitation in VRAM allocation is removed in above commit.
The remaing_size calculation was to address the 2GB limitation
in contiguous VRAM allocation, thus no longer needed. Simplify
vram
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