[AMD Official Use Only - AMD Internal Distribution Only]
The series was
Reviewed-by: Likun Gao .
Regards,
Likun
-Original Message-
From: Kenneth Feng
Sent: Thursday, May 16, 2024 9:11 AM
To: amd-gfx@lists.freedesktop.org
Cc: Gao, Likun ; Feng, Kenneth
Subject: [PATCH 2/2] drm/amd/pm: e
Reviewed-by: Tom Chung
On 5/15/2024 11:23 PM, Srinivasan Shanmugam wrote:
The parameters segment_width and last_segment_width are used to control
the configuration of the Output Plane Processor (OPP), specifically the
width of each segment that the display is divided into and the width of
the l
To avoid null pointer dereference, add return check and handle null pointer.
Signed-off-by: Bob Zhou
---
.../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 28 +--
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
b
From: Tvrtko Ursulin
Reduced re-spin of my previous series after Christian corrected a few
misconceptions that I had. So lets see if what remains makes sense or is still
misguided.
To summarise, the series address the following two issues:
* Migration rate limiting does not work, at least not
From: Tvrtko Ursulin
Current code appears to live in a misconception that playing with buffer
allowed and preferred placements can always control the decision on
whether backing store migration will be attempted or not.
That is however not the case when userspace sets buffer placements of
VRAM+G
From: Tvrtko Ursulin
Currently the driver appears to be thinking that it will be attempting to
re-validate the evicted buffers on the next submission if they are not in
their preferred placement.
That however appears not to be true for the very common case of buffers
with allowed placements of V
Add support to set/get information about different DPM policies. The
support is only available on SOCs which use swsmu architecture.
A DPM policy type may be defined with different levels. For example, a
policy may be defined to select Pstate preference and then later a
pstate preference may be ch
Add PMF message to select a Pstate policy in SOCs with SMU v13.0.6.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Reviewed-by: Asad Kamal
---
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h | 3 ++-
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 ++-
2 fil
This series adds APIs to get the supported PM policies and also set them. A PM
policy type is a predefined policy type supported by an SOC and each policy may
define two or more levels to choose from. A user can select the appropriate
level through amdgpu_dpm_set_pm_policy() or through sysfs node p
Add support to set XGMI PLPD policy levels through 'pm_policy/xgmi_plpd'
sysfs node.
Signed-off-by: Lijo Lazar
---
v2, v3: No change
v4: Use a macro for XGMI PLPD policy type
v5: Use a separate sysfs node for xgmi_plpd policy
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 1 +
drivers/gpu/drm
Add support to select pstate policy in SOCs with SMUv13.0.6
Signed-off-by: Lijo Lazar
eviewed-by: Hawking Zhang
Reviewed-by: Asad Kamal
---
v2,v3: No change
v4: Use macro for policy type name
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c| 2 +
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c |
On SOCs with SMU v13.0.6, allow changing xgmi plpd policy through
'pm_policy/xgmi_plpd' sysfs interface.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Reviewed-by: Asad Kamal
---
v2, v3: No change
v4: Use macro for XGMI policy type name
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 1
On aldebaran, allow changing xgmi plpd policy through
'pm_policy/xgmi_plpd' sysfs interface.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Reviewed-by: Asad Kamal
---
.../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c| 36 +++
1 file changed, 36 insertions(+)
diff --git a/d
Replace the legacy interface with amdgpu_dpm_set_pm_policy to set XGMI
PLPD mode. Also, xgmi_plpd_policy sysfs node is not used by any client.
Remove that as well.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Reviewed-by: Asad Kamal
---
v2: No change
v3: Rebase to remove device_attr_id_
Add documentation about the newly added pm_policy node in sysfs.
Signed-off-by: Lijo Lazar
---
v5: Update documentation to reflect pm_policy nodes and sub nodes for each
policy type
Documentation/gpu/amdgpu/thermal.rst | 6
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 53 ++
Remove unused callback to set PLPD policy and its implementation from
arcturus, aldebaran and SMUv13.0.6 SOCs.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Reviewed-by: Asad Kamal
---
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 6 ---
.../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
On arcturus, allow changing xgmi plpd policy through
'pm_policy/xgmi_plpd' sysfs interface.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Reviewed-by: Asad Kamal
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 7 ++--
.../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 42 +
Convert a variable sized array from [1] to [].
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/include/atomfirmware.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h
b/drivers/gpu/drm/amd/include/atomfirmware.h
index af3eebb4c9b
Applied. Thanks!
Alex
On Wed, May 15, 2024 at 5:47 PM Kendall Smith wrote:
>
> If a Radeon 6750M GPU from an iMac12,1 is installed into an iMac 12,2, there
> is no backlight device initialized during boot. Everything else is
> functional, but the display brightness cannot be controlled. There
Reviewed-by: David (Ming Qiang) Wu
On 2024-05-15 15:19, Ruijing Dong wrote:
Update the capabilities for supporting 8k encoding/decoding.
Signed-off-by: Ruijing Dong
---
drivers/gpu/drm/amd/amdgpu/soc24.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers
Applied. Thanks!
On Thu, May 16, 2024 at 4:47 AM Jiapeng Chong
wrote:
>
> ./drivers/gpu/drm/amd/amdgpu/amdgpu.h: amdgpu_umsch_mm.h is included more
> than once.
>
> Reported-by: Abaci Robot
> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=9063
> Signed-off-by: Jiapeng Chong
> ---
> d
On 5/14/2024 4:28 PM, Alex Deucher wrote:
Add new config option and set proper dependencies for ISP.
v2: add missed guards, drop separate Kconfig
Signed-off-by: Alex Deucher
I have one optional remark regarding headers, but otherwise it looks
fine by me. Feel free to ignore it or squash
Use current speed/width on devices which don't support
dynamic PCIe switching.
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3289
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff
From: Kenneth Feng
Align with new port same as smu 13.x.
Signed-off-by: Kenneth Feng
Reviewed-by: Jack Gui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/
On Wed, May 15, 2024 at 3:57 PM Ruijing Dong wrote:
>
> Update the capabilities for supporting 8k encoding/decoding.
>
> Signed-off-by: Ruijing Dong
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/soc24.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --
On Thu, May 16, 2024 at 8:18 AM Tvrtko Ursulin wrote:
>
> From: Tvrtko Ursulin
>
> Reduced re-spin of my previous series after Christian corrected a few
> misconceptions that I had. So lets see if what remains makes sense or is still
> misguided.
>
> To summarise, the series address the following
[AMD Official Use Only - AMD Internal Distribution Only]
I didn't have time to go through every patch in detail, but overall it looks
good to me. The series is:
Acked-by: Alex Deucher
From: Lazar, Lijo
Sent: Thursday, May 16, 2024 8:43 AM
To: amd-gfx@lists.free
From: Roman Li
This DC patchset brings improvements in multiple areas. In summary, we have:
- Fix powerpc compilation
- Fix TBT+TypeC Daisy-chain lightup
- Fix underflow on dcn35
- Fix DVI for dcn401
- Add 3DLUT DMA load trigger
- Modify clock programming to support DPM
From: George Shen
Move dsc functions from dc.c to dc_dsc.c.
Co-Developed-by: George Shen
Signed-off-by: Wenjing Liu
Reviewed-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc.c| 99 -
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 96
From: Alex Hung
The comparisons intend to be DCN401 inclusive, and fix it by adding
equal signs.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/disp
From: Rodrigo Siqueira
The function that commits planes calls the same set of functions twice,
and in the case of the FAMs utilization, it is not desired to call the
dmub, hwss_build and hwss_execute. This commit just removes the
unnecessary calls to those functions.
Acked-by: Roman Li
Signed-o
From: Alex Hung
This fixes indentations and adjust spaces for better readability and
code styles.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile | 1 -
.../amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 1 -
drivers/gpu/dr
From: "Revalla, Harikrishna"
[why]
Cleaning up the code refactor requires hubbub to be in its own
component.
[how]
Move all DCN401 files under newly created hubbub folder and fixing the
makefiles.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Harikrishna Revalla
---
drivers/gpu/drm/amd/displa
From: Samson Tam
[Why]
Enable adaptive scaler support for DCN401
[How]
- Enable build flag for SPL
- Set prefer_easf flag to true
- Apply light linear scaling policy based on transfer function and pixel
format. Choose between linear or non-linear scaling
- Set matrix_mode based on pixel forma
From: Chris Park
[Why]
DVI is TMDS signal like HDMI but without audio. Current signal check
does not correctly reflect DVI clock programming.
[How]
Define a new signal check for TMDS that includes DVI to HDMI TMDS
programming.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Chris Park
---
drive
From: Chris Park
[Why]
DML 2.1 allocates two types of memory in its ctx structure but does not
destroy them, causing memory leak whenever DML 2.1 instance is created
and destroyed.
[How]
Deallocate two instances of allocated memory whenever DML 2.1 is
destroyed.
Reviewed-by: Rodrigo Siqueira
S
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c | 2 ++
drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c
b/dr
From: Dillon Varone
Need to select DTBCLK and DPREFCLK as DTBCLK_p source according to
hardware guidance.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --
From: Hersen Wu
[Why] Coverity reports NULL_RETURN warning.
[How] Add pointer NULL check.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Hersen Wu
---
.../gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/displ
From: Nicholas Susanto
[Why]
Missing check for when there is new pipe configuration but both cur_pipe
and new_pipe are both populated causing update_state of DSC for that
instance not being updated correctly.
This causes some display mode changes to cause underflow since DSCCLK
is still gated w
From: Roman Li
[Why]
For debugging and testing purposes.
[How]
If IPS is supported create ips_status debugfs entry.
Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_ips_status
Reviewed-by: Jerry Zuo
Acked-by: Roman Li
Signed-off-by: Roman Li
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 4
From: Ilya Bakoulin
[Why/How]
Need to be able to trigger a DMA load to update 3DLUT contents in MPC.
Adding a HWSS function to serve as the trigger.
Reviewed-by: Krunoslav Kovac
Acked-by: Roman Li
Signed-off-by: Ilya Bakoulin
---
drivers/gpu/drm/amd/display/dc/core/dc.c| 8
From: Dillon Varone
[WHY&HOW]
Disable to improve stability for now.
Reviewed-by: Alvin Lee
Acked-by: Roman Li
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/r
From: Dillon Varone
[WHY&HOW]
At the time of block sequence construction, the exact reference DPP/DISP clock
is
not yet known, so the clock should be passed by reference to the DTO programming
function.
Reviewed-by: Alvin Lee
Acked-by: Roman Li
Signed-off-by: Dillon Varone
---
.../dc/clk_mg
From: Wenjing Liu
The functions are missing. These two functions are required to support
MST.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Wenjing Liu
---
.../amd/display/dc/dccg/dcn401/dcn401_dccg.c | 159 ++
.../amd/display/dc/dccg/dcn401/dcn401_dccg.h | 12 ++
.../amd/di
From: Roman Li
[Why]
Disable idle optimization for each atomic commit is unnecessary,
and can lead to a potential race condition.
[How]
Remove idle optimization check from amdgpu_dm_atomic_commit_tail()
Fixes: 196107eb1e15 ("drm/amd/display: Add IPS checks before dcn register
access")
Cc: sta
From: Cruise
[Why]
When the link BW is smaller than the request BW,
the DP LT just kept running and fallback to lower link config.
DP LT just aborted if is_hpd_pending bit is high.
But is_hpd_pending bit indicates a new HPD event received.
It doesn't mean the HPD is low.
[How]
Abort the DP LT if
From: Wenjing Liu
[why]
A recent change for ODM combine refactor contains a typo which causes ODM
combine mode programmed incorrectly.
Reviewed-by: George Shen
Acked-by: Roman Li
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 2 +-
1 file changed, 1
From: Roman Li
[Why]
Reset the shared dmub firmware region on dmub hw init to start with
known state.
[How]
Memset the shared region to 0 in dmub_hw_init().
Suggested-by: Nicholas Kazlauskas
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/a
From: Aric Cyr
This version pairs with DMUB FW Release 0.0.218.0 for dcn314/315/316,
dcn35/351, dcn401
and brings along the following:
- Fix powerpc compilation
- Fix TBT+TypeC Daisy-chain lightup
- Fix ODM combine setup
- Fix OTC underflow on dcn35
- Fix DVI config for dcn401
- Add ips status
From: Alvin Lee
[Description]
There is a corner case where we're in an ODM config that
has recout.x != 0. In these scenarios we have to take into
account the extra offset in the ODM adjustment for cursor.
Reviewed-by: Aric Cyr
Acked-by: Roman Li
Signed-off-by: Alvin Lee
---
.../drm/amd/displ
From: Roman Li
[Why]
Compilation errors while compiling without CONFIG_DRM_AMD_DC_FP:
"undefined reference to `dc_bandwidth_in_kbps_from_timing'"
[How]
Fix Makefile to move dsc files out of DC_FP guard.
Fixes: 50253f5d9ff4 ("drm/amd/display: Add misc DC changes for DCN401")
Signed-off-by: Roman
Reviewed-by: Aurabindo Pillai
On 5/16/24 3:26 PM, roman...@amd.com wrote:
From: Roman Li
[Why]
Compilation errors while compiling without CONFIG_DRM_AMD_DC_FP:
"undefined reference to `dc_bandwidth_in_kbps_from_timing'"
[How]
Fix Makefile to move dsc files out of DC_FP guard.
Fixes: 50253f5
From: Tim Van Patten
The following commit updated gmc->noretry from 0 to 1 for GC HW IP
9.3.0:
commit 5f3854f1f4e2 ("drm/amdgpu: add more cases to noretry=1")
This causes the device to hang when a page fault occurs, until the
device is rebooted. Instead, revert back to gmc->noretry=0 so the
Hi Christian,
On 08/05/2024 09:26, Tvrtko Ursulin wrote:
On 08/05/2024 06:42, Christian König wrote:
Am 06.05.24 um 18:26 schrieb Tvrtko Ursulin:
On 03/05/2024 10:14, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Help code readability by replacing a bunch of:
bo->tbo.base.resv == vm->root.
./drivers/gpu/drm/amd/amdgpu/amdgpu.h: amdgpu_umsch_mm.h is included more than
once.
Reported-by: Abaci Robot
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=9063
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/driv
Applied. Thanks!
Alex
On Thu, May 16, 2024 at 3:46 PM Tim Van Patten wrote:
>
> From: Tim Van Patten
>
> The following commit updated gmc->noretry from 0 to 1 for GC HW IP
> 9.3.0:
>
> commit 5f3854f1f4e2 ("drm/amdgpu: add more cases to noretry=1")
>
> This causes the device to hang when a
This commit removes a duplicate check for *is_queue_unmap in the
sdma_v7_0_ring_set_wptr function. The check at line 171 was considered
dead code because at this point in the code, we already know that
*is_queue_unmap is false due to the check at line 161.
By removing this unnecessary check, impro
modify the lock type to 'spinlock' to avoid schedule issue
in interrupt context.
Signed-off-by: Yang Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c | 19 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h | 3 ++-
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drive
modify the lock type to 'spinlock' to avoid schedule issue
in interrupt context.
Signed-off-by: Yang Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c | 11 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h | 2 +-
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/
fix ACA no query result after gpu reset.
Signed-off-by: Yang Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c | 7 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 9 -
3 files changed, 4 insertions(+), 13 deletions(-)
diff --git a/drivers
[AMD Official Use Only - AMD Internal Distribution Only]
This patch was
Reviewed-by: Likun Gao .
Regards,
Likun
-Original Message-
From: SHANMUGAM, SRINIVASAN
Sent: Friday, May 17, 2024 11:33 AM
To: Koenig, Christian ; Deucher, Alexander
Cc: amd-gfx@lists.freedesktop.org; SHANMUGAM, S
[AMD Official Use Only - AMD Internal Distribution Only]
Series is
Reviewed-by: Asad Kamal mailto:asad.ka...@amd.com>>
Thanks & Regards
Asad
From: Deucher, Alexander
Sent: Friday, May 17, 2024 12:57 AM
To: Lazar, Lijo ; amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Kamal, Asad ;
Ma,
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Asad Kamal
Thanks & Regards
Asad
-Original Message-
From: amd-gfx On Behalf Of Gao, Likun
Sent: Friday, May 17, 2024 9:32 AM
To: SHANMUGAM, SRINIVASAN ; Koenig, Christian
; Deucher, Alexander
Cc: amd-gfx@lists.free
Hi all,
with Android 14 QPR2 there were substantial changes in graphic stack's
Android HAL (Hardware Abstraction Layer),
essentially it became mandatory that hwcomposer HAL module supports AIDL
Android Interface Definition Language,
at the moment drm_hwcomposer does not support AIDL [1]
Project
Am 16.05.24 um 19:57 schrieb Tim Van Patten:
From: Tim Van Patten
The following commit updated gmc->noretry from 0 to 1 for GC HW IP
9.3.0:
commit 5f3854f1f4e2 ("drm/amdgpu: add more cases to noretry=1")
This causes the device to hang when a page fault occurs, until the
device is reboote
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