Check the return of pp_atomfwctrl_get_Voltage_table_v4
as it may fail to initialize max_vid_step
V2: change the check condition (Tim Huang)
Signed-off-by: Jesse Zhang
---
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a
On 4/28/2024 12:38 PM, YiPeng Chai wrote:
> Add mutex to protect ras shared memory.
>
> Signed-off-by: YiPeng Chai
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c| 121 ++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h| 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c
customized the reset to skip soft recovery
Signed-off-by: Kenneth Feng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd
use the default reset for ras recovery
Signed-off-by: Kenneth Feng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index a037e8fba29f..f92b2c4f0d5c 100644
---
Clear warning that using uninitialized variable when the dpm is
not enabled and reuse the code for SMU13 to get the boot frequency.
Signed-off-by: Tim Huang
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 4 ++
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c| 55 +--
.../drm/
[Public]
Reviewed-by: Tim Huang
Best Regards,
Tim Huang
> -Original Message-
> From: Jesse Zhang
> Sent: Monday, April 29, 2024 3:29 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
> Subject
Hi guys,
yeah that is a well known issue but actually completely harmless.
What happens is that a trace function accesses a stale pointer to print
some additional value into the trace log.
That memory might have been reused and the information is now outdated,
but the worst thing that can ha
Hi,
Thank you for patching two of the bugs we have reported!
I was just wondering if there's any news on the one other bug we have
reported:
BUG: KASAN: slab-use-after-free in amdgpu_bo_move+0x1479/0x1550.
I see that there is a gitlab issue(
https://gitlab.freedesktop.org/drm/amd/-/issues/3171) c
Assign an default value to agc_btc_response in failed case
Signed-off-by: Ma Jun
---
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
b/drivers/gpu/drm/amd/pm/
Check return value of smum_send_msg_to_smc to fix
uninitialized variable varning
Signed-off-by: Ma Jun
---
.../drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 21 +
.../drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c | 20
.../drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 23
ping ...
On 4/26/2024 5:37 PM, Ma Jun wrote:
> Check the user input and phy_id value range to fix
> "Using uninitialized value phy_id"
>
> Signed-off-by: Ma Jun
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/dr
[AMD Official Use Only - General]
+@Zhang, GuoQing (Sam)
-Original Message-
From: Kenneth Feng
Sent: Monday, April 29, 2024 3:32 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Owen(SRDC) ; Aldabagh, Maad
; Ma, Qing (Mark) ; Feng, Kenneth
Subject: [PATCH 1/2] drm/amd/amdgpu: customize
[AMD Official Use Only - General]
+@Zhang, GuoQing (Sam)
-Original Message-
From: Kenneth Feng
Sent: Monday, April 29, 2024 3:32 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Owen(SRDC) ; Aldabagh, Maad
; Ma, Qing (Mark) ; Feng, Kenneth
Subject: [PATCH 2/2] drm/amd/amdgpu: use the d
[AMD Official Use Only - General]
> -Original Message-
> From: Jesse Zhang
> Sent: Monday, April 29, 2024 10:10 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
> Subject: [PATCH 3/3 V2] drm/amd/p
This commit refactors the construct_phy function. The original function
was large and complex.
The following functions were created:
- initialize_link: Handles the initial setup of the link object.
- handle_connector_type: Sets the connector_signal and irq_source_hpd_rx
based on the link_id.id.
mes schq engine require more waiting time for engine ready
before packet submission.
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/mes_v1
[AMD Official Use Only - General]
Reviewed-by: Yifan Zhang
Best Regards,
Yifan
-Original Message-
From: Xiao, Jack
Sent: Monday, April 29, 2024 5:10 PM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Zhang, Hawking ; Gao, Likun
; Zhang, Yifan ; Huang, Tim
Cc: Xiao, Jack
Su
[Public]
>-Original Message-
>From: Kuehling, Felix
>Sent: Saturday, April 27, 2024 6:45 AM
>To: Yu, Lang ; amd-gfx@lists.freedesktop.org
>Cc: Yang, Philip ; Koenig, Christian
>; Zhang, Yifan ; Liu,
>Aaron
>Subject: Re: [PATCH 2/2] drm/amdkfd: Allow memory oversubscription on
>small APUs
[Public]
>-Original Message-
>From: Kuehling, Felix
>Sent: Saturday, April 27, 2024 6:52 AM
>To: Yu, Lang ; amd-gfx@lists.freedesktop.org
>Cc: Yang, Philip ; Koenig, Christian
>; Zhang, Yifan ; Liu,
>Aaron
>Subject: Re: [PATCH 1/2] drm/amdkfd: Let VRAM allocations go to GTT
>domain on sm
Am 26.04.24 um 18:43 schrieb Tvrtko Ursulin:
From: Tvrtko Ursulin
Help code readability by replacing a bunch of:
bo->tbo.base.resv == vm->root.bo->tbo.base.resv
With:
amdgpu_bo_is_vm_bo(bo, vm)
No functional changes.
Ah,yes that was on my TODO list as well.
But I would have rather added
Am 26.04.24 um 18:43 schrieb Tvrtko Ursulin:
From: Tvrtko Ursulin
All apart from AMDGPU_GEM_DOMAIN_GTT memory domains map 1:1 to TTM
placements. And the former be either AMDGPU_PL_PREEMPT or TTM_PL_TT,
depending on AMDGPU_GEM_CREATE_PREEMPTIBLE.
Simplify a few places in the code which convert
Am 26.04.24 um 18:43 schrieb Tvrtko Ursulin:
From: Tvrtko Ursulin
When commit b453e42a6e8b ("drm/amdgpu: Add new placement for preemptible
SG BOs") added a new TTM region it missed to notice the conceptual
imbalance in GART pin size accounting as done in amdgpu_bo_pin/unpin.
That imbalance lea
Instruction modifiers of the untyped vector memory buffer instructions
(MUBUF encoded) changed in gfx940. The slc, scc and glc modifiers have
been replaced with sc0, sc1 and nt.
The current CWSR trap handler is written using pre-gfx940 modifier
names, making the source incompatible with a strict
Am 29.04.24 um 11:43 schrieb Tvrtko Ursulin:
On 26/04/2024 23:24, Felix Kuehling wrote:
On 2024-04-26 12:43, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
When commit b453e42a6e8b ("drm/amdgpu: Add new placement for
preemptible
SG BOs") added a new TTM region it missed to notice the conceptu
This patch adds a missed handling of PL domain doorbell while
handling VRAM faults.
Fixes: a6ff969fe9cb ("drm/amdgpu: fix visible VRAM handling during faults")
Cc: Christian Koenig
Cc: Alex Deucher
Signed-off-by: Shashank Sharma
Signed-off-by: Arvind Yadav
---
drivers/gpu/drm/amd/amdgpu/amdgp
Am 29.04.24 um 14:50 schrieb Shashank Sharma:
This patch adds a missed handling of PL domain doorbell while
handling VRAM faults.
Fixes: a6ff969fe9cb ("drm/amdgpu: fix visible VRAM handling during faults")
Cc: Christian Koenig
Cc: Alex Deucher
Signed-off-by: Shashank Sharma
Signed-off-by: Arv
On 26/04/2024 23:24, Felix Kuehling wrote:
On 2024-04-26 12:43, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
When commit b453e42a6e8b ("drm/amdgpu: Add new placement for preemptible
SG BOs") added a new TTM region it missed to notice the conceptual
imbalance in GART pin size accounting as don
[Public]
Hi all,
This week this patchset was tested on the following systems:
* Lenovo ThinkBook T13s Gen4 with AMD Ryzen 5 6600U
* MSI Gaming X Trio RX 6800
* Gigabyte Gaming OC RX 7900 XTX
These systems were tested on the following display/connection types:
* eD
On Mon, Apr 29, 2024 at 3:07 AM Peyton Lee wrote:
>
> Some version of BIOS does not enable all clock levels,
> resulting in high level clock frequency of 0.
> The number of valid CLKs must be confirmed in advance.
>
> Signed-off-by: Peyton Lee
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/am
This reverts commit 31729e8c21ecfd671458e02b6511eb68c2225113.
This causes problems with reboots/shutdowns for some users.
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3351
Signed-off-by: Alex Deucher
Cc: Tim Huang
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 12 +--
On Mon, Apr 29, 2024 at 3:52 AM Tim Huang wrote:
>
> Clear warning that using uninitialized variable when the dpm is
> not enabled and reuse the code for SMU13 to get the boot frequency.
>
> Signed-off-by: Tim Huang
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
[AMD Official Use Only - General]
Ping.
Sonny
From: Jiang, Sonny
Sent: Thursday, April 25, 2024 4:12 PM
To: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3] drm/amdgpu: IB test encode test package change for VCN5
By tests, I didn't find error on VCN1 to VC
Am 29.04.24 um 15:34 schrieb Tvrtko Ursulin:
On 29/04/2024 12:02, Christian König wrote:
Am 26.04.24 um 18:43 schrieb Tvrtko Ursulin:
From: Tvrtko Ursulin
Help code readability by replacing a bunch of:
bo->tbo.base.resv == vm->root.bo->tbo.base.resv
With:
amdgpu_bo_is_vm_bo(bo, vm)
No fu
On Fri, Apr 26, 2024 at 5:57 AM Ma Jun wrote:
>
> Check the user input and phy_id value range to fix
> "Using uninitialized value phy_id"
>
> Signed-off-by: Ma Jun
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c | 4
> 1 file changed, 4 insertions(+)
>
[AMD Official Use Only - General]
Reviewed-by: Leo Liu
> -Original Message-
> From: amd-gfx On Behalf Of Sonny
> Jiang
> Sent: Thursday, April 25, 2024 4:11 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Jiang, Sonny ; Jiang, Sonny
>
> Subject: [PATCH v3] drm/amdgpu: IB test encode test
From: Likun Gao
Add gfx12 clearstate register arrays.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/clearstate_gfx12.h | 121 ++
1 file changed, 121 insertions(+)
create mode 100644 drivers/gpu/drm/amd/amdgpu/c
From: Likun Gao
Add new RLC_TABLE_OF_CONTENT structure definition.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h | 27 +
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/amd/am
From: Likun Gao
Add RLC autoload TOC header file for soc24 ASIC.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h | 47 +
1 file changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdg
From: Likun Gao
Split the function of mes fimrware address setting
from mes firmware load for mes v12, as it's also
needed for rlc autoload.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 37 +++
From: Likun Gao
Keep gfx v12 mes fw name to gc_12_x_x_mes.bin
and gc_12_x_x_mes1.bin.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/
From: Jack Xiao
1. fix available compute queue to use
2. enable mes v12 self test
Signed-off-by: Jack Xiao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 2 +-
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 6 ++
2 files changed, 7 inserti
From: Likun Gao
Add gfx v12_0_0 family id
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
include/uapi/drm/amdgpu_drm.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index
From: Jack Xiao
v1: Add mes v12_0 ip block support. (Jack)
v2: Switch to gfx.kiq array. (Hawking)
v3: Switch to AMDGPU_GFXHUB(0). (Hawking)
v4: Rebase (Alex)
Signed-off-by: Jack Xiao
Reviewed-by: Hawking Zhang
Signed-off-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/
From: Jonathan Kim
Fix request to MES to set SQ_SHADER_TBA_HI.trap_en for GFX12.
Signed-off-by: Jonathan Kim
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
b/drivers/gpu/drm/amd
From: Jack Xiao
Enlarge the data cache boundary.
v2: use the fix data cache boundary.
Signed-off-by: Jack Xiao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gp
From: Kenneth Feng
support imu related function for gfx v12.
Signed-off-by: Kenneth Feng
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile| 3 +-
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 4 +-
drivers/gpu/drm/amd/
On 2024-04-29 9:45, Tvrtko Ursulin wrote:
On 29/04/2024 12:11, Christian König wrote:
Am 29.04.24 um 11:43 schrieb Tvrtko Ursulin:
On 26/04/2024 23:24, Felix Kuehling wrote:
On 2024-04-26 12:43, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
When commit b453e42a6e8b ("drm/amdgpu: Add new
From: Likun Gao
Set GC family for GC 12.0 IPs.
v2: squash in updates (Alex)
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/am
From: shaoyunl
Enable basic mode handling for doorbell ring on unmapped CP queue.
In this mode, MES can start schedule the queue mapping based on HW
interrupt instead of timer.
Signed-off-by: shaoyunl
Reviewed-by: Harish Kasiviswanthan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdg
From: Hawking Zhang
Switch to smuio callback to query gpu clock counter
Signed-off-by: Hawking Zhang
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/dr
From: Harish Kasiviswanathan
Add MES_v12 header definition for gfx12
v2: Modify SET_SHADER_DEBUGGER to match mes_v11 definition. This doesn't
change the structure layout
v3: Removed unncessary comment and spaces
Signed-off-by: Harish Kasiviswanathan
Signed-off-by: Alex Deucher
---
drivers/g
From: Kenneth Feng
add cgcg&cgls interface for gfx 12.0
Signed-off-by: Kenneth Feng
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 190 -
drivers/gpu/drm/amd/amdgpu/soc24.c | 3 +
2 files changed, 191 insertions(+
From: Jack Xiao
Recalculate the number of compute rings to use based on
the gfx hardware configuration. As needed reserve half of
compute rings for mes, kgd can't use up all compute rings.
Signed-off-by: Jack Xiao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd
From: Likun Gao
Split PFF/ME/MEC firmware address setting function
from related load microcode funtion, as it's also
needed for rlc autolad.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 186 --
From: Likun Gao
Program rlc ram with golden setting data instead.
The old method (program_imu_rlc_ram_old) should be
retired in the future.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/imu_v12_0.c | 70 ++--
From: Likun Gao
Support Save & Restore related fw load with backdoor RLC
autoload type on gfx v12.
Signed-off-by: Likun Gao
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 16
1 file changed, 16 insertions(+)
diff --git a/d
From: Likun Gao
Skip dpm check to init imu firmware for imu v12.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0
From: Likun Gao
Only execute IMU related functions if dpm>0.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12
From: Tom St Denis
Signed-off-by: Tom St Denis
Reviewed-by: Jonathan Kim
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
b/drivers/gpu/drm/amd/amdg
From: shaoyunl
Enable event log through the HW specific FW API
Signed-off-by: shaoyunl
Reviewed-by: Harish Kasiviswanthan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
b/d
From: Likun Gao
For MEC fw data, different pipe should programed into
different address.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --gi
From: Likun Gao
Move microcode loading from sw_init to early_init to align with
the perious version of imu init sequence.
Signed-off-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
dif
From: Likun Gao
Align gfxhub settings with mmhub when program rlc ram.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/imu_v12_0.c | 39 ++
1 file changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/am
From: shaoyunl
On MES12, HW can monitor up to 2048 doorbells that not be
mapped currently and trigger the interrupt to MES when these unmapped
doorbell been ringed.
Signed-off-by: shaoyunl
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 24
From: Kenneth Feng
workaournd for the imu fw loading on gfx 12.0 without psp
Signed-off-by: Kenneth Feng
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/imu_v12_0.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v12_0
From: Likun Gao
Correct the algorithm of active CU and RB to bypass
the disabled SA for gfx12.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 81 +-
1 file changed, 55 insertions(+), 26 dele
On 2024-04-29 5:43, Tvrtko Ursulin wrote:
On 26/04/2024 23:24, Felix Kuehling wrote:
On 2024-04-26 12:43, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
When commit b453e42a6e8b ("drm/amdgpu: Add new placement for preemptible
SG BOs") added a new TTM region it missed to notice the conceptual
im
From: David Belanger
Initial implementation, based on GFX11.
v2: Removed functions not needed by cp scheduler.
v3: Fixed typos.
v4: squash in warning fix (Alex)
Signed-off-by: David Belanger
Acked-by: Jonathan Kim
Reviewed-by: Harish Kasiviswanathan
Signed-off-by: Alex Deucher
---
drivers/
From: Jay Cornwall
No functional change. Preparation for gfx12 support.
v2: drop unrelated change (Alex)
Signed-off-by: Jay Cornwall
Reviewed-by: Harish Kasiviswanathan
Signed-off-by: Alex Deucher
---
.../amd/amdkfd/cwsr_trap_handler_gfx10.asm| 127 +-
1 file changed, 65
From: Jay Cornwall
- HWREG changes since gfx11
- Save/restore barrier state
- get_wave_size is now reserved by assembler
v2: rebase (Alex)
Signed-off-by: Jay Cornwall
Reviewed-by: Harish Kasiviswanathan
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/amdkfd/cwsr_trap_handler.h| 465
From: Jonathan Kim
Similar to GFX11, always enable the setup of trap temporaries on GFX12.
Signed-off-by: Jonathan Kim
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 1 +
drivers/gpu/drm/amd/amdkf
From: David Belanger
Initial implementation, based on GFX11.
v2: squash in include fix from David (Alex)
Signed-off-by: David Belanger
Reviewed-by: Harish Kasiviswanathan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdkfd/Makefile | 1 +
.../drm/amd/amdkfd/kfd_device_queu
From: Laurent Morichetti
When trap_ctrl.trap_after_inst is set, it is possible for a wave to
enter the trap handler, after single-stepping an instruction and a
save_context is raised, with only save_context set in excp_flag_priv.
Because excp_flag_priv.trap_after_inst is not reliably set, we nee
From: David Belanger
Updated switch statement to use GFX12 trap handler.
Signed-off-by: David Belanger
Reviewed-by: Harish Kasiviswanathan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/driver
From: Sreekant Somasekharan
Add new GFX12 PTE flag AMDGPU_PTE_IS_PTE to svm_range_get_pte_flags
function. This resolves the issues related to SVM enablement in GFX12.
Signed-off-by: Sreekant Somasekharan
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdkfd/k
From: Sreekant Somasekharan
Due to a HW bug, the system memory mappings and peer GPU mappings
on GFX12 need to be marked as MTYPE_NC.
Cc: Joe Greathouse
Cc: David Belanger
Signed-off-by: Rajneesh Bhardwaj
Signed-off-by: Sreekant Somasekharan
Reviewed-by: Harish Kasiviswanathan
Signed-off-by
From: Jonathan Kim
Similar to GFX11, GFX12 supports trapping on wave start and end.
Signed-off-by: Jonathan Kim
Signed-off-by: Alex Deucher
---
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c| 48 +--
1 file changed, 43 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/dr
From: David Belanger
Enable flag in KFD and set the atomic support bit in MQD.
Signed-off-by: David Belanger
Reviewed-by: Harish Kasiviswanathan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 ++
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c | 3 +++
From: Lancelot SIX
Add support to save and restore the work group barrier state in gfx12
CWSR trap handler.
There is no support to directly restore the signal count of a barrier
state, so instead this patch repeatedly calls s_barrier_signal to
increment the signal count to the desired value.
In
From: Jonathan Kim
GFX12 debugging requires setting up precise ALU operation for catching
ALU exceptions.
Signed-off-by: Jonathan Kim
Tested-by: Lancelot Six
Reviewed-by: Eric Huang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdkfd/kfd_debug.c| 15 +--
drivers/gpu/d
From: Eric Huang
mqd_stride function in gfx v12 is not implemented, that
causes NULL ptr error. Add the generic func to fix it.
Signed-off-by: Eric Huang
Reviewed-by: Harish Kasiviswanathan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c | 3 +++
1 file chang
From: Jack Xiao
Add the unified mes firmware loading support.
Signed-off-by: Jack Xiao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
b/d
From: Jack Xiao
Add the unified mes firmware loading support.
Signed-off-by: Jack Xiao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 5 -
2 files changed, 5 insertions(+), 1 deletion(-)
From: Jack Xiao
Enable the unified mes firmware on mes pipe0.
Signed-off-by: Jack Xiao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 51 +++---
1 file changed, 38 insertions(+), 13 deletions(-)
diff --git a/drivers/gp
From: Jack Xiao
For unified mes fw, add the legacy interface to set hardware
resources.
v2: remove warning (Alex)
Signed-off-by: Jack Xiao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c| 22 +--
drivers/gpu/drm/amd/i
From: Jack Xiao
Enable mes to map legacy queue support.
v2: drop unused gfx_v12_0_kiq_enable_kgq() (Alex)
Signed-off-by: Jack Xiao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 39 +
drivers/gpu/drm/amd/amdgpu/gf
From: shaoyunl
The new mechanism for unmapped doorbell handling requires both driver side and
MES fw side change. The FW side changes are still not released.
Signed-off-by: shaoyunl
Reviewed-by: Harish Kasiviswanthan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
From: Jack Xiao
Random page fault was oberserved, temporarily disable
mes log buffer output.
Signed-off-by: Jack Xiao
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/g
From: Likun Gao
Add mes v12_0 ip block.
v2: squash in update (Alex)
v3: rebase on unified mes changes (Alex)
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 9 +
1 file changed, 9 insertions(+)
diff
From: Likun Gao
Add gfx v12_0 ip block.
v2: Squash in update (Alex)
v3: add exp flag (Alex)
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gp
From: Jack Xiao
Add module parameter 'amdgpu_uni_mes' to enable/disable unified
mes fw support.
Signed-off-by: Jack Xiao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 ++
dri
From: Jack Xiao
Add mes12 map legacy queue packet submission.
Signed-off-by: Jack Xiao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/
On 4/29/2024 08:38, Alex Deucher wrote:
This reverts commit 31729e8c21ecfd671458e02b6511eb68c2225113.
This causes problems with reboots/shutdowns for some users.
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3351
Signed-off-by: Alex Deucher
Cc: Tim Huang
It would be unfortunate to
Applied. Thanks!
On Sun, Apr 28, 2024 at 9:32 PM Zhou, Bob wrote:
>
> [Public]
>
> Reviewed-by: Bob Zhou
>
> Regards,
> Bob
>
> -Original Message-
> From: Dan Carpenter
> Sent: 2024年4月28日 20:57
> To: Zhou, Bob
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Pan, Xinhui ; David Airli
Applied. Thanks!
On Wed, Apr 24, 2024 at 9:52 PM Jiapeng Chong
wrote:
>
> ./drivers/gpu/drm/amd/display/dc/inc/hw/transform.h: spl/dc_spl_types.h is
> included more than once.
>
> Reported-by: Abaci Robot
> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=8884
> Signed-off-by: Jiapeng Ch
Applied. Thanks!
On Wed, Apr 24, 2024 at 11:42 PM Jiapeng Chong
wrote:
>
> ./drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c:
> dcn401/dcn401_clk_mgr.h is included more than once.
>
> Reported-by: Abaci Robot
> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=8885
> Signed
Applied. Thanks!
On Fri, Mar 8, 2024 at 8:58 PM wrote:
>
> From: Tobias Jakobi
>
> This 8.4 inch panel is integrated in the Ayaneo Kun handheld
> device. The panel resolution is 2560×1600, i.e. it has
> portrait dimensions.
>
> Decoding the EDID shows:
> Manufacturer: MSF
> Model: 4099
> Displa
From: Tvrtko Ursulin
Instead of mixing them together with regular system memory objects mark
them explicitly as 'PREEMPTIBLE'.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Felix Kuehling
---
No idea on the name to use.. :)
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 +++
1 fi
From: Tvrtko Ursulin
All apart from AMDGPU_GEM_DOMAIN_GTT memory domains map 1:1 to TTM
placements. And the former be either AMDGPU_PL_PREEMPT or TTM_PL_TT,
depending on AMDGPU_GEM_CREATE_PREEMPTIBLE.
Simplify a few places in the code which convert the TTM placement into
a domain by checking aga
From: Tvrtko Ursulin
Help code readability by replacing a bunch of:
bo->tbo.base.resv == vm->root.bo->tbo.base.resv
With:
amdgpu_vm_is_bo_always_valid(vm, bo)
No functional changes.
v2:
* Rename helper and move to amdgpu_vm. (Christian)
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
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