Now we have two flags for contiguous VRAM buffer allocation.
If the application request for AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
it would set the ttm place TTM_PL_FLAG_CONTIGUOUS flag in the
buffer's placement function.
This patch will change the default behaviour of the two flags.
When we set AMDG
Hi Matthew,
On 4/10/2024 6:22 PM, Matthew Auld wrote:
On 08/04/2024 16:16, Arunpravin Paneer Selvam wrote:
- Add tracking clear page feature.
- Driver should enable the DRM_BUDDY_CLEARED flag if it
successfully clears the blocks in the free path. On the otherhand,
DRM buddy marks each bl
Add clear page support in vram memory region.
v1(Christian):
- Dont handle clear page as TTM flag since when moving the BO back
in from GTT again we don't need that.
- Make a specialized version of amdgpu_fill_buffer() which only
clears the VRAM areas which are not already cleared
-
- Add tracking clear page feature.
- Driver should enable the DRM_BUDDY_CLEARED flag if it
successfully clears the blocks in the free path. On the otherhand,
DRM buddy marks each block as cleared.
- Track the available cleared pages size
- If driver requests cleared memory we prefer cleared
Add a new test case for the drm buddy clear and dirty
allocation.
v2:(Matthew)
- make size as u32
- rename PAGE_SIZE with SZ_4K
- dont fragment the address space for all the order allocation
iterations. we can do it once and just increment and allocate
the size.
- create new mm wit
ping...
Regards,
Ma Jun
On 4/3/2024 10:57 AM, Ma Jun wrote:
> refactor the code of runtime pm mode detection to support
> amdgpu_runtime_pm =2 and 1 two cases
>
> Signed-off-by: Ma Jun
> Reviewed-by: Yang Wang
> ---
> v1->v2:
> - Fix logic and output info (Lijo)
> - Fix code style (Kevin)
> --
[Public]
Ping for code review. Thanks!
Regards,
Wayne
From: Wayne Lin
Sent: Thursday, March 7, 2024 14:29
To: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org;
intel-...@lists.freedesktop.org
Cc: ly...@redhat.com; Wentland, Harry; imre.d..
[AMD Official Use Only - General]
Hi Christian:
If an ecc error occurs at an address, HW will generate an interrupt to SW to
retire all pages located in the same physical row as the error address based on
the physical characteristics of the memory device.
Therefore, if other pages located
On GFX 9.4.3 SOCs, only 2 SDMA instances need to be available to be
considered as a valid AID.
Signed-off-by: Lijo Lazar
Reviewed-by: Asad Kamal
---
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/a
