ni_patch_single_dependency_table_based_on_leakage() return zero or
negative error code. But ni_patch_dependency_tables_based_on_leakage()
doesn't check the return value of the first function call. It's same for
ni_dpm_init(). It's better to add this error code check.
Signed-off-by: Su Hui
---
dr
Use a proper MEID to make sure the CP_HQD_* and CP_GFX_HQD_* registers
can be touched when initialize the compute and gfx mqd in mes_self_test.
Otherwise, we expect no response from CP and an GRBM eventual timeout.
Signed-off-by: Tim Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 16 +++
Use a proper MEID to make sure the CP_HQD_* and CP_GFX_HQD_* registers
can be touched when initialize the compute and gfx mqd in mes_self_test.
Otherwise, we expect no response from CP and an GRBM eventual timeout.
Signed-off-by: Tim Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 16 +++
Reset error data info stored in vram when user clear eeprom table.
Signed-off-by: Stanley.Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 97 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 2 +
.../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c| 4 +
3 files changed,
Add MP0_C2PMSG_109/126 register field shift/masks
that are used to identify boot status by driver.
Signed-off-by: Hawking Zhang
Reviewed-by: Tao Zhou
Reviewed-by: Yang Wang
Reviewed-by: Le Ma
---
.../include/asic_reg/mp/mp_13_0_2_sh_mask.h | 28 +++
1 file changed, 28 insert
Add psp v13 function to query boot status.
v2: limit the use case to dGPU only (Lijo)
Signed-off-by: Hawking Zhang
Reviewed-by: Tao Zhou
Reviewed-by: Yang Wang
Reviewed-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 15 +
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 3 +
drivers/g
Query boot status and report boot errors. A follow
up change is needed to stop GPU initialization if boot
fails.
v2: only invoke the call for dGPU (Le/Lijo)
Signed-off-by: Hawking Zhang
Reviewed-by: Tao Zhou
Reviewed-by: Yang Wang
Reviewed-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_devi
On Wed, Nov 1, 2023 at 5:02 AM Tim Huang wrote:
>
> Use a proper MEID to make sure the CP_HQD_* and CP_GFX_HQD_* registers
> can be touched when initialize the compute and gfx mqd in mes_self_test.
> Otherwise, we expect no response from CP and an GRBM eventual timeout.
>
> Signed-off-by: Tim Huan
- Enable the seq64 mapping sequence.
- Fix wflinfo va conflict and other bugs.
v1:
- The seq64 area needs to be included in the AMDGPU_VA_RESERVED_SIZE
otherwise the areas will conflict with user space allocations (Alex)
- It needs to be mapped read only in the user VM (Alex)
v2:
- Ins
Replace seq64 bo lock sequences with drm_exec.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c | 73 ++-
1 file changed, 33 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_se
On 2023-10-17 17:13, Felix Kuehling wrote:
Let amdgpu_vm_handle_moved update all BO VA mappings of BOs reserved by
the caller. This will be useful for handling extra BO VA mappings in
KFD VMs that are managed through the render node API.
Signed-off-by: Felix Kuehling
Reviewed-by: Christian Köni
Hi Christian,
On 10/30/2023 9:34 PM, Christian König wrote:
Am 30.10.23 um 13:22 schrieb Arunpravin Paneer Selvam:
If the size returned by drm buddy allocator is higher than
the required size, we take the higher size to calculate
the buffer start address. This is required if we couldn't
trim
This was fixed in PMFW before launch and is no longer
required.
Signed-off-by: Alex Deucher
---
.../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 32 ++-
1 file changed, 2 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
b/drivers/g
Title: DC Patches October 30, 2023
Start from:
9379d9fc18582c69862dc25fb770ae2e102f29d6
drm/amd/display: 3.2.258
Stopped at:
0a6aa88e926196036c7cf9edb70924b659461617
drm/amd/display: 3.2.259
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- Enable DCN35
From: Alvin Lee
[Description]
- Similar to FPO, SubVP should also force cursor P-State
allow instead of relying on natural assertion
- Implement code path to force and unforce cursor P-State
allow for SubVP
Reviewed-by: Samson Tam
Acked-by: Hersen Wu
Signed-off-by: Alvin Lee
---
.../drm/
From: Daniel Miess
[Why]
DCN clock gating enablement is preventing light up on
high resolution DSC display
[How]
This reverts commit 933b6692d58671e47dff15b77abe69ccb4891298.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Hersen Wu
Signed-off-by: Daniel Miess
---
drivers/gpu/drm/amd/display/dc/
From: Wenjing Liu
[why]
There is a case when we are switching from ODM combine to Subvp where
minimal transition based off subvp state is required. In thise case, we
need to save and restore mall state when applying minimal transition.
Reviewed-by: Dillon Varone
Acked-by: Hersen Wu
Signed-off-
From: Rodrigo Siqueira
For all the components that participate in DCN architecture, there is a
header in the dc/inch/hw. For some reason, OPTC broke this pattern and
added all the primary functions/structs associated with that in the
dcn10_optc.h file. For consistency's sake, this commit introduc
From: Sung Joon Kim
This reverts commit 2b30049e735fce887108ed4d01726c4daf69ed3d
Reviewed-by: Aric Cyr
Acked-by: Hersen Wu
Signed-off-by: Sung Joon Kim
Signed-off-by: Hersen Wu
---
.../display/dc/dml2/dml2_dc_resource_mgmt.c | 45 ---
.../amd/display/dc/dml2/dml2_internal_types.h
From: Chaitanya Dhere
Clean-up the code to remove references of all unused
dml architecture versions since only dml2 is actively
used.
Reviewed-by: Jun Lei
Acked-by: Hersen Wu
Signed-off-by: Chaitanya Dhere
Signed-off-by: Hersen Wu
---
.../amd/display/dc/dml2/dml2_dc_resource_mgmt.c | 16 +
From: Ovidiu Bunea
[why]
Doing a mode timing change causes a hang when OTG is not disabled.
[how]
Add link_enc null check in disable_otg_wa to cover this case.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Hersen Wu
Signed-off-by: Ovidiu Bunea
Signed-off-by: Hersen Wu
---
drivers/gpu/drm/amd/
From: Joshua Aberback
[Why]
DCN32 uses ABM register definitions in dcn32_resource.h, remove
duplicate from dce_abm.h to avoid confusion.
Reviewed-by: Dillon Varone
Acked-by: Hersen Wu
Signed-off-by: Joshua Aberback
Signed-off-by: Hersen Wu
---
drivers/gpu/drm/amd/display/dc/dce/dce_abm.h |
From: Aric Cyr
Acked-by: Hersen Wu
Signed-off-by: Aric Cyr
Summary:
- Enable DCN35 physymclk root clock gating
- Fix DP automation test pattern bug
- Disable OTG for mode switch from TMDS to FRL
- Refactor DML2
- Revert Fix handling duplicate planes on one stream
- Revert Enable DCN clock gat
From: Daniel Miess
[Why]
Enable the last of the RCO options for dcn35
[How]
Breakout RCO from dccg35_set_physymclk so that
physymclk RCO can be set in dccg_init without
disabling physymclk
Reviewed-by: Nicholas Kazlauskas
Reviewed-by: Jun Lei
Acked-by: Hersen Wu
Signed-off-by: Daniel Miess
From: George Shen
[Why]
A recent refactor of DC's DP test pattern automation code requires the
DC stream's test pattern and test pattern color space fields to be
correctly populated before calling dc_link_dp_set_test_pattern.
[How]
Populate stream's test pattern type and color space fields befor
From: Sung Joon Kim
[why]
DML2 does not handle the case when we have
a single stream sourcing 2 or more planes
that are duplicates of one another. To properly
handle this scenario, pipe index to plane index
mapping is used to decide which plane is being
processed and programmed.
[how]
Create sta
Without this fix the 5120x1440@240 timing of these monitors
leads to screen flickering.
Cc: sta...@vger.kernel.org # 6.1+
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1442
Co-developed-by: Harry Wentland
Signed-off-by: Harry Wentland
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/dr
On Wed, Nov 1, 2023 at 5:01 PM Hamza Mahfooz wrote:
>
> Without this fix the 5120x1440@240 timing of these monitors
> leads to screen flickering.
>
> Cc: sta...@vger.kernel.org # 6.1+
> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1442
> Co-developed-by: Harry Wentland
> Signed-off-by: H
On 2023-10-31 11:18, Alex Deucher wrote:
On Tue, Oct 31, 2023 at 11:12 AM Christian König
wrote:
When clearing the root PD fails we need to properly release it again.
Signed-off-by: Christian König
Acked-by: Alex Deucher
Has this been submitted? I see some intermittent failures in the PSDB
[AMD Official Use Only - General]
Reviewed-by: Yang Wang
Best Regards,
Kevin
From: amd-gfx on behalf of Alex Deucher
Sent: Thursday, November 2, 2023 03:50
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu/smu13: drop compu
ping...
Regards,
Ma Jun
On 11/1/2023 11:04 AM, Ma Jun wrote:
> Use a new struct array to define the asic information which
> asic type needs to be fixed.
>
> Signed-off-by: Ma Jun
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 35 ++---
> include/drm/amd_asic_type.h
[AMD Official Use Only - General]
Reviewed-by: Kenneth Feng
-Original Message-
From: Ma, Jun
Sent: Thursday, November 2, 2023 8:58 AM
To: Ma, Jun ; amd-gfx@lists.freedesktop.org; Feng, Kenneth
; Deucher, Alexander
Cc: Ma, Jun
Subject: Re: [PATCH v2 1/2] drm/amdgpu: Optimize the asic
On 10/31/ , Christian König wrote:
> Am 31.10.23 um 14:59 schrieb Bas Nieuwenhuizen:
> >
> >
> > On Tue, Oct 31, 2023 at 2:57 PM Christian König
> > wrote:
> >
> > Am 31.10.23 um 14:40 schrieb Tatsuyuki Ishi:
> > > The current amdgpu_gem_va_update_vm only tries to perform
> > update
On 10/5/23 18:15, Melissa Wen wrote:
Add 3D LUT property for plane color transformations using a 3D lookup
table. 3D LUT allows for highly accurate and complex color
transformations and is suitable to adjust the balance between color
channels. It's also more complex to manage and require more
Otherwise we can end up with a frame on unsuspend where color management
is not applied when userspace has not committed themselves.
Fixes re-applying color management on Steam Deck/Gamescope on S3 resume.
Signed-off-by: Joshua Ashton
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
Am 02.11.23 um 03:36 schrieb Lang Yu:
On 10/31/ , Christian König wrote:
Am 31.10.23 um 14:59 schrieb Bas Nieuwenhuizen:
On Tue, Oct 31, 2023 at 2:57 PM Christian König
wrote:
Am 31.10.23 um 14:40 schrieb Tatsuyuki Ishi:
> The current amdgpu_gem_va_update_vm only tries to perform
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