Fix warnings reported by kernel test bot/smatch
smatch warnings:
drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c:65 amdgpu_xcp_run_transition()
error: buffer overflow 'xcp_mgr->xcp' 8 <= 8
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Closes: https://lore.kernel.org/r/202305231453.i0bxngyn-
From: Arnd Bergmann
The .resync_fifo_dccg_dio() callback pointer was added in an #ifdef block,
but is called unconditionally:
drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:2292:31:
error: 'struct hwseq_private_funcs' has no member named 'resync_fifo_dccg_dio'
Add the sa
./drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c: amdgpu_xcp.h is included more than
once.
Reported-by: Abaci Robot
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=5281
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/dri
No functional modification involved.
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c:374: warning: expecting prototype for
vcn_v4_0_mc_resume_dpg_mode(). Prototype was for
vcn_v4_0_3_mc_resume_dpg_mode() instead.
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c:631: warning: expecting prototype for
vcn_v4_0_ena
No functional modification involved.
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c:426: warning: expecting prototype for
sdma_v4_4_2_gfx_stop(). Prototype was for sdma_v4_4_2_inst_gfx_stop() instead.
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c:457: warning: expecting prototype for
sdma_v4_4_2_rlc_stop()
On Tue, May 23, 2023 at 12:02:32PM +0800, Shiwu Zhang wrote:
> + { PCI_DEVICE(0x1002, PCI_ANY_ID),
> + .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8,
> + .class_mask = 0xff,
> + .driver_data = CHIP_IP_DISCOVERY },
Probing for every single device of a given class for a si
Below two functions cause a warning because they lack a prototype:
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c:904:13: warning: no previous prototype
for ‘amdgpu_acpi_get_node_id’ [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c:930:30: warning: no previous prototype
for ‘amdgpu_acpi
[AMD Official Use Only - General]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Lijo Lazar
Sent: Tuesday, May 23, 2023 16:00
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Dan Carpenter
; kernel test robot ; Zhang, Hawking
Subje
Hi,
On 17/05/23 5:07 pm, Tom Chung wrote:
From: Aurabindo Pillai
[Why&How]
Change how DC version and hardware version is printed when driver is
loaded.
- Remove exclamation
- Add DC version and hardware version to both success and failure cases
- Add version in between appropriate filler word
gcc with W=1 reports
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:1069:43: error:
‘res_create_maximus_funcs’ defined but not used
[-Werror=unused-const-variable=]
1069 | static const struct resource_create_funcs res_create_maximus_funcs = {
|
Redirect xcp allocated drm_device::rdev/pdev/driver with
amdgpu pci_device/drm_device setting. They need be saved
before redirect and restored after unregister xcp drm_device.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 16 ++--
drivers/gpu/drm/amd/amdgpu/a
Add platform device driver for amdxcp to support
amdgpu spatial partition.
Signed-off-by: James Zhu
---
drivers/gpu/drm/Makefile| 1 +
drivers/gpu/drm/amd/amdxcp/Makefile | 25 +
drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c | 108
drivers/gp
Use amdxcp platform device as spatial partition device.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 12 ++--
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
On Tue, May 23, 2023 at 6:17 AM Srinivasan Shanmugam
wrote:
>
> Below two functions cause a warning because they lack a prototype:
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c:904:13: warning: no previous
> prototype for ‘amdgpu_acpi_get_node_id’ [-Wmissing-prototypes]
> drivers/gpu/drm/amd/amdgp
On Tue, May 23, 2023 at 5:25 AM Christoph Hellwig wrote:
>
> On Tue, May 23, 2023 at 12:02:32PM +0800, Shiwu Zhang wrote:
> > + { PCI_DEVICE(0x1002, PCI_ANY_ID),
> > + .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8,
> > + .class_mask = 0xff,
> > + .driver_data = CHIP_IP_D
On 5/23/23 07:49, Tom Rix wrote:
gcc with W=1 reports
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:1069:43: error:
‘res_create_maximus_funcs’ defined but not used
[-Werror=unused-const-variable=]
1069 | static const struct resource_create_funcs res_create_maximus_funcs =
On 5/23/23 04:34, Arnd Bergmann wrote:
From: Arnd Bergmann
The .resync_fifo_dccg_dio() callback pointer was added in an #ifdef block,
but is called unconditionally:
drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:2292:31:
error: 'struct hwseq_private_funcs' has no member
[AMD Official Use Only - General]
Reviewed-by: Alex Deucher
From: Huang, Tim
Sent: Tuesday, May 23, 2023 1:02 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
; Huang, Tim
Subject: [PATCH] drm/amd/pm: reverse mclk and fclk clocks leve
Reviewed-by: Aurabindo Pillai
On 5/22/23 09:08, Michel Dänzer wrote:
> From: Michel Dänzer
>
> This reverts commit 474f01015ffdb74e01c2eb3584a2822c64e7b2be.
>
> Caused a regression:
>
> Samsung Odyssey Neo G9, running at 5120x1440@240/VRR, connected to Navi
> 21 via DisplayPort, blanks and th
Acked-by: Alex Deucher
for the series.
Jay, I assume you or Hamza will pick these up?
Thanks,
Alex
On Tue, May 23, 2023 at 11:31 AM Aurabindo Pillai
wrote:
>
> Reviewed-by: Aurabindo Pillai
>
> On 5/22/23 09:08, Michel Dänzer wrote:
> > From: Michel Dänzer
> >
> > This reverts commit 474f01
Series is:
Acked-by: Alex Deucher
On Tue, May 23, 2023 at 9:29 AM James Zhu wrote:
>
> Use amdxcp platform device as spatial partition device.
>
> Signed-off-by: James Zhu
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 12 ++--
> 2
Applied. Thanks!
On Mon, May 22, 2023 at 10:18 PM Jiapeng Chong
wrote:
>
> ./drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c: amdgpu_xcp.h is included more than
> once.
>
> Reported-by: Abaci Robot
> Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=5281
> Signed-off-by: Jiapeng Chong
> ---
> dri
Applied. Thanks!
On Mon, May 22, 2023 at 11:17 PM Jiapeng Chong
wrote:
>
> No functional modification involved.
>
> drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c:426: warning: expecting prototype
> for sdma_v4_4_2_gfx_stop(). Prototype was for sdma_v4_4_2_inst_gfx_stop()
> instead.
> drivers/gpu/dr
Applied. Thanks!
Alex
On Mon, May 22, 2023 at 11:32 PM Jiapeng Chong
wrote:
>
> No functional modification involved.
>
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c:374: warning: expecting prototype for
> vcn_v4_0_mc_resume_dpg_mode(). Prototype was for
> vcn_v4_0_3_mc_resume_dpg_mode() instead.
[AMD Official Use Only - General]
Yep, we shall, thanks Alex.
--
Regards,
Jay
From: Alex Deucher
Sent: Tuesday, May 23, 2023 11:47 AM
To: Pillai, Aurabindo ; Mahfooz, Hamza
Cc: Michel Dänzer ; Deucher, Alexander
; Chalmers, Wesley ; Li,
Sun peng (Leo) ; Zhuo
On 5/22/23 09:08, Michel Dänzer wrote:
From: Michel Dänzer
This reverts commit ce560ac40272a5c8b5b68a9d63a75edd9e66aed2.
It depends on its parent commit, which we want to revert.
Signed-off-by: Michel Dänzer
I have applied the series, thanks!
---
.../drm/amd/display/dc/dcn20/dcn20_hwse
Fix the warning during driver load because the event
interrupt class is not set for GFX9.4.3.
Signed-off-by: Mukul Joshi
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_devic
[AMD Official Use Only - General]
Acked-by: Alex Deucher
From: Joshi, Mukul
Sent: Tuesday, May 23, 2023 2:12 PM
To: amd-gfx@lists.freedesktop.org
Cc: Kuehling, Felix ; Deucher, Alexander
; Joshi, Mukul
Subject: [PATCH] drm/amdkfd: Set event interrupt class for
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c: In function ‘amdgpu_gfx_disable_kcq’:
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:497:6: warning: variable ‘j’ set but
not used [-Wunused-but-set-variable]
497 | int j;
| ^
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c: In function ‘amdgpu_gfx_disable_k
On Tue, May 23, 2023 at 2:31 PM Srinivasan Shanmugam
wrote:
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c: In function ‘amdgpu_gfx_disable_kcq’:
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:497:6: warning: variable ‘j’ set but
> not used [-Wunused-but-set-variable]
> 497 | int j;
> | ^
>
Hi Felix,
On 5/21/2023 12:09 AM, Felix Kuehling wrote:
Am 2023-05-20 um 05:25 schrieb Arunpravin Paneer Selvam:
This reverts commit c105518679b6e87232874ffc989ec403bee59664.
This patch disables the TOPDOWN flag for APU and few dGPU cards
which has the VRAM size equal to the BAR size.
With re
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c: In function ‘amdgpu_gfx_disable_kcq’:
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:497:6: warning: variable ‘j’ set but
not used [-Wunused-but-set-variable]
497 | int j;
| ^
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c: In function ‘amdgpu_gfx_disable_k
Am 22.05.23 um 20:46 schrieb Thomas Zimmermann:
[...]
Looking at this patch makes me wonder if we should have implemented
fb_dirty for the MSM driver. We have drm_framebuffer_funcs::dirty()
implemented (by wrapping the drm_atomic_helper_dirtyfb()).
I think so. You'd need something similar to
Reviewed-by: Alex Deucher
On Tue, May 23, 2023 at 3:07 PM Srinivasan Shanmugam
wrote:
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c: In function ‘amdgpu_gfx_disable_kcq’:
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:497:6: warning: variable ‘j’ set but
> not used [-Wunused-but-set-variable]
> 497
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
WARNING: braces {} are not necessary for any arm of this statement
+ if (nvec <= 0) {
[...]
+ } else {
[...]
WARNING: Block comments use a trailing */ on a separate line
Cc: Christian König
Cc: Alex Deucher
Sign
Reviewed-by: Alex Deucher
On Tue, May 23, 2023 at 3:51 PM Srinivasan Shanmugam
wrote:
>
> WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
> WARNING: braces {} are not necessary for any arm of this statement
> + if (nvec <= 0) {
> [...]
> + } else {
> [...]
>
tree/branch: INFO setup_repo_specs:
/db/releases/20230524001904/lkp-src/repo/*/linux-next
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 9f925874281f7e8855855d6210d6e29d844e4307 Add linux-next specific
files for 20230523
Error/Warning reports:
https
Place it in drm_property where drm_property_replace_blob and
drm_property_lookup_blob live. Then we can use the DRM helper for
driver-specific KMS properties too.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/arm/malidp_crtc.c | 2 +-
drivers/gpu/drm/drm_atomic_uapi.c | 43
DRM_OBJECT_MAX_PROPERTY limits the number of properties to be attached
and we are increasing that value all time we add a new property (generic
or driver-specific).
In this series, we are adding 13 new KMS driver-specific properties for
AMD color manage:
- CRTC Gamma enumerated Transfer Function
-
This series is a refined version of our RFC [1] for AMD driver-specific
color management properties. It is a collection of contributions from
Joshua, Harry and I to enhance AMD KMS color pipeline for Steam
Deck/SteamOS by exposing the large set of color caps available in AMD
display HW.
Considerin
From: Harry Wentland
The region and segment calculation was incapable of dealing
with regions of more than 16 segments. We first fix this.
Now that we can support regions up to 256 elements we can
define a better segment distribution for near-linear LUTs
for our maximum of 256 HW-supported point
We will add color mgmt properties to DRM planes in the next patches and
we want to track when one of this properties change to define atomic
commit behaviors. Using a similar approach from CRTC color props, we set
a color_mgmt_changed boolean whenever a plane color prop changes.
Signed-off-by: Mel
Hook up driver-specific atomic operations for managing AMD color
properties and create AMD driver-specific color management properties
and attach them according to HW capabilities defined by `struct
dc_color_caps`. Add enumerated transfer function property to DRM CRTC
gamma to convert to wire encod
From: Harry Wentland
The shaper LUT requires a 10-bit value of the delta between
segments. We were using dc_fixpt_clamp_u0d10() to do that
but it doesn't do what we want it to do. It will preserve
10-bit precision after the decimal point, but that's not
quite what we want. We want 14-bit precisio
Add 3D LUT property for plane gamma correction using a 3D lookup table.
Since a 3D LUT has a limited number of entries in each dimension we want
to use them in an optimal fashion. This means using the 3D LUT in a
colorspace that is optimized for human vision, such as sRGB, PQ, or
another non-linear
From: Joshua Ashton
Multiplier to 'gain' the plane. When PQ is decoded using the fixed func
transfer function to the internal FP16 fb, 1.0 -> 80 nits (on AMD at
least) When sRGB is decoded, 1.0 -> 1.0. Therefore, 1.0 multiplier = 80
nits for SDR content. So if you want, 203 nits for SDR content,
On AMD HW, 3D LUT always assumes a preceding shaper 1D LUT used for
delinearizing and/or normalizing the color space before applying a 3D
LUT.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14 +
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 10 +
From: Joshua Ashton
Blend 1D LUT or a predefined transfer function can be set to linearize
content before blending, so that it's positioned just before blending
planes in the AMD color mgmt pipeline, and after 3D LUT (non-linear
space). Shaper and Blend LUTs are 1D LUTs that sandwich 3D LUT. Driv
Describe some expected behavior of the AMD DM color mgmt programming.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/dr
From: Joshua Ashton
Allow userspace to tell the kernel driver the input space and,
therefore, uses correct predefined transfer function (TF) to delinearize
content with or without LUT.
Signed-off-by: Joshua Ashton
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/am
HW allows us to program shaper LUT without 3D LUT settings and it is
also good for testing shaper LUT behavior, therefore, DC driver should
allow acquiring both 3D and shaper LUT, but programing shaper LUT
without 3D LUT (not initialized).
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/displ
From: Joshua Ashton
When commiting planes, we copy color mgmt resources to the stream state.
Do the same for shaper and 3D LUTs.
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
Signed-off-by: Joshua Ashton
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4
1 file changed
Create and attach driver-private properties for plane color management.
First add plane degamma LUT properties that means user-blob and its
size. We will add more plane color properties in the next commits. In
addition, we keep these driver-private plane properties limited by
defining AMD_PRIVATE_C
We will wire up MPC 3D LUT to DM CRTC color pipeline in the next patch,
but so far, only for atomic interface. By checking
set_output_transfer_func in DC drivers with MPC 3D LUT support, we can
verify that regamma is only programmed when 3D LUT programming fails. As
a groundwork to introduce 3D LUT
Add property to set predefined transfer function to enable delinearizing
content with or without shaper LUT. Drivers should advertize this
property acoording to HW caps.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 +
drivers/gpu/drm/amd/amdgpu
In the original dc_acquire_release_mpc_3dlut(), only current ctx is
considered, which doesn't fit the steps for atomic checking new ctx.
Therefore, create a function to handle 3D LUT resource for a given
context, so that we can check resources availability in atomic_check
time and handle failures p
From: Joshua Ashton
dc_acquire_release_mpc_3dlut_for_ctx initializes the bits required to
program 3DLUT in DC MPC hw block, applied in set_output_transfer_func().
Since acquire/release can fail, we should check resources availability
during atomic check considering the new context created. We dyn
From: Joshua Ashton
Add predefined transfer function programming. There is no out gamma ROM,
but we can use AMD color modules to program LUT parameters from a
predefined TF and an empty regamma LUT (or bump up LUT parameters with
predefined TF setup).
Signed-off-by: Joshua Ashton
Signed-off-by:
From: Joshua Ashton
Otherwise this is just initialized to 0. This needs to actually have a
value so that compute_curve can work for PQ EOTF.
Signed-off-by: Joshua Ashton
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 2 ++
Wire up DC 3D LUT to DM CRTC color management (post-blending). On AMD
display HW, we have to set a shaper LUT to delinearize or normalize the
color space before applying a 3D LUT (since we have a reduced number of
LUT entries). Therefore, we map DC shaper LUT to DM CRTC color mgmt in
the next patch
Map DC shaper LUT to DM CRTC color management. Shaper LUT can be used to
delinearize and/or normalize the color space for computational
efficiency and achiving specific visual styles. Blending usually occurs
in linear space and if a CRTC degamma 1D LUT is set to linearize the
color space, a custom
It follows the same path of out_transfer_func for stream updates, since
shaper LUT and 3D LUT is programmed in funcs.set_output_transfer_func()
and this function is called in the atomic commit_tail when
update_flags.bits.out_tf is set.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/d
Inspired by regamma TF, follow similar steps to add TF + 1D LUT for
shaper func. Reuse regamma_tf property, since the driver doesn't support
shaper and out gamma at the same time. Only set shaper TF if setting
shaper LUT or 3D LUT. We could rename regamma_tf - if necessary to avoid
misunderstanding
DC only has pre-blending degamma caps (plane/DPP) that is currently in
use for CRTC/post-blending degamma, so that we don't have HW caps to
perform plane and CRTC degamma at the same time. Reject atomic updates
when serspace sets both plane and CRTC degamma properties.
Signed-off-by: Melissa Wen
From: Joshua Ashton
Set DC plane with user degamma LUT or predefined TF from driver-specific
plane color properties. If plane and CRTC degamma are set in the same
time, plane degamma has priority. That means, we only set CRTC degamma
if we don't have plane degamma LUT or TF to configure. We retu
The next patch adds pre-blending degamma to AMD color mgmt pipeline, but
pre-blending degamma caps (DPP) is currently in use to provide DRM CRTC
atomic degamma or implict degamma on legacy gamma. Detach degamma usage
regarging CRTC color properties to manage plane and CRTC color
correction combinat
From: Joshua Ashton
With `dc_fixpt_from_s3132()` translation, we can just use it to set
hdr_mult.
Signed-off-by: Joshua Ashton
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 3 +++
2 files
We already have the steps to program post-blending shaper/3D LUT on AMD
display driver, but unlike MPC 3D LUT, we don't need to acquire/release
DPP 3D LUT. We can reuse programming steps to map plane properties to
DC plane for pre-blending (plane) shaper/3D LUT setup.
Signed-off-by: Melissa Wen
-
From: Joshua Ashton
Unlike degamma, blend gamma doesn't support hardcoded curve
(predefined/ROM), but we can use AMD color module to fill blend gamma
parameters when we have non-linear plane gamma TF without plane gamma
LUT. The regular degamma path doesn't hit this.
Signed-off-by: Joshua Ashton
From: Joshua Ashton
Detach value translation from CTM to reuse it for programming HDR
multiplier property.
Signed-off-by: Joshua Ashton
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 8 +---
drivers/gpu/drm/amd/display/include/fixed31_32.h | 12
From: Joshua Ashton
Need to funnel the color caps through to these functions so it can check
that the hardware is capable.
Signed-off-by: Joshua Ashton
Signed-off-by: Melissa Wen
---
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 35 ---
1 file changed, 23 insertions(+), 12 d
From: Joshua Ashton
Map DRM plane blend properties to DPP blend gamma. Plane blend is a
post-3D LUT curve that linearizes color space for blending. It may be
defined by a user-blob LUT and/or predefined transfer function. As
hardcoded curve (ROM) is not supported on blend gamma, we use AMD color
If shaper and 3D LUT data updates, lut_3d bit in update_flag is updated
and we need to call set_input_transfer_func to program DPP shaper and 3D
LUTs. Small cleanup of code style in the related if-condition.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 5 ++
We took a similar path for CRTC color mgmt changes, since we remap CRTC
degamma to plane/DPP block. Here we can use the status of
`plane->color_mgmt_changed` to detect when a plane color property
changed and recreate the plane accordingly.
Co-developed-by: Joshua Ashton
Signed-off-by: Joshua Asht
Reviewed-by: Simon Ser
On Mon, May 22, 2023 at 12:12 PM Christian König
wrote:
>
> Am 21.05.23 um 20:49 schrieb Chia-I Wu:
> > On Thu, May 18, 2023 at 1:12 PM Alex Deucher wrote:
> >> On Wed, May 17, 2023 at 5:27 PM Chia-I Wu wrote:
> >>> On Tue, May 9, 2023 at 11:33 AM Chia-I Wu wrote:
> Extend the address and
Validate drm_amdgpu_gem_va addrs in amdgpu_gem_va_ioctl.
amdgpu_vm_bo_replace_map no longer needs to validate (and its
validations were insufficient either). amdgpu_vm_bo_map has internal
users and its validations are kept.
This is motivated by OOB access in amdgpu_vm_update_range when
offset_in_
[Public]
This patch did not land at all? Well, please add your SOB in commit message,
and I will push it to amd-staging-drm-next branch with my RB.
Regards,
Guchun
> -Original Message-
> From: Zhenneng Li
> Sent: Wednesday, May 24, 2023 9:10 AM
> To: Chen, Guchun
> Cc: Deucher, Alexan
From: Jiadong Zhu
When MEC executes unmap_queue for mid command buffer preemption, it will
kick the write pointer of the gfx ring, set CP_VMID_PREEMPT to trigger the
preemption and wait for CP_VMID_PREEMPT becomes zero after the preemption
done. There is a race condition that PFP may excute the r
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