[AMD Official Use Only - General]
Hi Peter,
Thank you for your review.
The purpose of the patch set is to improve the performance when playing game
for some AMD APUs with SMT enabled/disabled.
When change the SMT state on the fly through " echo on/off >
/sys/devices/system/cpu/smt/control", t
[AMD Official Use Only - General]
> -Original Message-
> From: Lazar, Lijo
> Sent: Wednesday, March 29, 2023 2:15 PM
> To: Yang, WenYou ; Deucher, Alexander
> ; Koenig, Christian
> ; Pan, Xinhui ; Quan, Evan
> ; Limonciello, Mario ;
> b...@suse.de; pet...@infradead.org; jpoim...@kernel.
[AMD Official Use Only - General]
> -Original Message-
> From: Limonciello, Mario
> Sent: Wednesday, March 29, 2023 12:18 PM
> To: Yang, WenYou ; Deucher, Alexander
> ; Koenig, Christian
> ; Pan, Xinhui ; Quan, Evan
> ; b...@suse.de; pet...@infradead.org;
> jpoim...@kernel.org; Phillips
There is a mixup where AMDGPU_RAS_BLOCK__DF is used as a mask instead of
a shifter. It means that this condition will be true for
AMDGPU_RAS_BLOCK__MMHUB instead of for AMDGPU_RAS_BLOCK__DF.
Fixes: b6f512168478 ("drm/amdgpu: Add fatal error handling in nbio v4_3")
Signed-off-by: Dan Carpenter
--
On Wed, Mar 29, 2023 at 09:51:48AM +0800, Wenyou Yang wrote:
> Add the notifier chain to notify the cpu SMT status changes
>
Why!?!? What's the purpose of all this? IIRC this doesn't trigger if you
manually disable all the siblings. And because you didn't tell us why
you need this I can't tell yo
[AMD Official Use Only - General]
> -Original Message-
> From: Peter Zijlstra
> Sent: Wednesday, March 29, 2023 4:50 PM
> To: Yang, WenYou
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Pan, Xinhui ; Quan, Evan
> ; Limonciello, Mario ;
> b...@alien8.de; jpoim...@kernel.org; Phillips,
[Why]
Need dequeue MES KIQ under SRIOV when unloading driver
[How]
Modify mes_v11_0_kiq_dequeue_sched which was used to dequeue MES SCHED
to support veriable pipe.
Add MES KIQ dequeue in hw fini
Signed-off-by: Yifan Zha
---
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 17 +++--
1 file c
[Why]
As MES KIQ is dequeued, tell RLC that KIQ is inactive
[How]
Clear the RLC_CP_SCHEDULERS Active bit which RLC checks KIQ status
In addition, driver can halt MES under SRIOV when unloading driver
Signed-off-by: Yifan Zha
---
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 16 ++--
1 fi
To avoid new mes fw running with old driver, rename
mes schq fw to gc_*_mes_2.bin.
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 26 +
1 file changed, 22 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
b/driver
User can check pp_dpm_vclk1 and pp_dpm_dclk1 for DPM frequency of
vcn and dcn
Signed-off-by: Tong Liu01
---
.../gpu/drm/amd/include/kgd_pp_interface.h| 2 ++
drivers/gpu/drm/amd/pm/amdgpu_pm.c| 32 +++
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 8 +
3 f
Enable vclk1 and dclk1 node for gc10.3.0 and gc10.3.1
Signed-off-by: Tong Liu01
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 9991447b5f14..ea8e5e3829dd 100644
---
Enable node pp_dpm_vclk1 and pp_dpm_dclk1 for gc11.0.2 and gc11.0.3
Signed-off-by: Tong Liu01
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index ea8e5e38
Series is,
Acked-by: Luben Tuikov
Regards,
Luben
On 2023-03-29 06:51, Tong Liu01 wrote:
> User can check pp_dpm_vclk1 and pp_dpm_dclk1 for DPM frequency of
> vcn and dcn
>
> Signed-off-by: Tong Liu01
> ---
> .../gpu/drm/amd/include/kgd_pp_interface.h| 2 ++
> drivers/gpu/drm/amd/pm/amdg
Since the original issue is resolved by a new fix, the ASPM workaround
can be dropped.
Signed-off-by: Kai-Heng Feng
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 15 ---
drivers/gpu/drm/amd/amdgpu/nv.c| 2 +-
drivers/
When the power is lost due to ACPI power resources being turned off, the
driver should reset the GPU so it can work anew.
First, _PR3 support of the hierarchy needs to be found correctly. Since
the GPU on some discrete GFX cards is behind a PCIe switch, checking the
_PR3 on downstream port alone i
On Wed, Mar 29, 2023 at 07:23:29AM +, Yang, WenYou wrote:
> [AMD Official Use Only - General]
^^^ that has no business being in a public email.
> Hi Peter,
>
> Thank you for your review.
>
> The purpose of the patch set is to improve the performance when playing game
> for some AMD APUs wi
On 3/29/2023 4:59 AM, Kai-Heng Feng wrote:
Since the original issue is resolved by a new fix, the ASPM workaround
can be dropped.
What is the new fix? Can you elaborate more or add the new fix commit here?
Signed-off-by: Kai-Heng Feng
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 -
On Wed, Mar 29, 2023 at 6:11 AM Jack Xiao wrote:
>
> To avoid new mes fw running with old driver, rename
> mes schq fw to gc_*_mes_2.bin.
>
> Signed-off-by: Jack Xiao
Please add the necessary MODULE_FIRMWARE() declaration as well. With
that, the patch is:
Reviewed-by: Alex Deucher
> ---
> dr
On 3/29/23 08:08, Gong, Richard wrote:
On 3/29/2023 4:59 AM, Kai-Heng Feng wrote:
Since the original issue is resolved by a new fix, the ASPM workaround
can be dropped.
What is the new fix? Can you elaborate more or add the new fix commit
here?
It's his first patch in the series, but yes I
On Wed, Mar 29, 2023 at 6:00 AM Kai-Heng Feng
wrote:
>
> When the power is lost due to ACPI power resources being turned off, the
> driver should reset the GPU so it can work anew.
>
> First, _PR3 support of the hierarchy needs to be found correctly. Since
> the GPU on some discrete GFX cards is b
On 3/29/23 04:59, Kai-Heng Feng wrote:
When the power is lost due to ACPI power resources being turned off, the
driver should reset the GPU so it can work anew.
First, _PR3 support of the hierarchy needs to be found correctly. Since
the GPU on some discrete GFX cards is behind a PCIe switch, c
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 198925fae644b0099b66fac1d972721e6e563b17 Add linux-next specific
files for 20230329
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202303082135.njdx1bij-...@intel.com
https
Use this to determine if we support the new SET_Q_PREEMPTION_MODE
packet.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 ++
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 13 +
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu
Only set the supported flag if we have new enough CP FW.
XXX: don't commit this until the CP FW versions are finalized!
Acked-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/
This patch set allows for FW assisted shadowing on supported
platforms. A new enough CP FW is required. This feature is
required for mid command buffer preemption and proper SR-IOV
support. This also simplifies the UMDs by allowing persistent
hardware state when the command submission executes.
From: Christian König
Add support for submitting the shadow update packet
when submitting an IB. Needed for MCBP on GFX11.
v2: update API for CSA (Alex)
v3: fix ordering; SET_Q_PREEMPTION_MODE most come before COND_EXEC
Add missing check for AMDGPU_CHUNK_ID_CP_GFX_SHADOW in
amdgpu_cs_pa
For GFX11, the UMD needs to allocate some shadow buffers
to be used for preemption. The UMD allocates the buffers
and passes the GPU virtual address to the kernel since the
kernel will program the packet that specified these
addresses as part of its IB submission frame.
v2: UMD passes shadow init
Use the new callback to fetch the data. Return an error if
not supported. UMDs should use this query to check whether
shadow buffers are supported and if so what size they
should be.
v2: return an error rather than a zerod structure.
v3: drop GDS, move into dev_info structure. Data will be
Used to get the size and alignment requirements for
the gfx shadow buffer for preemption.
v2: use FW version check to determine whether to
return a valid size here
return an error if not supported (Alex)
v3: drop GDS (Alex)
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_
To provide IP specific shadow sizes. UMDs will use
this to query the kernel driver for the size of the
shadow buffers.
v2: make callback return an int (Alex)
v3: drop GDS (Alex)
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 10 ++
1 file changed, 10 insertio
Provide a debugfs interface to access the MQD. Useful for
debugging issues with the CP and MES hardware scheduler.
v2: fix missing unreserve/unmap when pos >= size (Alex)
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 60 +++
It varies by generation and we need to know the size
to expose this via debugfs.
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/g
Add UAPI to query the GFX shadow buffer requirements
for preemption on GFX11. UMDs need to specify the shadow
areas for preemption.
v2: move into existing asic info query
drop GDS as its use is determined by the UMD (Marek)
v3: Update comments to note that alignment is base
virtual alignm
We need to reset the shadow state every time we submit an
IB and there needs to be a COND_EXEC packet after the
SET_Q_PREEMPTION_MODE packet for it to work properly, so
we should emit both of these packets regardless of whether
there is a job present or not.
Reviewed-by: Christian König
Signed-of
From: Christian König
Add ring callback for gfx to update the CP firmware
with the new shadow information before we process the
IB.
v2: add implementation for new packet (Alex)
v3: add current FW version checks (Alex)
v4: only initialize shadow on first use
Only set IB_VMID when a valid shad
So UMDs can determine whether the kernel supports this.
Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21986
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdg
The doorbells in AMDGPU drivers are currently managed by different
users in a scattered way, across the driver. The existing clients are:
- AMDGPU graphics driver for kernel level doorbell writes.
- AMDGPU MES module for kernel level doorbell write (MES ring test).
- AMDGPU MES modules for kernel l
From: Shashank Sharma
Rename doorbell.num_doorbells to doorbell.num_kernel_doorbells to
make it more readable.
Cc: Alex Deucher
Cc: Christian Koenig
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 22
From: Shashank Sharma
This patch adds double include protection for doorbell.h
Cc: Alex Deucher
Cc: Christian Koenig
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorb
From: Shashank Sharma
This patch:
- creates a new file for doorbell management.
- moves doorbell code from amdgpu_device.c to this file.
Cc: Alex Deucher
Cc: Christian Koenig
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu
From: Shashank Sharma
This patch removes the check and change in num_kernel_doorbells
for MES, which is not being used anywhere by MES code.
Cc: Alex Deucher
Cc: Christian Koenig
Signed-off-by: Shashank Sharma
---
.../gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c | 34 ---
1 file
From: Alex Deucher
This patch adds changes:
- to accommodate the new GEM domain DOORBELL
- to accommodate the new TTM PL DOORBELL
in order to manage doorbell pages as GEM object.
V2: Addressed reviwe comments from Christian
- drop the doorbell changes for pinning/unpinning
- drop the do
From: Shashank Sharma
This patch:
- creates a doorbell page for graphics driver usages.
- removes the adev->doorbell.ptr variable, replaces it with
kernel-doorbell-bo's cpu address.
Cc: Alex Deucher
Cc: Christian Koenig
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_d
From: Alex Deucher
This patch adds flags for a new gem domain AMDGPU_GEM_DOMAIN_DOORBELL
in the UAPI layer.
V2: Drop 'memory' from description (Christian)
Cc: Alex Deucher
Cc: Christian Koenig
Signed-off-by: Alex Deucher
---
include/uapi/drm/amdgpu_drm.h | 7 ++-
1 file changed, 6 inser
From: Shashank Sharma
This patch initialzes the ttm resource manager for doorbells.
Cc: Alex Deucher
Cc: Christian Koenig
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_t
From: Shashank Sharma
This patch adds helper functions to create and free doorbell
pages for kernel objects.
Cc: Alex Deucher
Cc: Christian Koenig
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 41
.../gpu/drm/amd/amdgpu/amdgpu_doorbell_mg
This patch:
- updates start/end values for each of the doorbell object
created.
- adds a function which validates that the kernel doorbell read/write
is within this range.
- uses this function during doorbell writes from kernel.
Cc: Alex Deucher
Cc: Christian Koenig
Signed-off-by: Shashank S
This patch adds a helper function which converts a doorbell's
relative index in a BO to an absolute doorbell offset in the
doorbell BAR.
Cc: Alex Deucher
Cc: Christian Koenig
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 15 +++
.../gpu/drm/amd/amdg
This patch:
- adds a doorbell manager structure in kfd device structure.
- plugs-in doorbell manager APIs for KFD kernel doorbell allocations
an free functions.
- removes the doorbell bitmap, uses the one into the doorbell manager
structure for all the allocations.
- updates the get_kernel_door
This patch:
- adds a new doorbell manager object in kfd pdd structure.
- allocates doorbells for a process while creating its pdd.
- frees the doorbells with pdd destroy.
- uses direct doorbell manager API for doorbell indexing.
- removes previous calls to allocate process doorbells as
its not re
This patch:
- Adds a amdgpu_doorbell object in MES process.
- Allocs doorbell pages for MES process using doorbell manager.
- uses doorbell manager to get an absolute index of doorbells.
- removes a offset calculation function which is no more required.
- removes prototype of a few functions which
This patch removes some variables and functions from KFD
doorbell handling code, which are no more required since
doorbell manager is handling doorbell calculations.
Cc: Alex Deucher
Cc: Christian Koenig
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c | 32
This patch:
- adds a doorbell object in MES structure, to manage the MES
doorbell requirements in kernel.
- Removes the doorbell management code, and its variables from
the doorbell_init function, it will be done in doorbell manager
now.
- creates doorbell pages for MES kernel level needs (do
On 3/28/23 18:09, Caio Novais wrote:
Compiling AMD GPU drivers displays a warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.c:
In function ‘dml_rq_dlg_get_dlg_params’:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.c:991:14:
warni
This patch series introduces AMDGPU usermode queues for gfx workloads.
Usermode queues is a method of GPU workload submission into the graphics
hardware without any interaction with kernel/DRM schedulers. In this
method, a userspace graphics application can create its own workqueue
and submit it di
From: Alex Deucher
This patch intorduces new UAPI/IOCTL for usermode graphics
queue. The userspace app will fill this structure and request
the graphics driver to add a graphics work queue for it. The
output of this UAPI is a queue id.
This UAPI maps the queue into GPU, so the graphics app can s
From: Shashank Sharma
This patch adds:
- A new IOCTL function to create and destroy
- A new structure to keep all the user queue data in one place.
- A function to generate unique index for the queue.
V1: Worked on review comments from RFC patch series:
- Alex: Keep a list of queues, instead o
From: Shashank Sharma
This patch adds skeleton code for amdgpu usermode queue. It contains:
- A new files with init functions of usermode queues.
- A queue context manager in driver private data.
V1: Worked on design review comments from RFC patch series:
(https://patchwork.freedesktop.org/serie
From: Shashank Sharma
A Memory queue descriptor (MQD) of a userqueue defines it in the harware's
context. As MQD format can vary between different graphics IPs, we need gfx
GEN specific handlers to create MQDs.
This patch:
- Introduces MQD hander functions for the usermode queues.
- Adds new fun
From: Shashank Sharma
The FW expects us to allocate atleast one page as context space to
process gang, process, shadow, GDS and FW related work. This patch
creates a joint object for the same, and calculates GPU space offsets
for each of these spaces.
V1: Addressed review comments on RFC patch:
From: Shashank Sharma
This patch adds new functions to map/unmap a usermode queue into
the FW, using the MES ring. As soon as this mapping is done, the
queue would be considered ready to accept the workload.
V1: Addressed review comments from Alex on the RFC patch series
- Map/Unmap should
The userspace sends us the doorbell object and the doobell index
to be used for the usermode queue, but the FW expects the absolute
doorbell index on the PCI BAR in the MQD. This patch adds a function
to convert this relative doorbell index to the absolute doorbell index.
This patch is dependent o
From: Arvind Yadav
To support oversubscription, MES expects WPTR BOs to be mapped
to GART, before they are submitted to usermode queues.
Cc: Alex Deucher
Cc: Christian Koenig
Cc: Shashank Sharma
Signed-off-by: Arvind Yadav
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 89
From: Arvind Yadav
This patch:
- adds some new parameters defined for the gfx usermode queues
use cases in the v11_mqd_struct.
- sets those parametes with the respective allocated gpu context
space addresses.
Cc: Alex Deucher
Cc: Christian Koenig
Cc: Shashank Sharma
Signed-off-by: Arvind
On 3/28/23 18:09, Caio Novais wrote:
Compiling AMD GPU drivers displays a warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_optc.c:294:6: warning: no
previous prototype for ‘optc3_wait_drr_doublebuffer_pending_clear’
[-Wmissing-prototypes]
Get rid of it by adding a function prot
Am 29.03.23 um 18:04 schrieb Shashank Sharma:
From: Alex Deucher
This patch intorduces new UAPI/IOCTL for usermode graphics
queue. The userspace app will fill this structure and request
the graphics driver to add a graphics work queue for it. The
output of this UAPI is a queue id.
This UAPI ma
On Wed, Mar 29, 2023 at 12:05 PM Shashank Sharma
wrote:
>
> From: Alex Deucher
>
> This patch intorduces new UAPI/IOCTL for usermode graphics
> queue. The userspace app will fill this structure and request
> the graphics driver to add a graphics work queue for it. The
> output of this UAPI is a q
This patchset removes one unused variable and mark a function as static.
Caio Novais (2):
drm/amd/display: Remove unused variable 'scl_enable'
drm/amd/display: Mark function
'optc3_wait_drr_doublebuffer_pending_clear' as static
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
Compiling AMD GPU drivers displays a warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.c:
In function ‘dml_rq_dlg_get_dlg_params’:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.c:991:14:
warning: variable ‘scl_enable’ set but not u
Compiling AMD GPU drivers displays a warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_optc.c:294:6: warning: no
previous prototype for ‘optc3_wait_drr_doublebuffer_pending_clear’
[-Wmissing-prototypes]
Get rid of it by marking the function as static
Signed-off-by: Caio Novais
---
On 3/29/23 14:05, Caio Novais wrote:
Compiling AMD GPU drivers displays a warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_optc.c:294:6: warning: no
previous prototype for ‘optc3_wait_drr_doublebuffer_pending_clear’
[-Wmissing-prototypes]
Get rid of it by marking the function as
Hey Alex,
On 29/03/2023 19:57, Alex Deucher wrote:
On Wed, Mar 29, 2023 at 12:05 PM Shashank Sharma
wrote:
From: Alex Deucher
This patch intorduces new UAPI/IOCTL for usermode graphics
queue. The userspace app will fill this structure and request
the graphics driver to add a graphics work qu
On Wed, Mar 29, 2023 at 3:21 PM Shashank Sharma wrote:
>
> Hey Alex,
>
> On 29/03/2023 19:57, Alex Deucher wrote:
> > On Wed, Mar 29, 2023 at 12:05 PM Shashank Sharma
> > wrote:
> >> From: Alex Deucher
> >>
> >> This patch intorduces new UAPI/IOCTL for usermode graphics
> >> queue. The userspace
From: David Belanger
On GC 9.4.3, we are removing the EOP buffer.
If we specify 0 for the size, CP_HQD_EOP_CONTROL ends up with
incorrect value as order_size_2 calculations does not handle 0.
Fix it by using zero for the MQD entry for EOP size 0.
v2: Reworked code with a conditional assignment
From: Jonathan Kim
Similar to GFX9.4.2 non-A+A devices, GFX9.4.3 psp xgmi topology info is
half duplex and requires the driver to fill in the bidirectional info.
Signed-off-by: Jonathan Kim
Reviewed-by: Shiwu Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 11
From: Le Ma
Configure the sdma doorbell settings on NBIF0 and SYSHUB of each AID
v2: fetch aid_id from amdgpu_sdma_instance (Lijo)
Signed-off-by: Le Ma
Acked-by: Felix Kuehling
Reviewed-by: Lijo Lazar
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c | 65 +
From: Lijo Lazar
Add a mask of SDMA instances available for use. On certain ASIC configs,
not all SDMA instances are available for software use.
v2:
Change sdma mask type to uint32_t (Le)
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deuc
From: Mukul Joshi
Currently, even if kfd_locked is set, a process is first
created and then removed to work around a race condition
in updating kfd_locked flag. Rework kfd_locked handling to
ensure no processes is created if kfd_locked is set. This
is achieved by updating kfd_locked under kfd_pro
From: Le Ma
On multiple AIDs platform, bit[34:32] in SMD address is leveraged to access
nonAID0 register smn address and new PCI_INDEX_HI register is introduced
to access the higher bits.
v2: rebase on latest register accessors (Alex)
Signed-off-by: Le Ma
Acked-by: Felix Kuehling
Reviewed-by:
From: Mukul Joshi
GFX9.4.3 will support dynamic repartitioning of the GPU through sysfs.
Add device repartitioning support in KFD to repartition GPU from one
mode to other.
Signed-off-by: Mukul Joshi
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgp
From: Lijo Lazar
Register accesses need to be based on physical instance on bare metal.
Pass the right instance using logical to physical instance lookup
table before accessing registers. Add a macro GET_INST to get the right
physical instance of an IP corresponding to a logical instance.
v2: fi
From: Lijo Lazar
Add a map for logical to physical instances of an IP. For ex: on some device
configurations, the first logical XCC may not be the first physical XCC.
Software may continue to access in logical IP instance order. The map
provides a convenient way to get to the actual physical inst
From: James Zhu
Update vcn doorbell range to support multiple AIDs.
Signed-off-by: James Zhu
Acked-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h | 1 +
drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c | 20 +---
2 files changed, 18 insertions(+
From: Lijo Lazar
It needs to be done only for XCC instances in non-AID0. Use the physical
instance to determine non-AID0 XCC instances.
Signed-off-by: Lijo Lazar
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 9 ++---
1 file changed, 6 insert
From: Lijo Lazar
For ASICs with sdma IP v4.4.2, add mapping for logical to physical
instances.
v2:
Register accesses on bare metal should be based on physical
instance. Use GET_INST() to get physical instance.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Reviewed-by: Le Ma
Si
From: James Zhu
Add JPEG multiple AIDs support.
Signed-off-by: James Zhu
Acked-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 380 ++-
1 file changed, 227 insertions(+), 153 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg
From: James Zhu
Update clock gate setting.
Signed-off-by: James Zhu
Acked-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 30 +
1 file changed, 16 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.
From: James Zhu
add vcn multiple AIDs support.
v2: squash in FW setting fix (Alex)
Signed-off-by: James Zhu
Acked-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 810 +---
1 file changed, 434 insertions(+), 376 deletions(-)
diff --g
From: Lijo Lazar
The packet expects only 16 bits register offset. Hence pass register
offset which is local to each XCC.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 7 ---
1 file changed, 4 insertions(+),
From: Lijo Lazar
Program partition status register to reflect the current partition mode.
Partition capability register is for capability and is a one-time setting.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c | 2
From: Alex Sierra
This work is required for GC 9.4.3, previous to support memory
partitions per node at SVM. When multiple partition is configured,
every BO should be allocated inside one specific partition which
corresponds to the current amdgpu_device and kfd_node.
v2: squash in compilation fi
From: Mukul Joshi
On GFX 9.4.3, there can be multiple KFD nodes. As a result,
SMI events for SVM, queue evict/restore should be raised for
each node independently.
Signed-off-by: Mukul Joshi
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
From: Le Ma
It's not required for compute pipeline and will cause soft lockup on emulation
due to long-time writing.
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 99 -
1 file changed, 99 dele
From: Mukul Joshi
Update interrupt handling in CPX mode for GFX9.4.3 by using the
VMID space instead of SDMA client id to determine if an interrupt
should be processed by a KFD node. This is especially needed for
handling retry faults from MMHUB.
Signed-off-by: Mukul Joshi
Reviewed-by: Felix Ku
From: Shiwu Zhang
Since extended data is not supported, num_links should
be accumulated to reflect the xgmi topology info.
Signed-off-by: Shiwu Zhang
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++--
1 file changed, 2 insertions(+),
From: Amber Lin
GFX_9_4_3 supports multi-XCDs and multi-AIDs in one GPU device. SWS needs
to program IH_VMID_x_LUT with specified XCC instance and corresponded
AID instance.
Signed-off-by: Amber Lin
Reviewed-by: Mukul Joshi
Signed-off-by: Alex Deucher
---
.../drm/amd/amdgpu/amdgpu_amdkfd_gc_
From: Mukul Joshi
The recent overhauling of SDMA queue management introduced a
bug where XGMI SDMA user-mode queue allocation would mark bits
in the SDMA queue bitmap as set, representing a queue from
non-XGMI SDMA engines was allocated. This patch
addresses this issue and fixes the xGMI SDMA que
From: Mukul Joshi
For GFX 9.4.3, use the logical to physical mapping table,
to get the correct XCD instance when accessing registers on
bare metal.
Signed-off-by: Mukul Joshi
Reviewed-by: Amber Lin
Signed-off-by: Alex Deucher
---
.../drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 5 +-
.../gpu
From: Mukul Joshi
Fix the if condition which causes dynamic repartitioning
to fail when trying to switch to DPX mode.
Signed-off-by: Mukul Joshi
Reviewed-by: Amber Lin
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 6 +-
1 file changed, 5 insertions(+), 1 delet
From: Le Ma
Use s2a entry 5/6 registers to decode sdma doorbell trans on different AIDs,
which aligns the entry table in SHUB spec, and leave entry 4 dedicated for VCN
doorbell to avoid conflict.
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/
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