[PATCH 2/2] drm/amdgpu: Add MES KIQ clear to tell RLC that KIQ is dequeued

[Yifan Zha]

[Why]
As MES KIQ is dequeued, tell RLC that KIQ is inactive

[How]
Clear the RLC_CP_SCHEDULERS Active bit which RLC checks KIQ status
In addition, driver can halt MES under SRIOV when unloading driver

Signed-off-by: Yifan Zha <yifan....@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 6e97c28e3162..2e95b71fdbdf 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -1138,6 +1138,18 @@ static void mes_v11_0_kiq_setting(struct amdgpu_ring 
*ring)
        WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
 }
 
+static void mes_v11_0_kiq_clear(struct amdgpu_ring *ring)
+{
+       uint32_t tmp;
+       struct amdgpu_device *adev = ring->adev;
+
+       /* tell RLC which is KIQ dequeue */
+       tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
+       tmp &= 0xffffff00;
+       tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
+       WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
+}
+
 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev)
 {
        int r = 0;
@@ -1182,10 +1194,10 @@ static int mes_v11_0_kiq_hw_fini(struct amdgpu_device 
*adev)
 
        if (amdgpu_sriov_vf(adev)) {
                mes_v11_0_kiq_dequeue(&adev->gfx.kiq.ring);
+               mes_v11_0_kiq_clear(&adev->gfx.kiq.ring);
        }
 
-       if (!amdgpu_sriov_vf(adev))
-               mes_v11_0_enable(adev, false);
+       mes_v11_0_enable(adev, false);
 
        return 0;
 }
-- 
2.25.1