[AMD Official Use Only - Internal Distribution Only]
From: Dechun Song mailto:dechun.s...@amd.com>>
Navi12 0x7360/C7 SKU has no video support, so remove it.
Signed-off-by: Dechun Song mailto:dechun.s...@amd.com>>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 6 --
1 file changed, 4 insertions(+), 2 d
[AMD Public Use]
Reviewed-by: Guchun Chen mailto:guchun.c...@amd.com>>
Regards,
Guchun
From: amd-gfx On Behalf Of Song, Asher
Sent: Wednesday, February 24, 2021 4:07 PM
To: amd-gfx list
Subject: [PATCH] drm/amdgpu: disable VCN for Navi12 SKU
[AMD Official Use Only - Internal Distribution Onl
Am 24.02.21 um 04:28 schrieb xinhui pan:
BO would be added into swap list if it is validated into system domain.
If BO is validated again into non-system domain, say, VRAM domain. It
actually should not be in the swap list.
Signed-off-by: xinhui pan
Reviewed-by: Christian König
Going to pus
From: changzhu
From: Changfeng
The value of max_me in amdgpu_gfx_rlc_setup_cp_table should reduce to 4
when mec2_fw is removed on asic renoir/arcturus. Or it will cause kernel
NULL pointer when modprobe driver.
Change-Id: I268610e85f6acd9200478d0ab1518349ff81469b
Signed-off-by: Changfeng
---
Am 23.02.21 um 22:10 schrieb Jonathan Kim:
Add IH function to allow caller to process ring entries until the
checkpoint write pointer.
This needs a better description of what this will be used for.
Suggested-by: Felix Kuehling
Signed-off-by: Jonathan Kim
---
drivers/gpu/drm/amd/amdgpu/am
Hi Maxime,
for the whole series:
Acked-by: Thomas Zimmermann
Am 19.02.21 um 13:00 schrieb Maxime Ripard:
The current atomic helpers have either their object state being passed as
an argument or the full atomic state.
The former is the pattern that was done at first, before switching to the
l
From: Defang Bo
[ Upstream commit e4180c4253f3f2da09047f5139959227f5cf1173 ]
Similar to commit ("drm/amdgpu: fix IH overflow on Vega10 v2").
When an ring buffer overflow happens the appropriate bit is set in the WPTR
register which is also written back to memory. But clearing the bit in the
WPTR
From: Nicholas Kazlauskas
[ Upstream commit 44a09e3d95bd2b7b0c224100f78f335859c4e193 ]
[Why]
If the BIOS table is invalid or corrupt then get_i2c_info can fail
and we dereference a NULL pointer.
[How]
Check that ddc_pin is not NULL before using it and log an error if it
is because this is unexp
From: Jingwen Chen
[ Upstream commit 64dcf2f01d59cf9fad19b1a387bd39736a8f4d69 ]
[Why]
when vram lost happened in guest, try to write vram can lead to
kernel stuck.
[How]
When the readback data is invalid, don't do write work, directly
reschedule a new work.
Signed-off-by: Jingwen Chen
Reviewe
From: Nirmoy Das
[ Upstream commit 8c0225d79273968a65e73a4204fba023ae02714d ]
For high priority compute to work properly we need to enable
wave limiting on gfx pipe. Wave limiting is done through writing
into mmSPI_WCL_PIPE_PERCENT_GFX register. Enable only one high
priority compute queue to avo
From: Defang Bo
[ Upstream commit e4180c4253f3f2da09047f5139959227f5cf1173 ]
Similar to commit ("drm/amdgpu: fix IH overflow on Vega10 v2").
When an ring buffer overflow happens the appropriate bit is set in the WPTR
register which is also written back to memory. But clearing the bit in the
WPTR
From: Nicholas Kazlauskas
[ Upstream commit 44a09e3d95bd2b7b0c224100f78f335859c4e193 ]
[Why]
If the BIOS table is invalid or corrupt then get_i2c_info can fail
and we dereference a NULL pointer.
[How]
Check that ddc_pin is not NULL before using it and log an error if it
is because this is unexp
From: Jingwen Chen
[ Upstream commit 64dcf2f01d59cf9fad19b1a387bd39736a8f4d69 ]
[Why]
when vram lost happened in guest, try to write vram can lead to
kernel stuck.
[How]
When the readback data is invalid, don't do write work, directly
reschedule a new work.
Signed-off-by: Jingwen Chen
Reviewe
From: Nirmoy Das
[ Upstream commit 8c0225d79273968a65e73a4204fba023ae02714d ]
For high priority compute to work properly we need to enable
wave limiting on gfx pipe. Wave limiting is done through writing
into mmSPI_WCL_PIPE_PERCENT_GFX register. Enable only one high
priority compute queue to avo
From: Defang Bo
[ Upstream commit e4180c4253f3f2da09047f5139959227f5cf1173 ]
Similar to commit ("drm/amdgpu: fix IH overflow on Vega10 v2").
When an ring buffer overflow happens the appropriate bit is set in the WPTR
register which is also written back to memory. But clearing the bit in the
WPTR
From: Nicholas Kazlauskas
[ Upstream commit 44a09e3d95bd2b7b0c224100f78f335859c4e193 ]
[Why]
If the BIOS table is invalid or corrupt then get_i2c_info can fail
and we dereference a NULL pointer.
[How]
Check that ddc_pin is not NULL before using it and log an error if it
is because this is unexp
From: Nicholas Kazlauskas
[ Upstream commit 44a09e3d95bd2b7b0c224100f78f335859c4e193 ]
[Why]
If the BIOS table is invalid or corrupt then get_i2c_info can fail
and we dereference a NULL pointer.
[How]
Check that ddc_pin is not NULL before using it and log an error if it
is because this is unexp
[AMD Public Use]
Hi Shaoyun,
If this is SBR happening during device init, how different is the handling from
the normal passthrough case without XGMI. Shouldn't the minimal init be done
and reset performed in such a case also? Wondering why this is specific to
"xgmi.pending_reset". In case of
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Alex Deucher
From: Wei Yongjun
Sent: Wednesday, February 24, 2021 4:49 AM
To: Hulk Robot ; Wentland, Harry ;
Li, Sun peng (Leo) ; Deucher, Alexander
; Koenig, Christian ;
David Airlie ; Daniel V
GCC reports the following warning with W=1:
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5439:33:
warning: unused variable 'dm' [-Wunused-variable]
5439 | struct amdgpu_display_manager *dm = &adev->dm;
| ^~
This variable only used when CONFI
Ping
Andrey
On 2021-02-20 7:12 a.m., Andrey Grodzovsky wrote:
On 2/20/21 3:38 AM, Christian König wrote:
Am 18.02.21 um 17:41 schrieb Andrey Grodzovsky:
On 2/18/21 10:15 AM, Christian König wrote:
Am 18.02.21 um 16:05 schrieb Andrey Grodzovsky:
On 2/18/21 3:07 AM, Christian König wrote
[AMD Official Use Only - Internal Distribution Only]
> -Original Message-
> From: Koenig, Christian
> Sent: Wednesday, February 24, 2021 4:17 AM
> To: Kim, Jonathan ; amd-
> g...@lists.freedesktop.org
> Cc: Yang, Philip ; Kuehling, Felix
>
> Subject: Re: [PATCH] drm/amdgpu: add ih call t
[AMD Public Use]
SBR happens on hypervisior begin to start the VM . I think the purpose is
hypervisior try to reset the device in a clean state before the VM starts.
The specific issue for XGMI is HW requires all GPUS belongs to the hive need
to be reset within a limit time slot but SBR can
On 2021-02-19 5:24 a.m., Daniel Vetter wrote:
On Thu, Feb 18, 2021 at 9:03 PM Andrey Grodzovsky
wrote:
Looked a bit into it, I want to export sync_object to FD and import from that
FD
such that I will wait on the imported sync object handle from one thread while
signaling the exported sync
Making them an error confuses users and the errors are harmless
as not all asics support all profiles.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1488
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 2 +-
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_pp
On Thu, Feb 18, 2021 at 11:49 PM Nathan Chancellor wrote:
>
> Clang warns:
>
> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu_cmn.c:764:2: warning:
> variable 'structure_size' is used uninitialized whenever switch default
> is taken [-Wsometimes-uninitialized]
> default:
> ^~~
> dr
On Fri, 2021-02-19 at 15:42 -0800, Randy Dunlap wrote:
> On 2/19/21 1:52 PM, Lyude Paul wrote:
> > Since we're about to be adding some more fields and update this
> > documentation, let's rewrap it to the new column limit of 100 beforehand.
> > No actual doc or functional changes are made here.
> >
On 02/24, changfeng@amd.com wrote:
> From: changzhu
>
> From: Changfeng
>
> The value of max_me in amdgpu_gfx_rlc_setup_cp_table should reduce to 4
> when mec2_fw is removed on asic renoir/arcturus. Or it will cause kernel
> NULL pointer when modprobe driver.
Hi,
The commit
6972f8d17f36
On Sun, 2021-02-21 at 20:21 +0200, Laurent Pinchart wrote:
> Hi Lyude,
>
> Thank you for the patch.
>
> On Fri, Feb 19, 2021 at 04:53:11PM -0500, Lyude Paul wrote:
> > This is something that we've wanted for a while now: the ability to
> > actually look up the respective drm_device for a given dr
Per discussions with PMFW team, the driver only needs to
notify the PMFW when the RLC is disabled. The RLC FW will notify
the PMFW directly when it's enabled.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(
Acked-by: Nirmoy Das
On 2/24/21 6:28 PM, Alex Deucher wrote:
Making them an error confuses users and the errors are harmless
as not all asics support all profiles.
Bug:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fdrm%2Famd%2F-%2Fissues%2F1488&dat
This patch set adds support for the Aldebaran GPU. This
includes support for all of the IP blocks on the ASIC.
I'm not sending out the register header updates due to
their size, but you can view the full patch set here:
https://gitlab.freedesktop.org/agd5f/linux/-/commits/amd-staging-drm-next-alde
From: Le Ma
v1: add aldebaran_reg_base_init function to initialize
register base for aldebaran (Le)
v2: update VCN HWIP and initialize base offset (James)
Signed-off-by: Le Ma
Signed-off-by: James Zhu
Reviewed-by: Hawking Zhang
Reviewed-by: Leo Liu
Acked-by: Evan Quan
Signed-off-by: Alex De
From: Le Ma
Add aldebaran in amdgpu_asic_name array and amdgpu_asic_type enum
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Acked-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
include/drm/amd_asic_type.h| 15 --
From: Le Ma
Set backdoor loading way in current phase
v2: change case location to not break other asics
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Acked-by: Evan Quan
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 ++
1 file ch
From: Hawking Zhang
v1: re-use arct ip base offset array for aldebaran (Le)
v2: create aldebaran ip base offset array for major ip
blocks (Hawking)
v3: re-use arct VCN ip base offset array for aldebaran
(James)
v4: correct MP1 ip base offset array (Hawking)
v5: update VCN ip base offset array to
From: Le Ma
Add gfx initial support
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Acked-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu
From: Le Ma
Initialize aldebaran common ip block
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Acked-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/am
From: Le Ma
v1: dupilcate mmhub_v1_7.c from mmhub_v1_0.c because
mmhub register address for aldebaran is different
from existing asics (Le)
v2: switch to latest mmhub_v9_4_2 register headers (Hawking)
v3: squash in init VM_L2_CNTL3 default value for mmhub v1_7
Signed-off-by: Le Ma
Signed-off-by
From: Yong Zhao
Add initial KFD support.
Signed-off-by: Yong Zhao
Signed-off-by: Alex Deucher
---
.../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 1 +
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_de
From: Le Ma
Parses asic configurations stored in gpu_info firmware and make them available
for driver to use.
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Acked-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4
1 file changed, 4 insertions
From: Kevin Wang
add sdma firmware load support for soc model
v2: drop some emulator leftovers (Alex)
Signed-off-by: Kevin Wang
Reviewed-by: Alex Deucher
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 +---
1 file changed, 9 insertion
From: Le Ma
On aldebaran, mmBIF_SDMA4_DOORBELL_RANGE isn't right next to
mmBIF_SDMA3_DOORBELL_RANGE.
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Acked-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 18 ++
1 file changed, 14 inserti
From: Le Ma
Add initial sdma support for aldebaran, and this asic has 5 sdma instances.
v2: remove adundant condition check
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Acked-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 5 +
1 file changed,
From: Le Ma
Add gfx memory controller support
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Acked-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu
From: Le Ma
Set ip blocks and asic family id
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Acked-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drive
From: Hawking Zhang
Add callback functions for psp_v13 ring
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
Reviewed-by: Kevin Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 171 +
1 file changed, 171 insertions(+)
diff --git a/drivers
From: Hawking Zhang
Add callback function to support trusted os
loading for psp v13
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
Reviewed-by: Kevin Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 38 ++
1 file changed, 38 insertions(+
From: Jay Cornwall
Similar to arcturus, but ARCH/ACC VGPRs may now be split unevenly.
A new field in SQ_WAVE_GPR_ALLOC tracks the boundary between the two
sets of VGPRs.
Squash below patches:
drm/amdkfd: Use preprocessor for IP-specific trap handler code
drm/amdkfd: Fix VGPR restore race in gfx
From: Hawking Zhang
Add callback function to support key database firmware
loading for psp v13
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
Reviewed-by: Kevin Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 70 ++
1 file changed, 70 i
From: Hawking Zhang
Add callback function to support sys_drv firmware
loading for psp v13
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
Reviewed-by: Kevin Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 37 ++
1 file changed, 37 insert
From: Hawking Zhang
Initialze psp ip function for aldebaran
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
Reviewed-by: Kevin Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdg
From: Yong Zhao
This gives more information and improves productivity.
Singed-off-by: Yong Zhao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 34 +++
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c| 5 +--
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
From: Hawking Zhang
Initialize sos microcode for aldebaran
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
Reviewed-by: Kevin Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile| 3 +-
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 57 ++
drivers/
From: Hawking Zhang
Add psp v13 ip block to soc ip init list for aldebaran
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
Reviewed-by: Kevin Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 8
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 9 +
d
From: Hawking Zhang
Aldebaran will use smuio v13_0 callbacks
Signed-off-by: Hawking Zhang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c | 121 +++
drivers/gpu/drm/amd/a
From: Hawking Zhang
is_host_gpu_xgmi_supported is used to query gpu and
cpu/host link type. get_die_id is used to query die
ids.
Signed-off-by: Hawking Zhang
Reviewed-by: Alex Deucher
Reviewed-by: John Clements
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h | 2 ++
From: Hawking Zhang
SRIOV pf/vf function identifier regsiter in aldebaran
is the same as the one in arcturus
Signed-off-by: Hawking Zhang
Reviewed-by: Kevin Wang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 1 +
1 file changed, 1 insertion(+)
From: Hawking Zhang
mmRCC_DEV0_EPF0_STRAP0 offset in aldebaran is changed
from arcturus
Signed-off-by: Hawking Zhang
Reviewed-by: Kevin Wang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion
From: Hawking Zhang
ALDEBARAN doesn't need these golden settings.
Signed-off-by: Hawking Zhang
Reviewed-by: Kevin Wang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/d
From: Hawking Zhang
PMFW should be loaded before any operation that
may toggling DF-Cstate. otherwsie, tOS has no
choice but to locally toggle DF Cstate (i.e.
disable DF-Cstate even it already enabled by VBIOS)
Signed-off-by: Hawking Zhang
Reviewed-by: Kevin Wang
Reviewed-by: Le Ma
Signed-off
From: Hawking Zhang
initialize smuio v13_0 callbacks for aldebaran
Signed-off-by: Hawking Zhang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gp
From: Rajneesh Bhardwaj
Like its predecessors Aldebran also supports advanced high bandwidth
GPU-GPU communication interface known as xgmi. This enables the basic
xgmi support while refactoring the code slightly.
Detection of xgmi link between host cpu and gpu will be introduced in a
different p
From: James Zhu
including firmware support etc.
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu
From: James Zhu
Aldebaran is using vcn2.6, and the main change is vcn2.6 using
AMDGPU_MMHUB_0, and vcn2.5 using AMDGPU_MMHUB_1
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 99 ++-
drivers/gpu/drm
From: Rajneesh Bhardwaj
Aldebaran uses registers defined in header gc_9_4_2 but much of the xgmi
related functionality can be obtained by reusing the exisitng definition
from gfxhub_v1_1_get_xgmi_info. While adding support for Aldebaran, also
refactored code to better handle the new scenario.
Si
From: Rajneesh Bhardwaj
Currently host-gpu io link is always reported as PCIe however, on some
A+A systems, there could be one xgmi link available. This change exposes
xgmi link via sysfs when it is present.
v2: fix includes (Alex)
Reviewed-by: Oak Zeng
Reviewed-by: Hawking Zhang
Signed-off-b
From: James Zhu
Aldebaran has a new mmBIF_MMSCH1_DOORBELL_RANGE setting.
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/
From: Oak Zeng
Client ID 26 is reserved. Add it to the table.
Signed-off-by: Oak Zeng
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 1 +
drivers/gpu/drm/amd/include/soc15_ih_clientid.h | 1 +
2 files changed, 2 insertions(+)
diff --git
From: Eric Huang
v1: new A+A HW supports cached vram mapped to cpu (Eric)
v2: switch to range manager init functions for xgmi
connected host case (Hawking)
Signed-off-by: Eric Huang
Reviewed-by: Oak Zeng
Singed-off-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu
From: James Zhu
Enable VCN on aldebaran
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 486839
From: James Zhu
Aldebaran is using jpeg2.6, and the main change is jpeg2.6 using
AMDGPU_MMHUB_0, and jpeg2.5 using AMDGPU_MMHUB_1.
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 65 +-
drivers/gpu
From: Hawking Zhang
MEC2_JT is not supported
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v
From: Eric Huang
To support new cache coherence HW on A+A platform mainly in KFD.
Signed-off-by: Eric Huang
Reviewed-by: Oak Zeng
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 30 +--
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 ++
2 f
From: Rajneesh Bhardwaj
This applies to AMD Accelerated Processing Platforms that support host
gpu interconnect throguh a special link (xgmi). Aldebaran systems will
support this special feature for utilizing the benefits of host-gpu
cache coherence. This change outlines the basic framework for m
From: Kevin Wang
switch to use register distance member for mmhub v1_7
instead of hardcode
Signed-off-by: Kevin Wang
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c | 44 -
1 file changed, 29 insertions(+), 15 deletio
From: Hawking Zhang
only xgmi ta is supported at this stage
Signed-off-by: Hawking Zhang
Reviewed-by: Kevin Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
b/drivers/g
From: James Zhu
enable JPEG on aldebaran
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 99c2547
From: Eric Huang
The macro is for memory mapped by GPU as uncached.
Signed-off-by: Eric Huang
Reviewed-by: Oak Zeng
Signed-off-by: Alex Deucher
---
include/uapi/linux/kfd_ioctl.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl
From: Hawking Zhang
fix -Wmissing-protoypes warning
Signed-off-by: Hawking Zhang
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c
b
From: Oak Zeng
Add more function pointers to amdgpu_mmhub_funcs. ASIC specific
implementation of most mmhub functions are called from a general
function pointer, instead of calling different function for
different ASIC.
V2: Split patch into upstreamable and aldebaran
Signed-off-by: Oak Zeng
Re
From: John Clements
updated psp bin parsing and load register list
v2: update to latest interface (Alex)
Reviewed-by: Hawking Zhang
Signed-off-by: John Clements
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 +
From: Feifei Xu
Add 0x7408,0x740C,0x740F in pciidlist.
Signed-off-by: Feifei Xu
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/d
From: John Clements
call host to psp cmd to load reg list
v2: update to latest interface (Alex)
Reviewed-by: Hawking Zhang
Signed-off-by: John Clements
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 28 +
1 file changed, 28 insertions(+)
From: Yong Zhao
Aldebaran should be the same as Arcturus in the PTE SNOOPED bit handling.
Signed-off-by: Yong Zhao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
From: Kevin Wang
Add initial swSMU support.
v1: add smu13 ip support for aldebaran asic (Kevin/Kenneth)
v2: switch to thm/mp v13_0 ip headers (Hawking)
v3: squash in updates (Alex)
Signed-off-by: Kevin Wang
Signed-off-by: Kenneth Feng
Reviewed-by: Kenneth Feng
Signed-off-by: Hawking Zhang
S
From: Hawking Zhang
add exteranal rev_id for aldebaran
Signed-off-by: Hawking Zhang
Reviewed-by: Kevin Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/
From: Hawking Zhang
vcn fw front door loading is not functional. comments
out vcn/jpeg ip blocks so people can load amdgpu driver
without specify ip_mask module parameter.
Signed-off-by: Hawking Zhang
Reviewed-by: Kevin Wang
Reviewed-by: James Zhu
Signed-off-by: Alex Deucher
---
drivers/gpu
From: Kevin Wang
add aldebaran smu13 driver if header
v2: squash in updates
Signed-off-by: Kevin Wang
Signed-off-by: Kenneth Feng
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
.../amd/pm/inc/smu13_driver_if_aldebaran.h| 512 ++
1 file changed, 512 insertions
From: Kevin Wang
declare sdma firmware binary file for aldebaran
Signed-off-by: Kevin Wang
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/g
From: John Clements
added host to psp cmd for register list
v2: update to new interface (Alex)
Reviewed-by: Hawking Zhang
Signed-off-by: John Clements
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/
From: Hawking Zhang
Query vram_type, channel_num, channel_width
information through atomfirmware i/f
Signed-off-by: Hawking Zhang
Reviewed-by: Feifei Xu
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 21 +++
drivers/gpu/drm/amd/include/atomfir
From: Feifei Xu
Use MSG_GfxDriverReset for mode reset and retire MSG_Mode1Reset.
Centralize soc15_asic_mode1_reset() and nv_asic_mode1_reset()functions.
Add mode2_reset_is_support() for smu->ppt_funcs.
Signed-off-by: Feifei Xu
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
driver
From: Hawking Zhang
perform one-time initialization for sdma registers
Signed-off-by: Hawking Zhang
Reviewed-by: Kevin Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgp
From: Hawking Zhang
aldebaran removed gds internal memory for atomic usage.
it only supports gws opcode in kernel like barrier,
semaphore.etc. there won't be usage of gds in either
kernel or pm4 packet. max_wave_id should also be marked
as deprecated for aldebaran.
Signed-off-by: Hawking Zhang
From: Hawking Zhang
sdma ras function is the main structure to support
sdma ras on aldebaran. the patch initializes late_init
late_fini callbacks.
Signed-off-by: Hawking Zhang
Reviewed-by: Dennis Li
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile| 1 +
drivers/gpu/drm
From: Hawking Zhang
The callback will be invoked to reset sdma ras error
counters when needed.
Signed-off-by: Hawking Zhang
Reviewed-by: Dennis Li
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/driv
From: Lijo Lazar
Temporarily force to use BU PPTable defined in VBIOS. Add support to
override PPTable defined by module parameter.Add FW reported version to
kernel log.
Signed-off-by: Lijo Lazar
Reviewed-by: Kenneth Feng
Reviewed-by: Kevin Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/d
From: Hawking Zhang
The callback will be invoked to harvest all kinds
of mmhub ras error
Signed-off-by: Hawking Zhang
Reviewed-by: Dennis Li
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c | 740 ++--
1 file changed, 689 insertions(+), 51 deletions(
From: Feifei Xu
v1: Added some pspbl parameters
v2: fix fallthrough issue
Signed-off-by: Feifei Xu
Reviewed-by: Hawking Zhang
Reviewed-by: Kevin Wang
Reviewed-by: Lazar Lijo
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/include/atomfirmware.h | 5 -
drivers/gpu/drm/amd/pm/sws
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