Signed-off-by: ZhiJie.Zhang
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 2ee6edb3df93..ef4acb1d4a80 10064
It's in accordance with pmfw 65.22.0 for navy_flounder.
Signed-off-by: Jiansong Chen
Change-Id: I85fcf7a238b5a7d1da76709ef7963140702048ab
---
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
b/drive
Support Navi1x gfxoff state retrieving.
Change-Id: I57aa506b82dc122bbead708c580a4720e536cfce
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h| 2 ++
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 1 +
.../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c| 24 ++
Support Sienna Cichlid gfxoff state retrieving.
Change-Id: I952b652a41a33cdaa05e5294b17a8cfa45a18818
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
b
For some ASICs, the real dpm feature disablement job is handled by
PMFW during baco reset and custom pptable loading. Cached dpm feature
status need to be cleared to pair that.
Change-Id: I9e37d80e13599833301c04711b097fb37c2e41f9
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_s
[AMD Public Use]
A few nit-picks, please check.
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Evan Quan
Sent: Friday, January 15, 2021 5:34 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Quan, Evan
Subject: [PATCH 1/2] drm/amd/pm: fulfill the API for nav
[AMD Public Use]
Reviewed-by: Tao Zhou
> -Original Message-
> From: Jiansong Chen
> Sent: Friday, January 15, 2021 5:27 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhou1, Tao ; Chen, Jiansong (Simon)
>
> Subject: [PATCH] drm/amd/pm: update driver if version for navy_flounder
>
> It's
The buffer is allocated with the size of pointer and copy with the size of
data structure. Then trigger the system memory page fault. Use the
orignal data structure to get the object size.
Fixes: a8e30005b drm/amd/display/dc/core/dc_link: Move some local data
from the stack to the heap
Signed-off
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Jinzhou.Su
Regards,
Joe
-Original Message-
From: Huang, Ray
Sent: Saturday, January 16, 2021 2:47 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Su, Jinzhou (Joe)
; Zhu, Changfeng ; Huang, Ray
; Lee Jon
Am 15.01.21 um 19:46 schrieb Huang Rui:
The buffer is allocated with the size of pointer and copy with the size of
data structure. Then trigger the system memory page fault. Use the
orignal data structure to get the object size.
Fixes: a8e30005b drm/amd/display/dc/core/dc_link: Move some local d
[AMD Public Use]
Hi Rui,
Seems the change has violated the kernel coding style😊, please help check.
https://www.kernel.org/doc/html/latest/process/coding-style.html
Allocating memory
..
The preferred form for passing a size of a struct is the following:
p = kmalloc(sizeof(*p), ...);
The alte
Am 06.01.21 um 21:21 schrieb Maxim Levitsky:
On Mon, 2021-01-04 at 09:45 -0700, Alex Williamson wrote:
On Mon, 4 Jan 2021 12:34:34 +0100
Christian König wrote:
Hi Maxim,
I can't help with the display related stuff. Probably best approach to
get this fixes would be to open up a bug tracker fo
Hi
Am 15.01.21 um 13:56 schrieb Maxime Ripard:
The current atomic helpers have either their object state being passed as
an argument or the full atomic state.
The former is the pattern that was done at first, before switching to the
latter for new hooks or when it was needed.
Let's start conve
On Fri, Jan 15, 2021 at 07:22:43PM +0800, Christian König wrote:
> Am 15.01.21 um 19:46 schrieb Huang Rui:
> > The buffer is allocated with the size of pointer and copy with the size of
> > data structure. Then trigger the system memory page fault. Use the
> > orignal data structure to get the obje
On Fri, Jan 15, 2021 at 07:26:23PM +0800, Chen, Jiansong (Simon) wrote:
> [AMD Public Use]
>
> Hi Rui,
> Seems the change has violated the kernel coding style😊, please help check.
> https://www.kernel.org/doc/html/latest/process/coding-style.html
>
> Allocating memory
> ..
> The preferred for
Hi
Am 15.01.21 um 13:56 schrieb Maxime Ripard:
diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c
b/drivers/gpu/drm/imx/ipuv3-plane.c
index 8a4235d9d9f1..2cb09e9d9306 100644
--- a/drivers/gpu/drm/imx/ipuv3-plane.c
+++ b/drivers/gpu/drm/imx/ipuv3-plane.c
@@ -344,12 +344,12 @@ static const struct drm
Follow the coding style of size of a struct, changing to:
p = kmalloc(sizeof(*p), ...);
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu
Am 15.01.21 um 22:54 schrieb Huang Rui:
Follow the coding style of size of a struct, changing to:
p = kmalloc(sizeof(*p), ...);
Signed-off-by: Huang Rui
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
On Fri, Jan 15, 2021 at 2:28 AM Dave Airlie wrote:
>
> On Fri, 15 Jan 2021 at 07:22, Alex Deucher wrote:
> >
> > Hi Dave, Daniel,
> >
> > More new stuff for 5.12.
> >
> > The following changes since commit 044a48f420b9d3c19a135b821c34de5b2bee4075:
> >
> > drm/amdgpu: fix DRM_INFO flood if displ
[AMD Public Use]
Can you help explain why we need introduce such a callback? Seems it has
presupposed pmfw's internal
Implementation.
Regards,
Jiansong
-Original Message-
From: amd-gfx On Behalf Of Evan Quan
Sent: Friday, January 15, 2021 5:34 PM
To: amd-gfx@lists.freedesktop.org
Cc: D
Now that atomic_check takes the global atomic state as a parameter, we
don't need to go through the pointer in the plane state.
This was done using the following coccinelle script:
@ plane_atomic_func @
identifier helpers;
identifier func;
@@
static struct drm_plane_helper_funcs helpers = {
The current atomic helpers have either their object state being passed as
an argument or the full atomic state.
The former is the pattern that was done at first, before switching to the
latter for new hooks or when it was needed.
Let's start convert all the remaining helpers to provide a consiste
On Sat, 16 Jan 2021, Huang Rui wrote:
> The buffer is allocated with the size of pointer and copy with the size of
> data structure. Then trigger the system memory page fault. Use the
> orignal data structure to get the object size.
>
> Fixes: a8e30005b drm/amd/display/dc/core/dc_link: Move some
Le 15/01/2021 à 11:10, Colin Ian King a écrit :
On 15/01/2021 10:07, Christophe JAILLET wrote:
Le 15/01/2021 à 10:37, Colin Ian King a écrit :
On 12/01/2021 10:07, Dan Carpenter wrote:
On Mon, Jan 11, 2021 at 11:46:38AM +, Colin King wrote:
From: Colin Ian King
A recent change added a n
On 15/01/2021 10:07, Christophe JAILLET wrote:
> Le 15/01/2021 à 10:37, Colin Ian King a écrit :
>> On 12/01/2021 10:07, Dan Carpenter wrote:
>>> On Mon, Jan 11, 2021 at 11:46:38AM +, Colin King wrote:
From: Colin Ian King
A recent change added a new BOOTUP_DEFAULT power profile
On 12/01/2021 10:07, Dan Carpenter wrote:
> On Mon, Jan 11, 2021 at 11:46:38AM +, Colin King wrote:
>> From: Colin Ian King
>>
>> A recent change added a new BOOTUP_DEFAULT power profile mode
>> to the PP_SMC_POWER_PROFILE enum but omitted updating the
>> corresponding profile_name array. Fix
On Fri, 15 Jan 2021, Christian König wrote:
> Am 15.01.21 um 19:46 schrieb Huang Rui:
> > The buffer is allocated with the size of pointer and copy with the size of
> > data structure. Then trigger the system memory page fault. Use the
> > orignal data structure to get the object size.
> >
> > Fi
Hi,
On Fri, Jan 15, 2021 at 02:46:36PM +0100, Thomas Zimmermann wrote:
> Hi
>
> Am 15.01.21 um 13:56 schrieb Maxime Ripard:
> > diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c
> > b/drivers/gpu/drm/imx/ipuv3-plane.c
> > index 8a4235d9d9f1..2cb09e9d9306 100644
> > --- a/drivers/gpu/drm/imx/ipuv3-p
Le 15/01/2021 à 10:37, Colin Ian King a écrit :
On 12/01/2021 10:07, Dan Carpenter wrote:
On Mon, Jan 11, 2021 at 11:46:38AM +, Colin King wrote:
From: Colin Ian King
A recent change added a new BOOTUP_DEFAULT power profile mode
to the PP_SMC_POWER_PROFILE enum but omitted updating the
co
On Sat, 16 Jan 2021, Huang Rui wrote:
> Follow the coding style of size of a struct, changing to:
>
> p = kmalloc(sizeof(*p), ...);
>
> Signed-off-by: Huang Rui
> ---
> drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Lee J
Most drivers call the argument to the plane atomic_check hook simply
state, which is going to conflict with the global atomic state in a
later rework. Let's rename it to new_plane_state (or new_state depending
on the convention used in the driver).
This was done using the coccinelle script below,
The current atomic helpers have either their object state being passed as
an argument or the full atomic state.
The former is the pattern that was done at first, before switching to the
latter for new hooks or when it was needed.
Let's start convert all the remaining helpers to provide a consiste
On Fri, Jan 15, 2021 at 9:51 AM Alex Deucher wrote:
>
> On Fri, Jan 15, 2021 at 2:28 AM Dave Airlie wrote:
> >
> > On Fri, 15 Jan 2021 at 07:22, Alex Deucher wrote:
> > >
> > > Hi Dave, Daniel,
> > >
> > > More new stuff for 5.12.
> > >
> > > The following changes since commit
> > > 044a48f420b
This DC patchset brings improvements in multiple areas.
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.48
Aric Cyr (2):
drm/amd/display: Allow PSTATE chnage when no displays are enabled
drm/amd/display: 3.2.119
Bing Guo (2):
drm/amd/display: Change function decide_dp_link_
From: Vladimir Stempen
[why]
Heavy corruption or blank screen reported on wake,
with 6k display connected and FEC enabled
[how]
When Disable/Enable stream for display pipes on HPDRX,
DC should take into account ODM split pipes.
Signed-off-by: Vladimir Stempen
Reviewed-by: Aric Cyr
Acked-by: A
From: Mike Hsieh
[Why]
FEC over eDP support is incomplete.
[How]
Disable FEC over eDP.
Signed-off-by: Mike Hsieh
Reviewed-by: Nikola Cornij
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/driver
From: Sung Lee
[WHY]
Previously as MPO + ODM Combine was not supported, finding secondary pipes
for each case was mutually exclusive. Now that both are supported at the same
time, both cases should be taken into account when finding a secondary pipe.
[HOW]
If a secondary pipe cannot be found bas
From: Nicholas Kazlauskas
[Why & How]
These can differ per ASIC or not be present. Don't call the dcn20 ones
directly but rather the ones defined by the ASIC init table.
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Eric Yang
Acked-by: Anson Jacob
---
.../amd/display/dc/dcn10/dcn10_hw_sequ
From: Stylon Wang
[Why]
Since Linux 5.9.0, DRM has provided vrr_range debugfs for
all connectors. Reporting Freesync capability to vrr_range
debugfs entry registered in Linux DM no longer works.
[How]
Report min/max vertical frequency to vrr_range debugfs entrry
created by DRM connectors. Remove
From: Nicholas Kazlauskas
[Why]
If the BIOS table is invalid or corrupt then get_i2c_info can fail
and we dereference a NULL pointer.
[How]
Check that ddc_pin is not NULL before using it and log an error if it
is because this is unexpected.
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Eric
From: Nicholas Kazlauskas
[Why]
We need hardware reset before hardware init for backdoor loading when
we're reusing the framebuffer memory.
[How]
This doesn't run if the hardware isn't already in reset from software
perspective. The reset function has register level checks so just
remove the sof
From: Nicholas Kazlauskas
[Why]
DMCUB encounters a page fault/double exception with driver direct load
because DMCUB is not held in soft reset after releasing secure reset.
The clean shutdown sequence via GPINT is also not executed in this
sequence which leaves hardware behavior in an indetermin
From: Wyatt Wood
[Why]
FW version check doesn't allow dmu_stg to support cached inbox,
which yields much better performance than region 4.
[How]
Check a range of fw versions, rather than a simple greater than check.
Signed-off-by: Wyatt Wood
Reviewed-by: Nicholas Kazlauskas
Acked-by: Anson Ja
From: George Shen
[Why/How]
Add logging statements to assist in debugging
errors in the BIOS object table.
Signed-off-by: George Shen
Reviewed-by: Nicholas Kazlauskas
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 6 ++
drivers/gpu/drm/amd/display/dc/core/dc_
From: Bing Guo
Why:
Function decide_dp_link_settings() loops infinitely when required bandwidth
can't be supported.
How:
Check the required bandwidth against verified_link_cap before trying to
find a link setting for it.
Signed-off-by: Bing Guo
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
---
From: Bing Guo
Why:
dml20v2_ModeSupportAndSystemConfigurationFull() didn't check against
DesiredBPP, so it doesn't work correctly when DesiredBPP can't be satisfied.
How:
Port the TruncToValidBPP() version from display_mode_vba_21.c to
display_mode_vba_20v2.c.
Signed-off-by: Bing Guo
Reviewed-
From: Aric Cyr
[Why]
When no displays are currently enabled, display driver should not
disallow PSTATE switching.
[How]
Allow PSTATE switching if either the active configuration supports it,
or there are no active displays.
Signed-off-by: Aric Cyr
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
-
From: Jake Wang
[WHY]
dram clock change latencies get updated using ddr4 latency table, but
that update does not happen before validation. This value
should not be the default and should be number received from
df for better mode support.
This may cause a PState hang on high refresh panels with s
From: Anthony Koo
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/displa
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index f3ba02cc85d2..28e0b6a
On Fri, Jan 15, 2021 at 3:55 AM ZhiJie.Zhang wrote:
>
> Signed-off-by: ZhiJie.Zhang
Applied with a cleaned up commit message.
Thanks!
Alex
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 7 +--
> 1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/
ROCm user mode depends on userptr support. Without it, KFD is basically
useless.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/Kconfig
b/drivers/gpu/drm/amd/amdkfd/Kconfig
index e8fb10c41f16..2
Hi Maxime,
Thank you for the patch.
On Fri, Jan 15, 2021 at 01:56:54PM +0100, Maxime Ripard wrote:
> Most drivers call the argument to the plane atomic_check hook simply
> state, which is going to conflict with the global atomic state in a
> later rework. Let's rename it to new_plane_state (or ne
Hi Maxime,
Thank you for the patch.
On Fri, Jan 15, 2021 at 01:56:56PM +0100, Maxime Ripard wrote:
> The current atomic helpers have either their object state being passed as
> an argument or the full atomic state.
>
> The former is the pattern that was done at first, before switching to the
> l
Hi Maxime,
Thank you for the patch.
On Fri, Jan 15, 2021 at 01:56:57PM +0100, Maxime Ripard wrote:
> Now that atomic_check takes the global atomic state as a parameter, we
> don't need to go through the pointer in the plane state.
>
> This was done using the following coccinelle script:
>
> @ p
[AMD Public Use]
Hi all,
I tested this patch on Navi10 and a Renoir laptop (HP Envy 360 with Ryzen 5
4500U).
Tested the laptop with its internal 1080p display and externally with USB-C to
DP, USB-C to HDMI, USB- C to VGA, and USB-C to DVI to 2x 4k60 displays, 1x
1440p 144hz display, and one
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