For some ASICs, the real dpm feature disablement job is handled by
PMFW during baco reset and custom pptable loading. Cached dpm feature
status need to be cleared to pair that.
Change-Id: I9e37d80e13599833301c04711b097fb37c2e41f9
Signed-off-by: Evan Quan <evan.q...@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 7fe61ad3ed10..facada52350a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1175,6 +1175,16 @@ static int smu_hw_init(void *handle)
return 0;
}
+static void smu_reset_cached_dpm_feature_status(struct smu_context *smu)
+{
+ struct smu_feature *feature = &smu->smu_feature;
+
+ mutex_lock(&feature->mutex);
+ bitmap_zero(feature->enabled, feature->feature_num);
+ bitmap_zero(feature->supported, feature->feature_num);
+ mutex_unlock(&feature->mutex);
+}
+
static int smu_disable_dpms(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
@@ -1197,16 +1207,20 @@ static int smu_disable_dpms(struct smu_context *smu)
*/
if (smu->uploading_custom_pp_table &&
(adev->asic_type >= CHIP_NAVI10) &&
- (adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
+ (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) {
+ smu_reset_cached_dpm_feature_status(smu);
return 0;
+ }
/*
* For Sienna_Cichlid, PMFW will handle the features disablement
properly
* on BACO in. Driver involvement is unnecessary.
*/
if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
- use_baco)
+ use_baco) {
+ smu_reset_cached_dpm_feature_status(smu);
return 0;
+ }
/*
* For gpu reset, runpm and hibernation through BACO,
--
2.29.0
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