From: Emil Velikov
The driver does not hold struct_mutex, thus using the locked version of
the helper is incorrect.
Cc: Alex Deucher
Cc: Christian König
Cc: amd-gfx@lists.freedesktop.org
Fixes: a39414716ca0 ("drm/amdgpu: add independent DMA-buf import v9"):
Signed-off-by: Emil Velikov
Acked-b
Hello!
Registration & Call for Proposals are now open for XDC 2020, which will
take place at the Gdańsk University of Technology in Gdańsk, Poland on
September 16-18, 2020.
Thanks to LWN.net for hosting the website again this year!
https://xdc2020.x.org
As usual, the conference is free
From: Nikola Cornij
[why]
Assigning a different DSC resource than the one previosly used is
currently not handled. This causes black screen on mode change when more
than one monitor is connected on some ASICs.
[how]
- Acquire the previously used DSC if available
- Make sure re-program is trigger
From: Sung Lee
[WHY]
Failing validation when building scaling parameters causes corruption to
occur due to pipe splitting with smaller pixel widths than HW supports.
This needs to fail silently for now to hide the corruption until the
corruption itself can be fixed.
[HOW]
Do not fail validation
From: Dmytro Laktyushkin
Current odm/mpc combine logic to detect which pipes need to split
logically is flawed leading to incorrect pipe merge/split operations
being taken.
This change cleans up the logic and fixes the logical errors.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernste
From: Nicholas Kazlauskas
[Why]
New unified firmware binary with only inst const still passes down
fw_bss_data != NULL and params->bss_data_size == 0 from DM.
This leads it into the legacy path causing firmware state allocation to
be too small.
[How]
Check bss_data_size as well.
Signed-off-by:
From: Jaehyun Chung
[Why]
Remove dm_write_persistent_data and dm_read_persistent_data as
persistence should be handled in DM.
[How]
Remove functions. Move read/write calls into DM layer while maintaining
logic.
Signed-off-by: Jaehyun Chung
Reviewed-by: Anthony Koo
Acked-by: Rodrigo Siqueira
From: Nicholas Kazlauskas
[Why]
In order to switch over the inbox from region4 to cw4 we need to know if
the firmware is capable of properly invalidating the cache before
reading the commands.
Easiest way is to just check the firmware version, but we don't have the
helper macros or a way for the
From: Dmytro Laktyushkin
Save the correct num vmid during resource creation and fix RN gpuvm
level from 1 to 16 vmid entries.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h | 1 +
drivers/gpu/
From: Wenjing Liu
[why]
DP link layer CTS specs updated to change the test parameters in test
4.2.1.1.
Before it requires source to delay 400us on aux no reply.
With the specs updates Errata5, it requires source to delay 3.2ms
(based on LTTPR aux timeout)
This causes our test to fail after updati
Christian Koenig pointed out a code duplication related to bit swap in
case of big-endian manipulation. This commit adds a helper for handling
this verification and reduces the requirement of replicate some part of
the code.
Signed-off-by: Rodrigo Siqueira
Reviewed-by: Wyatt Wood
Acked-by: Rodri
From: Anthony Koo
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_fw_meta.h | 2 ++
drivers/gpu/drm/amd/display/dmub/inc/dmub_rb.h | 6 --
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drive
From: Nicholas Kazlauskas
[Why]
If bss_data_size is 0 then we shouldn't be passing down fw_bss_data into
the DMUB service since the region isn't really "valid."
[How]
Pass NULL instead if the size is 0.
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Zhan Liu
Acked-by: Rodrigo Siqueira
---
From: Dmytro Laktyushkin
This change removes internal rounding in dml_log2 function.
Dml_log2 is expected to return a float output. In case an int is needed
dml will floor the output on it's own.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Rodrigo Siqueira
---
dr
From: Dmytro Laktyushkin
Set the correct value to immediate flip required field.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Samson Tam
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h | 2 +-
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c |
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* FW updates;
* Fix issues on DML, modes, ABM, and others;
* Remove file that use FPU unit;
* Improvements on DMUB, DM, DP, and others.
Anthony Koo (2):
drm/amd/display: FW release 1.0.10
drm/amd/display: FW Re
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 85908561c741..a4
During the rework for removing the FPU issues, I found the following
warning:
[..] dml_common_defs.o: warning: objtool: dml_round()+0x9: FPU
instruction outside of kernel_fpu_{begin,end}()
This file has a single function that does not need to be in a specific
file. This commit drop dml_com
From: Yongqiang Sun
[Why & How]
Implement abm set_pipe call stacks
Have some asics speicifc call stacks for abm.
Signed-off-by: Yongqiang Sun
Reviewed-by: Anthony Koo
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 92 ---
.../display/dc/dce110/
From: Nicholas Kazlauskas
[Why]
We dropped the delay after changed the cursor functions locking the
entire pipe to locking just the CURSOR registers to fix page flip
stuttering - this introduced cursor stuttering instead, and an underflow
issue.
The cursor update can be delayed indefinitely if t
From: Stylon Wang
[Why]
When "max bpc" is set to enable deep color, some modes are removed from
the list if they fail validation on max bpc. These modes should be kept
if they validates fine with lower bpc.
[How]
- Retry with lower bpc in mode validation.
- Same in atomic commit to apply working
From: Anthony Koo
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 2 +-
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 12 ---
.../drm/amd/display/dmub/inc/dmub_cmd_dal.h | 35 +++
.../g
From: Jake Wang
[WHY]
Currently we're copying the entire bios image into vbios. Loading time
for FW with entire bios(54272 bytes) is 105138us. By copying only the
sections of bios we're using(4436 bytes), loading time drops to 104326us
which saves us 812us.
[HOW]
ROM header, master data table,
From: Dmytro Laktyushkin
Preparation for new asic support.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Rodrigo Siqueira
---
.../dc/dml/dcn20/display_rq_dlg_calc_20.c | 33 +--
.../dc/dml/dcn20/display_rq_dlg_calc_20v2.c | 33 +--
.../dc/dml/dcn21/display_r
From: Nicholas Kazlauskas
[Why]
The minimum plane size we can support in DML is 16x16. If we try to pass
a 16x16 plane with dynamic pipe split then validation will fail since it
tries to split it into two pipes, each 8x8.
Some userspace doesn't check that the commit fails and because the
commit
From: Yongqiang Sun
[Why]
dal side nv12 wa has a lot of side effects.
KMD side wa is used, so this should be remove.
[How]
Removed wa from dal side.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/core/dc_vm_helper.c| 3 -
dri
From: Nicholas Kazlauskas
[Why]
Region 4 is non cacheable and slower than using cache window 4.
[How]
Check the firmware version to determine how we should program the
base address and memory windows.
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Tony Cheng
Acked-by: Rodrigo Siqueira
---
From: Jinze Xu
[Why]
When disconnect fe from be, something such as unstable clock may cause
garbage occurs.
[How]
Send set avmute at the beginning of disable stream and send reset avmute
at the end of enable stream.
Signed-off-by: Jinze Xu
Reviewed-by: Anthony Koo
Acked-by: Rodrigo Siqueira
From: Wyatt Wood
[Why]
Due to packing of abm_config_table, memory addresses aren't aligned to
32 bit boundary dmcub prefers. Therefore when using pointers to this
structure, it's possible that dmcub will automatically align the data
read from that address, yielding incorrect values.
[How]
Inste
From: Vladimir Stempen
[Why]
DP training sequence to set SCRAMBLING_DISABLE bit properly based on
training pattern - per DP Spec.
[How]
Update dpcd_pattern.v1_4.SCRAMBLING_DISABLE with 1 for TPS1, TPS2, TPS3,
but not for TPS4.
Signed-off-by: Vladimir Stempen
Reviewed-by: Wenjing Liu
Acked-by:
Add some APU flags to simplify handling of different APU
variants. It's easier to understand the special cases
if we use names flags rather than checking device ids and
silicon revisions.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd
Move it into the fw_info function since it's logically part
of the same functionality.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/d
We need to get the silicon revision id before we parse
the firmware in order to load the correct gpu info firmware
for raven2 variants.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1103
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8
1 file change
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