Hi Petr,
well that is indeed a rather unusual use case.
I'm not 100% sure how you actually hacked the HD4550 to do what you want
to do, cause this ASIC generation shouldn't support this.
For a Polaris you can just use the PCIe resizeable BAR extension. For
how to use it see the pci_resize_re
On Tue, Aug 27, 2019 at 01:16:13PM -0700, Ralph Campbell wrote:
>
> On 8/27/19 11:41 AM, Jason Gunthorpe wrote:
> > On Fri, Aug 23, 2019 at 03:17:53PM -0700, Ralph Campbell wrote:
> >
> > > Signed-off-by: Ralph Campbell
> > > mm/hmm.c | 3 +++
> > > 1 file changed, 3 insertions(+)
> > >
> >
The driver does not support these sensors yet and there is no point in
creating sysfs attributes which will always return an error.
Signed-off-by: Jean Delvare
Cc: Alex Deucher
Cc: "Christian König"
Cc: "David (ChunMing) Zhou"
---
This works for me however I couldn't seen any other place in th
On Fri, Aug 23, 2019 at 03:17:51PM -0700, Ralph Campbell wrote:
> I have been working on converting Jerome's hmm_dummy driver and self
> tests into a stand-alone set of tests to be included in
> tools/testing/selftests/vm and came across these two bug fixes in the
> process. The tests aren't quite
Den tis 27 aug. 2019 kl 20:17 skrev Andrey Grodzovsky
:
>
> This should be checked at all places job is accessed.
>
> Signed-off-by: Andrey Grodzovsky
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/dr
Am 27.08.19 um 20:17 schrieb Andrey Grodzovsky:
This should be checked at all places job is accessed.
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/
From: "Tianci.Yin"
Fix compute ring test failure in sriov scenario.
Signed-off-by: Tianci.Yin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 14 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 +
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amd
Am 28.08.19 um 11:25 schrieb Tianci Yin:
From: "Tianci.Yin"
Fix compute ring test failure in sriov scenario.
Signed-off-by: Tianci.Yin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 14 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 +
2 files changed, 11 insertions(+), 4 dele
Hi Christian,
I have just realized the stolen_vga_memory problem,
I have ever thought that no one really use the stolen_vga_memory BO in KMD
code, so it should be safe.
It seems we have to add a new parameter for amdgpu_bo_create_kernel() to pass
the prefer region.
Thanks!
Rico
__
It seems we have to add a new parameter for amdgpu_bo_create_kernel() to pass
the prefer region.
You can also just pass a cpu pointer to the function allocating the
stolen_vga_memory.
That's probably less work to change all callers and cleaner in general.
Christian.
Am 28.08.19 um 12:21 schri
Great! That's good idea!
Thanks!
From: Koenig, Christian
Sent: Wednesday, August 28, 2019 18:25
To: Yin, Tianci (Rico) ; amd-gfx@lists.freedesktop.org
Cc: Xu, Feifei ; Ma, Le ; Xiao, Jack
; Zhang, Hawking
Subject: Re: [PATCH] drm/amdgpu/psp: keep TMR in visibl
From: "Tianci.Yin"
stolen memory should be fixed in visible region.
Change-Id: Icbbbd39fd113e93423aad8d2555f4073c08020e5
Signed-off-by: Tianci.Yin
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
From: "Tianci.Yin"
Fix compute ring test failure in sriov scenario.
Signed-off-by: Tianci.Yin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 14 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 +
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amd
Might be better to use a local variable for the CPU pointer instead of
duplicating the calling parameters.
Local variable can't be used in cleaner.
From: Christian K?nig
Sent: Wednesday, August 28, 2019 17:57
To: Yin, Tianci (Rico) ; amd-gfx@lists.freedesktop.o
That's irrelevant in this case. CPU mapping's are destroyed automatically when
the BO is freed.
Giving the CPU pointer to the free function is only for extra checking that we
can't access it anymore.
Christian.
Am 28.08.2019 13:05 schrieb "Yin, Tianci (Rico)" :
Might be better to use a local v
From: "Tianci.Yin"
Fix compute ring test failure in sriov scenario.
Change-Id: I141d3d094e2cba9bcf2f6c96f4d8c4ef43c421c3
Signed-off-by: Tianci.Yin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/am
From: "Tianci.Yin"
stolen memory should be fixed in visible region.
Change-Id: Icbbbd39fd113e93423aad8d2555f4073c08020e5
Signed-off-by: Tianci.Yin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 6 --
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 ++-
2 files changed, 6 insertions(+), 3 deleti
I checked the code, cpu pointer indeed only used for checking.
Thanks for your suggestions!
From: Koenig, Christian
Sent: Wednesday, August 28, 2019 19:08
To: Yin, Tianci (Rico)
Cc: amd-gfx@lists.freedesktop.org ; Xu, Feifei
; Ma, Le ; Xiao, Jack ;
Zhang, Hawk
call helper function in late init phase to handle ras init
for gfx ip block
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 90 ---
1 file changed, 19 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/dr
call ras_late_init helper function to do ras init for sdma block
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 96 --
1 file changed, 22 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/
call amdgpu_ras_late_init to do ras init for gmc v9 block
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 155 ++
1 file changed, 43 insertions(+), 112 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd
In late_init for ras, the helper function will be used to
1). disable ras feature if the IP block is masked as disabled
2). send enable feature command if the ip block was masked as enabled
3). create debugfs/sysfs node per IP block
4). register interrupt handler
Signed-off-by: Hawking Zhang
---
The function will be called in late init phase to do mmhub
ras init
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 21 ++---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 28
invoke nbio ras_late_init callback function to do nbio ras init
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index e7f
ras_late_init callback function will be used to do common ras
init in late init phase.
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 2 ++
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 41
2 files changed, 43 insertions(+)
diff --git
> Yeah but sadly it seems it is possible to only increase the BAR size from its
> currently default 256MB.
Well the specification allows to change the BAR size from 1MB up to
several TB. The key point is we usually use it to increase the BAR size,
but it is perfectly possible to make it smaller
Am 28.08.19 um 13:40 schrieb Tianci Yin:
From: "Tianci.Yin"
Fix compute ring test failure in sriov scenario.
Change-Id: I141d3d094e2cba9bcf2f6c96f4d8c4ef43c421c3
Signed-off-by: Tianci.Yin
Reviewed-by: Christian König for both patches.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 15 ++
Dne 28. 08. 19 v 10:31 Christian König napsal(a):
> Hi Petr,
>
> well that is indeed a rather unusual use case.
>
> I'm not 100% sure how you actually hacked the HD4550 to do what you want to
> do, cause this ASIC generation shouldn't support this.
I don't remember correctly how exactly I've ma
No need to add new asic cases. This is a sw display
implementation, so just drop the error message so when
we add new asics, all we have to do is add the virtual
dce IP module.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 11 +--
1 file changed, 1 insertion
Dne 28. 08. 19 v 15:06 Koenig, Christian napsal(a):
>> Yeah but sadly it seems it is possible to only increase the BAR size from
>> its currently default 256MB.
>
> Well the specification allows to change the BAR size from 1MB up to
> several TB. The key point is we usually use it to increase th
Ping
Andrey
On 8/27/19 2:17 PM, Andrey Grodzovsky wrote:
> This should be checked at all places job is accessed.
>
> Signed-off-by: Andrey Grodzovsky
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu
It partially reverts the regression of
commit e4a67e6cf14c258619f
("drm/amdgpu/psp: move TMR to cpu invisible vram region")
which causes gfx ib test failed when driver loading
in sriov system.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 16
drivers/
On Wed, Aug 14, 2019 at 12:44:59PM +0200, Dariusz Marcinkiewicz wrote:
> Pass the connector info to the CEC adapter. This makes it possible
> to associate the CEC adapter with the corresponding drm connector.
>
> Signed-off-by: Dariusz Marcinkiewicz
> Signed-off-by: Hans Verkuil
> Tested-by: Han
From: Prike Liang
add the get_dpm_ultimate_freq for supporting different swSMU.
-v2:
Handle the unsupported clock type and read smc message failed case and
return error code.
Move the smu12 uclk frequency retrieved logic to renoir ppt.
-v3:
Use goto clause to handle inval
From: Prike Liang
There is no driver message to enable/disable feature mask for APU.
For the sake of APU reusing swSMU interface and assume APU supports all
the feature.
Signed-off-by: Prike Liang
Reviewed-by: Evan Quan
Reviewed-by: Aaron Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/
From: Prike Liang
Should populate DPM clocks tables during hw init,otherwise will
suffer from invalidate table.
Signed-off-by: Prike Liang
Reviewed-by: Evan Quan
Reviewed-by: Aaron Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 3 ---
1 file changed, 3 dele
From: Prike Liang
Init SDMA HW base configuration and enable idle INT for rn.
Signed-off-by: Prike Liang
Reviewed-by: Aaron Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b
Comparing adev->family with CHIP constants is not correct.
adev->family can only be compared with AMDGPU_FAMILY constants and
adev->asic_type is the struct member to compare with CHIP constants.
They are separate identification spaces.
Signed-off-by: Jean Delvare
Fixes: 62a37553414a ("drm/amdgpu:
It can't break an older driver, because there is no older driver that
requires the static allocation.
Note that closed source drivers don't count, because they don't need
backward compatibility.
Marek
On Wed, Aug 28, 2019 at 2:44 AM zhoucm1 wrote:
>
> On 2019/7/23 上午3:08, Christian König wrote
Nice clean up. Series is:
Reviewed-by: Alex Deucher
From: Hawking Zhang
Sent: Wednesday, August 28, 2019 9:03 AM
To: amd-gfx@lists.freedesktop.org ; Zhou1, Tao
; Deucher, Alexander
Cc: Zhang, Hawking
Subject: [PATCH 7/7] drm/amdgpu: switch to ras_late_init cal
dcn20_resource.c:2636:9: error: missing braces around initializer
[-Werror=missing-braces]
struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES]
= {0};
^
Fixes: 7ed4e6352c16f ("drm/amd/display: Add DCN2 HW Sequencer and Resource")
Signed-off-by: Raul E Rangel
-
On Wed, Aug 28, 2019 at 2:51 PM Randy Dunlap wrote:
>
> On 8/27/19 8:40 PM, a...@linux-foundation.org wrote:
> > The mm-of-the-moment snapshot 2019-08-27-20-39 has been uploaded to
> >
> >http://www.ozlabs.org/~akpm/mmotm/
> >
> > mmotm-readme.txt says
> >
> > README for mm-of-the-moment:
> >
DP 1.4a specification defines Link Training Tunable PHY Repeater (LTTPR)
which is required to add support for systems with Thunderbolt or other
repeater devices.
Changes since V2:
- Drop the kernel-doc comment
- Reorder LTTPR according to register offset
Changes since V1:
- Adjusts registers names
From: Bhawanpreet Lakha
Provides the interface to configure display interrrupts on renoir.
Signed-off-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/irq/Makefile | 10 +
.../display/dc/irq/dcn21/irq_service_dcn21.c | 372 ++
.../displa
This patch set adds initial DC display support for
Renoir. Renoir is a new APU.
I have omitted the register patch due to size. The
full tree is available here:
https://cgit.freedesktop.org/~agd5f/linux/log/?h=amd-staging-drm-next-renoir-dc
Bhawanpreet Lakha (20):
drm/amd/display: Add Renoir
From: Bhawanpreet Lakha
Signed-off-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../drm/amd/display/dc/dcn10/dcn10_hubbub.h | 73 +++
.../drm/amd/display/dc/dcn20/dcn20_hubbub.h | 10 +++
.../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 35 +
3 files changed
From: Bhawanpreet Lakha
Signed-off-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/dce/dce_hwseq.h| 97 +++
1 file changed, 97 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
b/drivers/gpu/drm/amd/display/dc/dce/d
From: Bhawanpreet Lakha
This defines the interface for communicating requirements
between DC and powerplay.
Signed-off-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 47 ++
1 file changed, 47 insertions(+)
diff --git a/d
From: Bhawanpreet Lakha
This provides the interface to memory for the display hw.
v2: minor cleanup (Alex)
Signed-off-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 10 +
.../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 244 +
From: Bhawanpreet Lakha
Signed-off-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../drm/amd/display/dc/dce/dce_clock_source.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
b/drivers/gpu/drm/amd/display/d
From: Bhawanpreet Lakha
Controls display clocks and interfaces with powerplay for
clock and power requirements.
Signed-off-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/clk_mgr/Makefile | 10 +
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 9 +
.../am
From: Bhawanpreet Lakha
Misc display related configuration details.
Signed-off-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/gpio/Makefile | 7 +
.../display/dc/gpio/dcn21/hw_factory_dcn21.c | 210 ++
.../display/dc/gpio/dcn21/hw_factory_dcn2
From: Bhawanpreet Lakha
rename VM_CONTEXT0 to MMVM_CONTEXT0 as that is the name defined in
the register files
Signed-off-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
From: Bhawanpreet Lakha
Add a kconfig option to enable renoir.
Signed-off-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/Kconfig
b/drivers/gpu/drm/amd/display/Kc
From: Roman Li
Need to check for renoir first.
Signed-off-by: Roman Li
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
b/drivers/
From: Bhawanpreet Lakha
add Renoir DCN version in DC and handle it
Signed-off-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../drm/amd/display/dc/bios/command_table_helper2.c | 5 +
drivers/gpu/drm/amd/display/dc/core/dc_resource.c| 12
drivers/gpu/drm/amd/disp
From: Bhawanpreet Lakha
Signed-off-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/include/dal_asic_id.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
b/drivers/gpu/drm/amd/display/include/dal_asic_
From: Bhawanpreet Lakha
Enable the building of dcn21 support.
Signed-off-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/Makefile | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
b/drivers/gpu/drm/amd/display/
From: Bhawanpreet Lakha
Manages the renoir display resources (crtcs, phys, plls, etc.).
v2: rebase (Alex)
Signed-off-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn21/Makefile |2 +-
.../drm/amd/display/dc/dcn21/dcn21_resource.c | 1680 +++
From: Bhawanpreet Lakha
Controls the display hw's interface to memory.
v2: rebase (Alex)
Signed-off-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 2 +-
.../drm/amd/display/dc/dcn21/dcn21_hubbub.c | 595 ++
.../drm/am
From: Roman Li
Hook up the DML changes for renoir.
Signed-off-by: Roman Li
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dml/Makefile | 4
.../drm/amd/display/dc/dml/display_mode_lib.c | 19 +++
2 files changed, 23 insertions(+)
diff --git a/drivers/g
From: Bhawanpreet Lakha
Add missing parameters, to make dcn21 compile
without errors
Signed-off-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dc.h | 3 +++
drivers/gpu/drm/amd/display/dc/inc/core_types.h | 3 +++
drivers/gpu/drm/amd/displ
From: Bhawanpreet Lakha
Hook up renoir support to KMS.
v2: squash in "Fixes for Renoir in amdgpu_dm"
Signed-off-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/
From: Roman Li
Enable DC support for renoir.
Signed-off-by: Roman Li
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
drivers/gpu/drm/amd/amdgpu/soc15.c | 6 ++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_devi
From: Bhawanpreet Lakha
call update_bw_bounding_box in DC construct
Signed-off-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/core/dc.c| 5 +
drivers/gpu/drm/amd/display/dc/inc/core_types.h | 5 +
2 files changed, 10 insertions(+)
diff --
On 08/27, Jani Nikula wrote:
> On Mon, 26 Aug 2019, "Siqueira, Rodrigo" wrote:
> > DP 1.4a specification defines Link Training Tunable PHY Repeater (LTTPR)
> > which is required to add support for systems with Thunderbolt or other
> > repeater devices.
> >
> > Changes since V1:
> > - Adjusts regis
Problem:
Under certain conditions, when some IP bocks take a RAS error,
we can get into a situation where a GPU reset is not possible
due to issues in RAS in SMU/PSP.
Temporary fix until proper solution in PSP/SMU is ready:
When uncorrectable error happens the DF will unconditionally
broadcast err
In case of RAS error allow user configure auto system
reboot through ras_ctrl.
This is also part of the temproray work around for the RAS
hang problem.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 18 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
On Wed, Aug 28, 2019 at 4:32 AM Jean Delvare wrote:
>
> The driver does not support these sensors yet and there is no point in
> creating sysfs attributes which will always return an error.
>
> Signed-off-by: Jean Delvare
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: "David (ChunMing) Zhou"
On Wed, Aug 28, 2019 at 11:28 AM Jean Delvare wrote:
>
> Comparing adev->family with CHIP constants is not correct.
> adev->family can only be compared with AMDGPU_FAMILY constants and
> adev->asic_type is the struct member to compare with CHIP constants.
> They are separate identification spaces.
Summary Of Changes
*add surface registers
*underflow fixes
*i2c/aux refactors
*DSC fixes
Alvin Lee (1):
drm/amd/display: Don't allocate payloads if link lost
Anthony Koo (1):
drm/amd/display: 3.2.49
Bayan Zabihiyan (1):
drm/amd/display: Isolate DSC module from driver dependencies
Charlene
From: Alvin Lee
We should not allocate payloads if the link is lost until the link is retrained.
Some displays require this.
Signed-off-by: Alvin Lee
Reviewed-by: Wenjing Liu
Acked-by: Bhawanpreet Lakha
---
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 10 +-
drivers/gpu/drm/amd/
From: Ilya Bakoulin
[Why]
DML diags tests are failing because the struct contents get
clobbered by a memcpy.
[How]
Remove the memcpy call.
Signed-off-by: Ilya Bakoulin
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 1 -
From: Dmytro Laktyushkin
Remove code used to allow compilation error free
interface change.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 29
1 file changed, 29 deletions(-)
dif
From: Bayan Zabihiyan
[Why]
Edid Utility wishes to include DSC module from driver instead
of doing it's own logic which will need to be updated every time
someone modifies the driver logic.
[How]
Modify some functions such that we dont need to pass the entire
DC structure as parameter.
-Remove D
From: Qingqing Zhuo
Signed-off-by: Qingqing Zhuo
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
---
.../amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c | 8
.../display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c| 8
.../drm/amd/display/dc/dml/dml1_display_rq_dlg
From: Dmytro Laktyushkin
New behaviour will track global updates and update any hw that isn't
related to current stream being updated.
This should fix any issues caused by pipe split pipes being taken
by other streams.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Charlene Liu
Acked-by: Bhaw
From: Nikola Cornij
[why]
It's sometimes useful to have this option when debugging
[how]
Add a config flag. If the flag is not set, use driver default policy.
If the flag is set, use the value from the flag as the starting DSC slice
height.
Signed-off-by: Nikola Cornij
Reviewed-by: Martin Leun
From: Ilya Bakoulin
[Why]
- Need to add missing surface address register definitions.
- RGBE+A does not work in a stereo configuration because
surface addresses are no programmed correctly.
[How]
Added the register definitions and surface address programming.
Signed-off-by: Ilya Bakoulin
Rev
From: Jaehyun Chung
[Why] Underflow occurs on some display setups(repro'd on 3x4K HDR) on boot,
mode set, and hot-plugs with. Underflow occurs because mem clk
is not set high after disabling pstate switching. This behaviour occurs
because some calculations assumed displays were synchronized.
[Ho
From: Vitaly Prosyak
[Why & How]
Use dcn2 blender, shaper, 3dlut registers
Signed-off-by: Vitaly Prosyak
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
Acked-by: Vitaly Prosyak
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h | 84 +++
.../drm/amd/display/dc/dcn20/dc
From: Lewis Huang
[Why]
When user mode use i2c over aux through ADL or DDI, the function
dal_ddc_service_query_ddc_data will be called. There are two issues.
1. When read/write length > 16byte, current always return false because
the DEFAULT_AUX_MAX_DATA_SIZE != length.
2. When usermode only nee
From: Krunoslav Kovac
[Why&How]
Driver defaults to 1-tap subsample mode for 4:2:2.
DCE11.2 added 3-tap. The policy is:
DCE8-DCE11 - change to 2-tap, it's better than 1-tap.
DCE11.2+ - use 3-tap
Note that 4:2:0 was added in DCE11.2 and already uses 3-tap always.
Note 2 is that DCE not covered on
From: Anthony Koo
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 3d32e9
From: Jun Lei
[why]
dc_destroy should only clean up SW, this is because GPUs may be
removed before driver unload, leading to HW to be unavailable.
[how]
remove GPIO close as part of GPIO destroy, this is unnecessary because
GPIO is not shared, and GPIOs are generally closed after being opened
A
From: Jing Zhou
[Why]
DP1.2 LL CTS test failure.
[How]
The failure is caused by not verify stream link is equal
to link, only check stream and link is not null.
Signed-off-by: Jing Zhou
Reviewed-by: Wenjing Liu
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss
From: Nikola Cornij
[why]
The requirement has been clarified and only DSC 4:2:2 Native has to
be disabled.
Signed-off-by: Nikola Cornij
Reviewed-by: Wenjing Liu
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
From: Charlene Liu
[Description]
1. OUTSTANDING_REQUEST_LIMIT update from 0xFF to 0x1F (HW doc update)
2. using memory type to convert UMC's MCLK to Yclk.
Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
.../display/dc/clk_mgr/dce110/dce110_clk_mgr.
On 2019-08-28 4:00 p.m., Andrey Grodzovsky wrote:
> Problem:
> Under certain conditions, when some IP bocks take a RAS error,
> we can get into a situation where a GPU reset is not possible
> due to issues in RAS in SMU/PSP.
>
> Temporary fix until proper solution in PSP/SMU is ready:
> When uncor
On 8/28/19 5:18 PM, Kuehling, Felix wrote:
> On 2019-08-28 4:00 p.m., Andrey Grodzovsky wrote:
>> Problem:
>> Under certain conditions, when some IP bocks take a RAS error,
>> we can get into a situation where a GPU reset is not possible
>> due to issues in RAS in SMU/PSP.
>>
>> Temporary fix unti
From: Colin Ian King
There is a spelling mistake in a DRM_DEBUG_DRIVER debug message.
Fix it.
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
b/d
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Hawking Zhang
Sent: Wednesday, August 28, 2019 9:03 PM
To: amd-gfx@lists.freedesktop.org; Zhou1, Tao ; Deucher,
Alexander
Cc: Zhang, Hawking
Subject: [PATCH 7/7] drm/amdgpu: switch to ras_late_init callback for nbio v7_4
i
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
> On Aug 28, 2019, at 9:56 PM, Alex Deucher wrote:
>
> No need to add new asic cases. This is a sw display
> implementation, so just drop the error message so when
> we add new asics, all we have to do is add the virtual
> dce IP module.
>
> Signed-off-b
Hi Dave, Daniel,
A few fixes for 5.3. Nothing too major.
The following changes since commit 7837951a12fdaf88d2c51ff0757980c00072790c:
drm/mediatek: include dma-mapping header (2019-08-24 15:09:20 +1000)
are available in the Git repository at:
git://people.freedesktop.org/~agd5f/linux tags
> -Original Message-
> From: Hawking Zhang
> Sent: 2019年8月28日 21:03
> To: amd-gfx@lists.freedesktop.org; Zhou1, Tao ;
> Deucher, Alexander
> Cc: Zhang, Hawking
> Subject: [PATCH 1/7] drm/amdgpu: add helper function to do common
> ras_late_init
>
> In late_init for ras, the helper func
From: "Tianci.Yin"
stolen memory should be fixed in visible region.
Change-Id: Icbbbd39fd113e93423aad8d2555f4073c08020e5
Signed-off-by: Tianci.Yin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 6 --
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 ++-
2 files changed, 6 insertions(+), 3 deleti
From: "Tianci.Yin"
Fix compute ring test failure in sriov scenario.
Change-Id: I141d3d094e2cba9bcf2f6c96f4d8c4ef43c421c3
Signed-off-by: Tianci.Yin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/
Hi Christian,
Thank you very much for your suggestions!
A little more improvement have made about the patch1, please review again.
BTW, any suggestion about the patch2?
Rico
From: Christian König
Sent: Wednesday, August 28, 2019 21:09
To: Yin, Tianci (Rico) ; a
Applied. Thanks!
Alex
On Wed, Aug 28, 2019 at 8:52 PM Colin King wrote:
>
> From: Colin Ian King
>
> There is a spelling mistake in a DRM_DEBUG_DRIVER debug message.
> Fix it.
>
> Signed-off-by: Colin Ian King
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 2 +-
> 1 file changed, 1
> -Original Message-
> From: amd-gfx On Behalf Of
> Hawking Zhang
> Sent: 2019年8月28日 21:03
> To: amd-gfx@lists.freedesktop.org; Zhou1, Tao ;
> Deucher, Alexander
> Cc: Zhang, Hawking
> Subject: [PATCH 2/7] drm/amdgpu: switch to amdgpu_ras_late_init for gfx v9
> block
>
> call helper f
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