From: Bhawanpreet Lakha <bhawanpreet.la...@amd.com>

Add missing parameters, to make dcn21 compile
without errors

Signed-off-by: Bhawanpreet Lakha <bhawanpreet.la...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h               | 3 +++
 drivers/gpu/drm/amd/display/dc/inc/core_types.h   | 3 +++
 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 4 ++++
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 1 +
 4 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 42b6a6e41c0b..a82352a87808 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -385,6 +385,9 @@ struct dc_debug_options {
        struct dc_bw_validation_profile bw_val_profile;
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
        bool disable_fec;
+#endif
+#ifdef CONFIG_DRM_AMD_DC_DCN2_1
+       bool disable_48mhz_pwrdwn;
 #endif
        /* This forces a hard min on the DCFCLK requested to SMU/PP
         * watermarks are not affected.
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h 
b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 8726bd7dd910..f189307750ab 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -87,6 +87,9 @@ void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool 
enable);
 struct resource_pool;
 struct dc_state;
 struct resource_context;
+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+struct clk_bw_params;
+#endif
 
 struct resource_funcs {
        void (*destroy)(struct resource_pool **pool);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
index 7193acfcd779..e8668388581b 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
@@ -40,6 +40,10 @@ struct cstate_pstate_watermarks_st {
 struct dcn_watermarks {
        uint32_t pte_meta_urgent_ns;
        uint32_t urgent_ns;
+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+       uint32_t frac_urg_bw_nom;
+       uint32_t frac_urg_bw_flip;
+#endif
        struct cstate_pstate_watermarks_st cstate_pstate;
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 732a93df1844..3a938cd414ea 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -48,6 +48,7 @@ struct dce_hwseq_wa {
        bool DEGVIDCN10_253;
        bool false_optc_underflow;
        bool DEGVIDCN10_254;
+       bool DEGVIDCN21;
 };
 
 struct hwseq_wa_state {
-- 
2.20.1

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