; Yang, Stanley ; Liu, Xiang(Dean)
Subject: [PATCH] drm/amdgpu: Use correct gfx deferred error count
In the case of parsing GFX deferred error from SMU corrected error channel, the
error count should be set to 1 instead of parsing from
MISC0 register, which is 0.
Signed-off-by: Xiang Liu
In the case of parsing GFX deferred error from SMU corrected error
channel, the error count should be set to 1 instead of parsing from
MISC0 register, which is 0.
Signed-off-by: Xiang Liu
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
di
