[PATCH] drm/amdgpu: Use correct gfx deferred error count

[Xiang Liu]

In the case of parsing GFX deferred error from SMU corrected error
channel, the error count should be set to 1 instead of parsing from
MISC0 register, which is 0.

Signed-off-by: Xiang Liu <xiang....@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index a58e2ce4deb5..e84238336fb6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -898,9 +898,10 @@ static int gfx_v9_4_3_aca_bank_parser(struct aca_handle 
*handle,
                break;
        case ACA_SMU_TYPE_CE:
                bank->aca_err_type = ACA_BANK_ERR_CE_DE_DECODE(bank);
-               ret = aca_error_cache_log_bank_error(handle, &info,
-                                                    bank->aca_err_type,
-                                                    
ACA_REG__MISC0__ERRCNT(misc0));
+               ret = aca_error_cache_log_bank_error(handle, &info, 
bank->aca_err_type,
+                       (bank->aca_err_type == ACA_ERROR_TYPE_CE) ?
+                               ACA_REG__MISC0__ERRCNT(misc0) :
+                               1);
                break;
        default:
                return -EINVAL;
-- 
2.34.1