Re: [PATCH 4/4] drm/amdkfd: Add sdma allocation debug message

2018-11-13 Thread ozeng
Hi Alex, Those 4 patches internally passed Felix's code review. Those are required for MI100 but are general changes so I think it is better to check into drm-next. Thanks, Oak On 11/13/2018 02:11 PM, Zeng, Oak wrote: > From: Oak Zeng > > Change-Id: I47ec79eceac810f7031eaf88d267fc8370501c2

Re: [PATCH 1/2] drm/amdgpu: Moved fault hash table to amdgpu vm

2018-09-06 Thread ozeng
Hi Christian, In this implementation, fault hash is made per vm, not per pasid as suggested, based on below considerations: * Delay the destroy of hash introduces more effort like how to set the proper grace period after which no retry interrupt will be generated. We want to avoid those

[PATCH] drm/amdgpu: Fixed a potential circular lock

2017-09-29 Thread ozeng
The dead circular lock senario captured is as followed. The idea of the fix is moving read_user_wptr outside of acquire_queue...release_queue critical section [ 63.477482] WARNING: possible circular locking dependency detected [ 63.484091] 4.12.0-kfd-ozeng #3 Not tainted [ 63.488531

[PATCH] drm/amdgpu: Changed CU reservation golden settings

2017-06-27 Thread ozeng
With previous golden settings, compute task can't use reserved LDS (32K) on CU0 and CU1. On 64K LDS system, if compute work group allocate more than 32K LDS, then it can't be dispatched to CU0 and CU1 because of the reservation. This enables compute task to use reserved LDS on CU0 and CU1. Signed-

[PATCH] drm/amdgpu: Added more hqd debug messages v2

2017-03-01 Thread ozeng
Dump register COMPUTE_PGM_RSRC1 and COMPUTE_PGM_RSRC2 in function kgd_hqd_dump v2: Update HQD_N_REGS (the number of registers dumped) accordingly Change-Id: I8e007f5bcc095d3283b642791860dd072dd43b1c Signed-off-by: Oak Zeng --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 4 +++- drivers/

[PATCH] drm/amdgpu: Added more hqd debug messages

2017-03-01 Thread ozeng
Dump register COMPUTE_PGM_RSRC1 and COMPUTE_PGM_RSRC2 in function kgd_hqd_dump Change-Id: I8e007f5bcc095d3283b642791860dd072dd43b1c Signed-off-by: Oak Zeng --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 2 ++ 2 files changed, 4 i

[PATCH] drm/amdgpu: Initialize pipe priority order on graphic initialization

2017-02-12 Thread ozeng
Initialized PIPE_ORDER_TS0/1/2/3 field of SPI_ARB_PRIORITY register to 2. This set the pipe priority order to: 02 - HP3D, CS_H, GFX, CS_M, CS_L Change-Id: I1e89a2fdcf45a99808f0f5b3cbd83ae537174023 Signed-off-by: Oak Zeng --- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 8 drivers/gpu/drm/amd