Port this change to vega20_ih.c:
"89ae318001e5 drm/amdgpu: clear RB_OVERFLOW bit when enabling interrupts"
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 27 ++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/v
SRIOV does not need to wait for IFWI init, and MP0_C2PMSG_33 is blocked
for VF access.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 26 ++-
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu
GFX and SDMA is not properly deinitialized under SRIOV.
Remove amdgpu_sriov_vf() guards to allow VF to deinitialize correctly.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 7 +--
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 9 -
2 files changed, 9
IH_CHICKEN is blocked for VF writes; this access should be skipped.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 38 ++
1 file changed, 20 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
b/drivers/gpu/drm/amd
The current error detection only looks for a timeout.
This should be changed to also check scratch_reg1 for any errors
returned from RLCG.
v2: remove new error value
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 5 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 1
VM_L2_CNTL* should not be programmed on driver unload under SRIOV.
These regs are skipped during SRIOV driver init.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu
Under SRIOV, programming to VM_CONTEXT*_CNTL regs failed because the
current macro does not pass through the correct xcc instance.
Use the *REG32_XCC macro in this case.
The behaviour without SRIOV is the same.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8
1
VF should not program this register.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 00b21ece081f..30cc155f20d4 100644
--- a
The current error detection only looks for a timeout.
This should be changed to also check scratch_reg1 for any errors
returned from RLCG.
Also add a new error value.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 8 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
MC_VM_AGP_* registers should not be programmed by guest driver.
v2: move early return outside of loop
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
b
The following regs can only be programmed by the PF:
HDP_MISC_CNTL
HDP_NONSURFACE_BASE
HDP_NONSURFACE_BASE_HI
v2: update commit message
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu
This register is blocked for VF access.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
index 3f3a6445c006..bf3bdf67abb7 100644
--- a
PCTL0_MMHUB_DEEPSLEEP_IB is blocked for VF access
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
MC_VM_AGP_* registers should not be programmed by guest driver.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
index
;
v3: xcc not needed for MMMHUB
v2: rebase
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 5 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 3 ++-
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c| 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c| 2 +-
drivers/gpu/drm/
W/RREG32_RLC is hardedcoded to use instance 0. W/RREG32_SOC15_RLC
should be used instead when inst != 0.
v2: rebase
Signed-off-by: Victor Lu
---
.../drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 38 --
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 40
The "rlcg_reg_access_supported" flag is missing. Add it back in.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index a1
condition in amdgpu_device_xcc_w/rreg, remove trace func call
v4: avoid using amdgpu_sriov_w/rreg
v3: use W/RREG32_XCC to handle non-kiq case
v2: define amdgpu_device_xcc_wreg/rreg instead of changing parameters
of amdgpu_device_wreg/rreg
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd
: avoid using amdgpu_sriov_w/rreg
v3: use W/RREG32_XCC to handle non-kiq case
v2: define amdgpu_device_xcc_wreg/rreg instead of changing parameters
of amdgpu_device_wreg/rreg
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 13 ++-
.../drm/amd/amdgpu
;
v3: xcc not needed for MMMHUB
v2: rebase
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 5 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 3 ++-
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c| 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c| 2 +-
drivers/gpu/drm/
W/RREG32_RLC is hardedcoded to use instance 0. W/RREG32_SOC15_RLC
should be used instead when inst != 0.
v2: rebase
Signed-off-by: Victor Lu
---
.../drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 38 --
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 40
The "rlcg_reg_access_supported" flag is missing. Add it back in.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index a1
;
v3: xcc not needed for MMMHUB
v2: rebase
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 5 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 3 ++-
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c| 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c| 2 +-
drivers/gpu/drm/
W/RREG32_RLC is hardedcoded to use instance 0. W/RREG32_SOC15_RLC
should be used instead when inst != 0.
v2: rebase
Signed-off-by: Victor Lu
---
.../drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 38 --
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 40
amdgpu_virt_kiq_reg_write_reg_wait is hardcoded to use MEC engine 0.
Add xcc_inst as a parameter to allow it to use different MEC engines.
v3: use first xcc for MMHUB in gmc_v9_0_flush_gpu_tlb
v2: rebase
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 5 +++--
drivers
: avoid using amdgpu_sriov_w/rreg
v3: use W/RREG32_XCC to handle non-kiq case
v2: define amdgpu_device_xcc_wreg/rreg instead of changing parameters
of amdgpu_device_wreg/rreg
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 13 ++-
.../drm/amd/amdgpu
The WREG32/RREG32_SOC15_IP_NO_KIQ call is using XCC0's RLCG interface
when programming other XCCs.
Add xcc instance parameter to them.
v3: xcc not needed for MMMHUB
v2: rebase
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 16
drivers/gpu/dr
W/RREG32_RLC is hardedcoded to use instance 0. W/RREG32_SOC15_RLC
should be used instead when inst != 0.
Signed-off-by: Victor Lu
---
.../drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 38 --
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 40 +--
drivers/gpu/drm
amdgpu_virt_kiq_reg_write_reg_wait is hardcoded to use MEC engine 0.
Add xcc_inst as a parameter to allow it to use different MEC engines.
v2: rebase
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 5 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 3 ++-
drivers/gpu
parameters
of amdgpu_device_wreg/rreg
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 13 ++-
.../drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 2 +-
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 84
The WREG32/RREG32_SOC15_IP_NO_KIQ call is using XCC0's RLCG interface
when programming other XCCs.
Add xcc instance parameter to them.
v2: rebase
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 16
drivers/gpu/drm/amd/amdgpu/soc15_common.h
The "rlcg_reg_access_supported" flag is missing. Add it back in.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 41
d xcc instance parameter to *REG32_RLC"
Signed-off-by: Victor Lu
---
.../drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 41 +--
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 34 +++
drivers/gpu/drm/amd/amdgpu/soc15_common.h | 8 +++-
3 files changed, 44 inserti
gfx_v9_4_3_xcc_set_compute_eop_interrupt_state should use
*REG32_RLC_XCC so CP_ME1_PIPE0_INT_CNTL registers can be accessed
under SRIOV.
v2: Use RREG32_RLC_XCC
Original v1 title: "drm/amdgpu: Use *REG32_RLC in gfx_v9_4_3.c"
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/gf
amdgpu_virt_kiq_reg_write_reg_wait is hardcoded to use MEC engine 0.
Add xcc_inst as a parameter to allow it to use different MEC engines.
v2: rebase
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 5 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 3 ++-
drivers/gpu
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 13 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 76 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 8 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h| 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
The WREG32/RREG32_SOC15_IP_NO_KIQ call is using XCC0's RLCG interface
when programming other XCCs.
Add xcc instance parameter to them.
v2: rebase
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 16
drivers/gpu/drm/amd/amdgpu/soc15_common.h
The "rlcg_reg_access_supported" flag is missing. Add it back in.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index fb
amdgpu_kiq_wreg/rreg is hardcoded to use MEC engine 0.
Add an "xcc_id" parameter to them so its uses the correct XCD's engine
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 24 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +++
gfx_v9_4_3_xcc_set_compute_eop_interrupt_state should use *REG32_RLC
so CP_ME1_PIPE0_INT_CNTL registers can be accessed with SRIOV.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm
WREG32/RREG32_RLC should specify the instance so the correct XCC's RLCG
interface can be used.
Signed-off-by: Victor Lu
---
.../drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c | 4 +--
.../drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 25 +++
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_
The "rlcg_reg_access_supported" flag is missing. Add it back in.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index a8
amdgpu_virt_kiq_reg_write_reg_wait is hardcoded to use MEC engine 0.
Add xcc_inst as a parameter to allow it to use different MEC engines.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 5 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 3 ++-
drivers/gpu/drm/amd
The WREG32/RREG32_SOC15_IP_NO_KIQ call is using XCC0's RLCG interface
when programming other XCCs.
Add inst parameter to them.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 16
drivers/gpu/drm/amd/amdgpu/soc15_common.h | 6 +++---
2 files ch
An instance of for_each_inst() was not changed to match its new
behaviour and is causing a loop.
v2: remove tmp_mask variable
Fixes: 50c1d81d6365 ("drm/amdgpu: Modify for_each_inst macro")
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 5 +-
scripts/packag
An instance of for_each_inst() was not changed to match its new
behaviour and is causing a loop.
Fixes: 50c1d81d6365 ("drm/amdgpu: Modify for_each_inst macro")
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/d
Add RLCG interface support for gfx v9.4.3 and multiple XCCs.
Do not enable it yet.
v2: Fix amdgpu_rlcg_reg_access_ctrl init, add support for multiple XCCs
in amdgpu_mm_wreg_mmio_rlc
v3: Use GET_INST() when indexing amdgpu_rlcg_reg_access_ctrl
Signed-off-by: Victor Lu
---
drivers/gpu/drm
Add RLCG interface support for gfx v9.4.3 and multiple XCCs.
Do not enable it yet.
v2: Fix amdgpu_rlcg_reg_access_ctrl init, add support for multiple XCCs
in amdgpu_mm_wreg_mmio_rlc
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
drivers/gpu/drm/amd/amdgpu
Add RLCG interface support for gfx v9.4.3 and multiple XCCs.
Do not enable it yet.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h| 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 17 --
drivers/gpu/drm/amd
[why]
Enabling drm.debug=0x4 can flood the dmesg due to prints on every cursor
update or page flip.
[how]
Define and use pr_debug macros instead of a few spammy DRM_DEBUG_*'s.
Signed-off-by: Victor Lu
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 +--
.../dr
2f5e3683>] bus_for_each_dev+0x6a/0xc0
[<a1cfc897>] driver_attach+0x1e/0x20
Fixes: a8e30005b47a ("drm/amd/display/dc/core/dc_link: Move some local
data from the stack to the heap")
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 1 +
1 fil
51 matches
Mail list logo
