[PATCH 6/6] drm/amdgpu: Use *REG32_RLC_XCC in gfx_v9_4_3.c (v2)

[Victor Lu]

gfx_v9_4_3_xcc_set_compute_eop_interrupt_state should use
*REG32_RLC_XCC so CP_ME1_PIPE0_INT_CNTL registers can be accessed
under SRIOV.

v2: Use RREG32_RLC_XCC

Original v1 title: "drm/amdgpu: Use *REG32_RLC in gfx_v9_4_3.c"

Signed-off-by: Victor Lu <victorchengchi...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index e7543bc49ee5..c010e80adb99 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -2739,16 +2739,16 @@ static void 
gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
 
        switch (state) {
        case AMDGPU_IRQ_STATE_DISABLE:
-               mec_int_cntl = RREG32(mec_int_cntl_reg);
+               mec_int_cntl = RREG32_RLC_XCC(mec_int_cntl_reg, xcc_id);
                mec_int_cntl = REG_SET_FIELD(mec_int_cntl, 
CP_ME1_PIPE0_INT_CNTL,
                                             TIME_STAMP_INT_ENABLE, 0);
-               WREG32(mec_int_cntl_reg, mec_int_cntl);
+               WREG32_RLC_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id);
                break;
        case AMDGPU_IRQ_STATE_ENABLE:
-               mec_int_cntl = RREG32(mec_int_cntl_reg);
+               mec_int_cntl = RREG32_RLC_XCC(mec_int_cntl_reg, xcc_id);
                mec_int_cntl = REG_SET_FIELD(mec_int_cntl, 
CP_ME1_PIPE0_INT_CNTL,
                                             TIME_STAMP_INT_ENABLE, 1);
-               WREG32(mec_int_cntl_reg, mec_int_cntl);
+               WREG32_RLC_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id);
                break;
        default:
                break;
-- 
2.34.1