On Tue, Apr 29, 2025 at 03:50:25PM +0200, Christian König wrote:
> On 4/29/25 12:29, Huang Rui wrote:
> > APU doesn't have second IH ring, so re-routing action here is a no-op.
> > It will take a lot of time to wait timeout from PSP during the
> > initialization. So remo
Soft ping~
On Tue, Apr 22, 2025 at 12:16:29PM +0800, Huang Rui wrote:
> Since secure firmware is more stable than bring up phase, I believe we
> don't need such mdelays any more before wait PSP response on PSP v12.
>
> Signed-off-by: Huang Rui
> ---
> drivers/gpu/drm
APU doesn't have second IH ring, so re-routing action here is a no-op.
It will take a lot of time to wait timeout from PSP during the
initialization. So remove the function in psp v12.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/psp_v12_0.c | 34 --
1
PSP v12 won't have SRIOV function.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/psp_v12_0.c | 52 +-
1 file changed, 17 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
Since secure firmware is more stable than bring up phase, I believe we
don't need such mdelays any more before wait PSP response on PSP v12.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/psp_v12_0.c | 16
1 file changed, 16 deletions(-)
diff --git a/drivers/gp
On Wed, Jun 19, 2024 at 12:46:25PM +0800, Huang Rui wrote:
> On Wed, Jun 19, 2024 at 12:29:24PM +0800, Zhang, Julia wrote:
> > Instead of using state->fb->obj[0] directly, get object from framebuffer
> > by calling drm_gem_fb_get_obj() and return error code when object is
&g
_gem_fb_get_obj after check old_state->fb for NULL.
>
> Signed-off-by: Julia Zhang
> ---
Julia, you can add my RB during V1 in the next submission.
Reviewed-by: Huang Rui
> drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 18 --
> 1 file changed, 16 insertions(+), 2
d-off-by: Julia Zhang
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 17 +++--
> 1 file changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> index
On Wed, Mar 15, 2023 at 08:52:30AM +0800, Stefano Stabellini wrote:
> On Mon, 13 Mar 2023, Jan Beulich wrote:
> > On 12.03.2023 13:01, Huang Rui wrote:
> > > Xen PVH is the paravirtualized mode and takes advantage of hardware
> > > virtualization support when possible.
interrupt by vector.
Signed-off-by: Chen Jiqian
Signed-off-by: Huang Rui
---
arch/x86/include/asm/apic.h | 7 ++
arch/x86/include/asm/xen/pci.h | 5
arch/x86/kernel/acpi/boot.c | 2 +-
arch/x86/pci/xen.c | 39
drivers/xen/events
scall
IOCTL_PRIVCMD_GSI_FROM_IRQ to translate irq to gsi. So
that, we can map pirq successfully in hypervisor side.
Signed-off-by: Chen Jiqian
Signed-off-by: Huang Rui
---
arch/x86/pci/xen.c | 4
drivers/xen/events/events_base.c | 37
driver
ed to set passthrough mode for Xen PVH/HVM as well.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index f2e2cba
Xen PVH is the paravirtualized mode and takes advantage of hardware
virtualization support when possible. It will using the hardware IOMMU
support instead of xen-swiotlb, so disable swiotlb if current domain is
Xen PVH.
Signed-off-by: Huang Rui
---
arch/x86/kernel/pci-dma.c | 8 +++-
1 file
efore.
Signed-off-by: Huang Rui
---
arch/x86/xen/grant-table.c | 2 +-
drivers/xen/grant-table.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/xen/grant-table.c b/arch/x86/xen/grant-table.c
index 1e681bf62561..64a04d1e70f5 100644
--- a/arch/x86/xen/grant-table.c
+++ b
n (2):
x86/xen: acpi registers gsi for xen pvh
xen/privcmd: add IOCTL_PRIVCMD_GSI_FROM_IRQ
Huang Rui (3):
x86/xen: disable swiotlb for xen pvh
xen/grants: update initialization order of xen grant table
drm/amdgpu: set passthrough mode for xen pvh/hvm
arch/x86/include/asm/ap
On Mon, Jul 25, 2022 at 09:59:08AM +0800, Liu, Aaron wrote:
> Enable swiotlb for gmc 11.0.
>
> Signed-off-by: Aaron Liu
Series are Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/dr
Switch to use the callback function to poll the reset status on IMU.
Because it will have different sequency on other ASICs.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h | 1 +
drivers/gpu/drm/amd/amdgpu/imu_v11_0.c | 35 -
2 files changed, 23
IMU has two work mode such as debug mode and mission mode. Current GC
v11_0_0 is using the debug mode.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h | 6 +
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/imu_v11_0.c | 30
+0x2c0/0x2c0 [amdgpu]
[ 1109.406609] drm_ioctl_kernel+0xb6/0x140 [drm]
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
index 1d63f1
> 1)) {
> + fw_shared->present_flag_0 |=
> AMDGPU_VCN_SMU_VERSION_INFO_FLAG;
> + fw_shared->smu_interface_info.smu_interface_type = 1;
> + }
fw_shared->present_flag_0 |= AMDGPU_VCN_SMU_VERSION_INFO_FLAG;
This line can be moved out of "if else".
With that fixed, patch is Acked-by: Huang Rui
>
> if (amdgpu_vcnfw_log)
> amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
> --
> 2.35.1
>
fix to unblock the amdgpu_test. You
may add the comment (FIXME) around the code to describe this issue and what
you plan for next step.
With that fixed, patch is Acked-by: Huang Rui
>
> -Original Message-
> From: Zhang, Yifan
> Sent: Tuesday, March 15, 2022 8:42 PM
&
On Tue, Mar 15, 2022 at 06:25:51PM +0800, Zhang, Yifan wrote:
> If GFX DPM is disbaled, Stable pstate Test in amdgpu_test fails.
> Check GFX DPM statue before change clock level
>
> Log:
> [ 46.595274] [drm] Initialized amdgpu 3.46.0 20150101 for :02:00.0 on
> minor 0
> [ 46.599929] fbcon
On Tue, Mar 01, 2022 at 11:01:19PM +0800, Zhang, Yifan wrote:
> otherwise adev->ip_versions is still empty when amdgpu_gmc_noretry_set
> is called.
>
> Signed-off-by: Yifan Zhang
Series are Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
On Thu, Feb 24, 2022 at 10:48:14PM +0800, Zhang, Yifan wrote:
> Based on smu 13.0.5 features, refine pp table code.
>
> Signed-off-by: Yifan Zhang
Reviewed-by: Huang Rui
> ---
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 134 --
> .../drm/
On Thu, Feb 24, 2022 at 11:45:43AM +0800, Zhang, Yifan wrote:
> SMU MSG index should be used as parameter.
>
> Signed-off-by: Yifan Zhang
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 9 ++---
> 1 file changed, 2 insertio
by: Prike Liang
Series are Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/nv.c | 10 +-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> index 74e0550d00bd..5f375f3430e1
On Mon, Feb 14, 2022 at 03:48:47PM -0500, Alex Deucher wrote:
> Since this is an existing asic, adjust the code to follow
> the same logic as previously so the driver state is consistent.
>
> No functional change intended.
>
> Signed-off-by: Alex Deucher
Acked-by: Huang Rui
On Mon, Feb 07, 2022 at 10:41:54AM +0800, Liu, Aaron wrote:
> Confirmed with hardware team, there is harvesting for gc 10.3.1.
>
> Signed-off-by: Aaron Liu
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 7 ++-
> 1 file changed, 6 inserti
gisters.
>
> Signed-off-by: Lang Yu
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> index 73ab0eebe4
On Thu, Jan 27, 2022 at 11:33:50AM +0800, Huang, Tim wrote:
> [Why]
> It will build failed with unused variable 'dc' with
> '-Werror=unused-variable'enabled when CONFIG_DRM_AMD_DC_DCN
> is not defined.
>
> Signed-off-by: Tim Huang
Reviewed-by: Huang Rui
On Thu, Jan 27, 2022 at 09:48:06AM +0800, Liu, Aaron wrote:
> This patch adds 1.3.1/2.4.0 athub clock gating support.
>
> Signed-off-by: Aaron Liu
Series are Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/athub_v2_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/athub
On Mon, Jan 24, 2022 at 02:43:42PM +0800, Yu, Lang wrote:
> Remove redundant code and use general smu_v11_0_fini_smc_tables function.
>
> Signed-off-by: Lang Yu
Reviewed-by: Huang Rui
> ---
> .../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c| 18 +-
>
uint32_t *min,
> + uint32_t *max)
> +{
We need to add comment here to explain in Cyan Skillfish, the clock is
constant and not changed. So here, min = max = current clock.
With that updated, patch is Reviewed-by:
There is another way to define a APU flag on enum amd_apu_flags to
differentiate A0 and B0 for yellow carp.
But this way looks good for me as well.
Patch is Acked-by: Huang Rui
> + hw_params.dpia_supported = true;
> #if defined(CONFIG_DRM_AMD_DC_DCN)
> - hw_
On Mon, Jan 24, 2022 at 11:20:41AM +0800, Huang, Tim wrote:
> Use IP versions rather than asic_type to differentiate IP version specific
> features.
>
> Signed-off-by: Tim Huang
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 9 +++--
&g
On Mon, Jan 24, 2022 at 11:20:40AM +0800, Huang, Tim wrote:
> Use IP versions rather than asic_type to differentiate IP version specific
> features.
>
> Signed-off-by: Tim Huang
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c | 48 ++
On Tue, Jan 18, 2022 at 09:36:56PM +0800, Lazar, Lijo wrote:
>
>
> On 1/18/2022 4:56 PM, Xiaojian Du wrote:
> > This patch will modify a pair of functions for pcie port wreg/rreg.
> > AMD GPU have had an independent NBIO block from SOC15 arch.
> > If the dirver wants to read/write the address spa
8, ring='
> [ 158.890910] WARNING: CPU: 6 PID: 1617 at kernel/trace/trace.c:3830
> trace_check_vprintf+0x481/0x4a0
>
> Signed-off-by: Huang Rui
> ---
> drivers/gpu/drm/scheduler/gpu_scheduler_trace.h | 17 +
> 1 file changed, 9 inser
through the NBIO block.
> This patch will move the pcie port wreg/rreg functions to
> "amdgpu_device.c", so that to make the functions can be used on the
> future GPU ASICs.
>
> Signed-off-by: Xiaojian Du
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/
> Signed-off-by: Xiaojian Du
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 46 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 1 +
> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 5 +++
> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 5
On Thu, Jan 13, 2022 at 03:45:26PM +0800, Du, Xiaojian wrote:
> This will add vram check function for GMC, it will cover gmc v8/9/10
>
> Signed-off-by: Xiaojian Du
> Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 42 +
>
On Thu, Jan 13, 2022 at 03:45:25PM +0800, Du, Xiaojian wrote:
> This patch is to add data struct for vram check.
>
The subject has a typo: admgpu -> amdgpu
> Signed-off-by: Xiaojian Du
> Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +
viewed-by: Alex Deucher
Please remove the Change-Id. With that fixed, patch is
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ++
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/d
ffset
> accordingly.
>
> Long-term we should expose this info from DC as GMC shouldn't
> need to know about DCN registers.
>
> Signed-off-by: Harry Wentland
Look good for me, this patch needs to backport it to stable kernel (CC
stable mailing list).
Reviewed-by: Huang Rui
&
entity=76f0d517, id=1,
> fence=8dd56028, ring='
> [ 158.890910] WARNING: CPU: 6 PID: 1617 at kernel/trace/trace.c:3830
> trace_check_vprintf+0x481/0x4a0
>
> Signed-off-by: Huang Rui
> ---
> drivers/gpu/drm/scheduler/gpu_scheduler_trace.h | 17 +
>
Reported-by: kernel test robot
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index db41d16838b9..9afd11ca2709 100644
-
0day-ci%2Flinux&data=04%7C01%7Cray.huang%40amd.com%7C57b8f278a2a14c8dab7908d9bfcf2649%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637751718697946000%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=eX6JF%2FjinJTZj9CzP4tvTA3Chd8NODf85oNlSd
156.131993] amdgpu_fence_emit+0x10d/0x2b0 [amdgpu]
[ 156.132302] amdgpu_ib_schedule+0x2f9/0x580 [amdgpu]
[ 156.132586] amdgpu_job_run+0xed/0x220 [amdgpu]
Signed-off-by: Huang Rui
---
V1 -> V2: add another amdgpu_fence_ops which is for job-embedded fence.
156.131993] amdgpu_fence_emit+0x10d/0x2b0 [amdgpu]
[ 156.132302] amdgpu_ib_schedule+0x2f9/0x580 [amdgpu]
[ 156.132586] amdgpu_job_run+0xed/0x220 [amdgpu]
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +-
driv
nt:%d
' current_buffer: 'Xorg-1588[001] .
149.391136: drm_sched_job: entity=76f0d517, id=1,
fence=8dd56028, ring='
[ 158.890910] WARNING: CPU: 6 PID: 1617 at kernel/trace/trace.c:3830
trace_check_vprintf+0x481/0x4a0
Signed-off-by: Huang Rui
---
drive
132302] amdgpu_ib_schedule+0x2f9/0x580 [amdgpu]
[ 156.132586] amdgpu_job_run+0xed/0x220 [amdgpu]
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
b/drivers/g
might trigger some issues in get_timeline_name
callback implementation of different gpu driver. So make a member to
initialize the flags in dma_fence_init().
Signed-off-by: Huang Rui
---
drivers/dma-buf/dma-fence.c | 2 +-
include/linux/dma-fence.h | 7 +++
2 files changed, 8 insertions
On Wed, Dec 01, 2021 at 05:24:58PM +0800, Yu, Lang wrote:
> To maintain system error state when SMU errors occurred,
> which will aid in debugging SMU firmware issues, add SMU
> debug option support.
>
> It can be enabled or disabled via amdgpu_smu_debug
> debugfs file. When enabled, it makes SMU
> RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
> + data = 0x4E20 &
> RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
Acked-by: Huang Rui
Is this patch able to fix the cgpg issue in ROCr test?
Thanks,
Ray
On Tue, Nov 02, 2021 at 02:01:17AM +0800, Sider, Graham wrote:
> Previously Renoir compiler gfx target version was forced to Raven.
> Update driver side for completeness.
>
> Signed-off-by: Graham Sider
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_device.
On Thu, Oct 28, 2021 at 10:53:36AM -0500, Mario Limonciello wrote:
> Although this has been plumbed for Renoir, Green Sardine, Van Gogh,
> and Yellow Carp the functionality in the SMU doesn't do anything for
I double confirmed them in the firmware. These messages are actually
existed in SMU firmwa
PSP firmware will be responsible for applying the GRBM CAM remapping in
the production. And the GRBM_CAM_INDEX / GRBM_CAM_DATA registers will be
protected by PSP under security policy. So remove it according to the
new security policy.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu
PSP firmware will be responsible for applying the GRBM CAM remapping in
the production. And the GRBM_CAM_INDEX / GRBM_CAM_DATA registers will be
protected by PSP under security policy. So remove it according to the
new security policy.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu
Update golden setting to enable full compute units for cyan_skillfish.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index
We should use the real compute unit number for shader array mask. Some
asic doesn't have 16 compute units per shader array.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/dr
Looks OK for me. Although it's not perfect, the legacy design impact a lot
of ASICs and it's hard to change it one by one, so this solution is OK with
minimal impact at this moment.
Acked-by: Huang Rui
> ---
> .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c| 8 ++--
>
The function is ready on psp firmware, and enable it by default.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu
It won't need to clear the xxx_PSP_DEBUG registers, because firmware
will handle this change.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v1
On Wed, Jul 14, 2021 at 05:32:03PM +0800, Du, Xiaojian wrote:
> This patch is to update the golden setting for vangogh.
>
> Signed-off-by: Xiaojian Du
> ---
Reviewed-by: Huang Rui
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
> 1 file changed, 1 insertion(+)
>
>
On Tue, Jul 13, 2021 at 03:00:57PM +0800, Liu, Aaron wrote:
> Remove mdelay process and use smu_cmn_send_smc_msg_with_param to send
> mode-reset message to SMC.
>
> Signed-off-by: Aaron Liu
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu13/yell
On Thu, Jun 24, 2021 at 02:47:22PM +0800, Yu, Lang wrote:
> From: Lang Yu
>
> Implement function amdgpu_ucode_show to show ucode name
> via ucode id.
>
> Signed-off-by: Lang Yu
Series are Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/am
On Wed, Jun 23, 2021 at 10:10:09AM +0800, Liu, Aaron wrote:
> The tmz functions are verified on yellow carp. So enable it by
> default.
>
> Signed-off-by: Aaron Liu
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 1 +
> 1 file changed, 1 inserti
In some asics, we need to adjust the behavior according to the apu flags
at very early stage.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 36 ++
drivers/gpu/drm/amd/amdgpu/nv.c| 1 -
drivers/gpu/drm/amd/amdgpu/soc15.c | 10
On Wed, Jun 02, 2021 at 12:47:40PM -0400, Alex Deucher wrote:
> This patch set adds initial support for Yellow Carp, a new
> GPU from AMD.
Always happy to see the new GPU support. :-)
Series are Acked-by: Huang Rui
>
> I did not send out patch 1 due to its size (new register hea
On Tue, May 18, 2021 at 02:26:03PM +0800, Liu, Aaron wrote:
> Starting from Navi+, the rlc reference clock is used for system clock
> from vbios gfx_info table. It is incorrect to use core_refclk_10khz of
> vbios smu_info table as system clock.
>
> Signed-off-by: Aaron Liu
Acke
es?
>
I think so.
Changfeng, could you please confirm this on all raven series?
Patch is Reviewed-by: Huang Rui
> Alex
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +++---
> > drivers/gpu/drm/amd/amdgpu/soc15.c| 2 --
> > 2 files changed, 7 i
ee to add below
reported-by:
"Reported-by: kernel test robot "
Patch is Acked-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c
> b/dr
> + data = 0;
The data should be inited with register default value like this:
def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
Then you can set the mask according to clock gating enabling flag.
We should handle it like this on the following codes as
On Fri, Apr 23, 2021 at 04:30:10PM +0800, Su, Jinzhou (Joe) wrote:
> Add flags AMD_CG_SUPPORT_SDMA_LS for Vangogh.
> Start to open sdma ls from firmware version 70.
>
> Signed-off-by: Jinzhou Su
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/nv.c| 1 +
On Wed, Apr 21, 2021 at 03:12:50PM +0800, Su, Jinzhou (Joe) wrote:
> Add flags AMD_CG_SUPPORT_SDMA_MGCG for Vangogh.
> Start to open sdma mgcg from firmware version 70.
>
> Signed-off-by: Jinzhou Su
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/nv.c|
;ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo);
> > + /* flush the cache before commit the IB */
>
> Either drop the comment or change it a bit.
>
> E.g. like "/* Invalidate the cache to make the GPU see the newest SA
> content */
>
> With that d
The tmz function are verified on renoir chips as well. So enable it by
default.
Signed-off-by: Huang Rui
Tested-by: Lang Yu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm
e other part is the
> average smu metrics table data. The hwmon will read the current gfxclk
> and mclk from the current smu metrics table data.
>
> Signed-off-by: Xiaojian Du
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 12 ++--
&
; only fclk is allowed to set value manually, so remove the unnecessary
> code of "set" function for mclk.
>
> Signed-off-by: Xiaojian Du
Acked-by: Huang Rui
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 6 --
> 1 file changed, 6 deletions(-)
&g
On Tue, Apr 13, 2021 at 02:23:00PM +0800, Su, Jinzhou (Joe) wrote:
> Add emit mem sync callback for sdma_v5_2
I suggest to describe the problem you encountered for this change, most of
persons would like to know how.
With that fixed, patch is Reviewed-by: Huang Rui
>
> Sign
On Wed, Apr 07, 2021 at 04:25:51PM +0800, Du, Xiaojian wrote:
> This patch is to add the callback to get vbios bootup values for
> vangogh, it will get the bootup values of gfxclk, mclk, socclk and so
> on.
>
> Signed-off-by: Xiaojian Du
Reviewed-by: Huang Rui
> ---
> d
.992843] amdgpu: timeout: rlcg program reg:0x02984 failed!
>
> Fix for patch:
> drm/amdgpu: indirect register access for nv12 sriov
>
> Change-Id: I971804e4e8dbd83e4179beefa8ae8a06bd52913b
> Signed-off-by: Changfeng
Acked-by: Huang Rui
> ---
> drivers/gpu/drm/amd/a
ood version for reset.
Others look good for me, good job!
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/nv.c | 4
> 1 file changed, 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> index 5846eac292c3..a31ef68e
On Mon, Mar 15, 2021 at 11:21:36AM +0800, Bhaskar Chowdhury wrote:
>
> s/"an minimum"/"a minimum"/
> s/"an maxmum"/"a maximum"/
>
> Signed-off-by: Bhaskar Chowdhury
Reviewed-by: Huang Rui
> ---
> Changes from V1:
> Randy&#
h windows KMD s0ix sequence and
> only suspend the DCE and IH for s0i3 entry . Will try figure out the each GNB
> IP idle off dependency and then improve the AMDGPU suspend/resume sequence
> for system-wide Sx entry/exit.
>
Maybe we need a comment before amdgpu_device_ip_sus
when modprobe driver.
>
> Change-Id: I268610e85f6acd9200478d0ab1518349ff81469b
> Signed-off-by: Changfeng
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/a
On Wed, Feb 24, 2021 at 01:33:19PM +0800, Su, Jinzhou (Joe) wrote:
> Add AMD_CG_SUPPORT_SDMA_MGCG for Vangogh
>
> Signed-off-by: Jinzhou Su
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers
We should commit the value after restore them back to default as well.
$ echo "r" > pp_od_clk_voltage
$ echo "c" > pp_od_clk_voltage
Signed-off-by: Huang Rui
---
.../drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 14 ---
.../gpu/drm/amd/pm/swsmu
xisting interfaces for the getting/setting of PPT
> limits. Encode the upper 8 bits of limit value to distinguish
> slow and fast power limit type.
>
> Signed-off-by: Xiaomeng Hou
Series are Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/pm/amdgpu_pm.c| 45
On Tue, Feb 02, 2021 at 08:04:43PM +0800, Su, Jinzhou (Joe) wrote:
> Check GFX DPM and PG bit before enable GFXOFF on Vangogh
> smu post init.
>
> Signed-off-by: Jinzhou Su
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 14 ++
t;
> With that fixed, the patch is
>
> Reviewed-by: Felix Kuehling
>
> The fix also needs to go upstream as KFD seems to be very broken without it.
Thanks, will add the description and push into 5.11 drm-next.
Ray
>
> Regards,
> Felix
>
> Am 2021-02-01 um
232341] ? kfd_ioctl_get_queue_wave_state+0x52/0x52 [amdgpu]
Signed-off-by: Huang Rui
---
This patch is to fix the issue on latest 5.11-rc2 based amd-staging-drm-next.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 16 ++--
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/
gt;
> Signed-off-by: Xiaojian Du
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index f958b02f9317.
On Mon, Feb 01, 2021 at 04:33:40PM +0800, Du, Xiaojian wrote:
> This patch is to fill in the data member of v2 gpu metrics
> table for vangogh.
>
> Signed-off-by: Xiaojian Du
> ---
Reviewed-by: Huang Rui
> drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 3 +++
&g
We cannot modify initial_domain every time while the retry starts. That
will cause the busy waiting that unable to switch to GTT while the vram
is not enough.
Fixes: f8aab60422c3 ("drm/amdgpu: Initialise drm_gem_object_funcs for
imported BOs")
Signed-off-by: Huang Rui
Reviewed-by: Al
On Wed, Jan 27, 2021 at 06:14:03PM +0800, Yu, Lang wrote:
> Move all the dummy functions in amdgpu_amdkfd.c to
> amdgpu_amdkfd.h as inline functions.
>
> Signed-off-by: Lang Yu
> Suggested-by: Felix Kuehling
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/
wise operator")
> Fixes: 3c9a7b7d6e75 ("drm/amdgpu: update mmhub mgcg&ls for mmhub_v2_3")
> Signed-off-by: Colin Ian King
Thanks.
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
Fixes: 27755cdf83f1
> drm/amd/display: Update dcn30_apply_idle_power_optimizations() code
>
> Signed-off-by: Lang Yu
Acked-by: Huang Rui
> ---
> drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/dr
On Thu, Jan 21, 2021 at 10:13:40AM +0800, Su, Jinzhou (Joe) wrote:
> Send allow GfxOff message to SMU to enter GfxOff
> mode as default.
>
> Signed-off-by: Jinzhou Su
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
> 1 file changed, 1 inserti
> Sent: Tuesday, January 19, 2021 1:52 PM
> > > > > To: amd-gfx@lists.freedesktop.org
> > > > > Cc: Deucher, Alexander ; Liang, Prike
> > > > > ; Huang, Ray
> > > > > Subject: [PATCH] drm/amdgpu: remove gpu info firmware of green
&g
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