[why & how]
We need to add the necessary DC codes to support PSR-SU rate
control (RC).
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 14 +++
drivers/gpu/drm/amd/display/dc/dc_link.h | 3 +++
drivers/gpu/drm/amd/display/dc/dc_types.h
[why & how]
The source specific DPCD exposure which is to set the sink device PSR
active vtotal control mode.
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/include/ddc_service_types.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/inc
From: Leo Li
[WHY]
For additional power savings, PSR SU (also referred to as PSR2) can be
enabled on eDP panels with PSR SU support.
PSR2 saves more power compared to PSR1 by allowing more opportunities
for the display hardware to be shut down. In comparison to PSR1, Shut
down can now occur in-
before program cursor registers
Signed-off-by: David Zhang
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 2 +
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 131 ++
.../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 2 +
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 1
e psr version field in psr_config structure, since only
the field psr_version of DC link psr_settings matters for that
fed to DMUB FW, thus no need to set/update the psr_version field
of psr_config structure.
Signed-off-by: David Zhang
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
one stream and the output is eDP panel connected.
changes in v2:
--
- add detailed comment for how psr setup time is calculated as per
eDP 1.5 spec
Cc: Chandan Vurdigerenataraj
Signed-off-by: David Zhang
---
.../amd/display/modules/power/power_helpers.c | 84
[why]
Some specific TCON chip has HW limitation to support PSRSU+DSC.
[how]
Force ffu mode when DSC enabled if we detect it is the specific
model from sink OUI DPCD. And disable ABM update for this case.
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/dc_link.h | 1
[why]
Feature requires synchronization of dig, pipe, and cursor locking
between driver and DMUB fw for PSR-SU
[how]
return True if PSR-SU in the checker should_use_dmub_lock()
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c | 2 ++
1 file changed, 2
ed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4
drivers/gpu/drm/amd/display/dc/dc_types.h | 4 +++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_lin
e PSR state, it take the state for PSR inactive.
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 7 +++
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 16
2 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types
[Why]
The Y-granularity panel parameter indicate the grid
pattern granularity in the Y direction for PSRSU.
[How]
Send the Y-granularity data by PSR_COPY_SETTINGS dmub command.
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4
drivers/gpu/drm/amd/display/dc
[Why & how]
We only support line capture indication as 0 for PSRSU
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
b/drivers/gpu/drm/amd/display/dc/dce/dmub_p
margin with target line number, change the
margin unit to micro second which indicate the time needed for
programming SU. Then FW set the margin line number base on the
line time and margin time.
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 ++
drivers/gpu/drm
[Why]
To support PSR2 Source DPCD configuration
[How]
Update the PSR2 Source DPCD settings while the PSR2 enabled
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 23 ++-
.../drm/amd/display/dc/inc/hw/link_encoder.h | 13 ++-
2 files
[why & how]
We need to implement the VSC packet rev4 that is required by PSRSU.
Follow the eDP 1.5 spec pg. 257
changes in v2:
---
- set vsc packet rev2 for PSR1
Cc: Chandan Vurdigerenataraj
Signed-off-by: David Zhang
---
.../display/modules/info_packet/info_packet.c
[why & how]
Based on PSRSU specification, every selective update frame need to use
two SDP to indicate the frame active range. So we occupy another GSP1
for PSRSU execution.
Signed-off-by: David Zhang
---
.../display/dc/dcn30/dcn30_dio_stream_encoder.c | 15 +++
1 file changed
update function.
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 54 ++
drivers/gpu/drm/amd/display/dc/dc_stream.h | 5 ++
2 files changed, 59 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc
[why & how]
set psr version as PSR-SU in kernel-FW interface function to ensure
the correct dmub command parameter is fed into FW.
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/displa
changes in v2:
---
- set vsc_packet_rev2 for PSR1 which is safer
- add exposure of AMD specific DPCD regs for PSR-SU-RC (rate-control)
- add DC/DM change related to amdgpu PSR-SU-RC
David Zhang (18):
drm/amd/display: align dmub cmd header to latest dmub FW to support
ursor infor
- setting sink vtotal
- dmub ringbuffer command items
Signed-off-by: David Zhang
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 250 +-
1 file changed, 245 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/dr
e psr version field in psr_config structure, since only
the field psr_version of DC link psr_settings matters for that
fed to DMUB FW, thus no need to set/update the psr_version field
of psr_config structure.
Signed-off-by: David Zhang
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
before program cursor registers
Signed-off-by: David Zhang
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 2 +
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 131 ++
.../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 2 +
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 1
[why]
Feature requires synchronization of dig, pipe, and cursor locking
between driver and DMUB fw for PSR-SU
[how]
return True if PSR-SU in the checker should_use_dmub_lock()
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c | 2 ++
1 file changed, 2
From: Leo Li
[WHY]
For additional power savings, PSR SU (also referred to as PSR2) can be
enabled on eDP panels with PSR SU support.
PSR2 saves more power compared to PSR1 by allowing more opportunities
for the display hardware to be shut down. In comparison to PSR1, Shut
down can now occur in-
one stream and the output is eDP panel connected.
Signed-off-by: David Zhang
---
.../amd/display/modules/power/power_helpers.c | 73 +++
.../amd/display/modules/power/power_helpers.h | 6 ++
2 files changed, 79 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/modules
e PSR state, it take the state for PSR inactive.
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 7 +++
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 16
2 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types
[why]
Some specific TCON chip has HW limitation to support PSRSU+DSC.
[how]
Force ffu mode when DSC enabled if we detect it is the specific
model from sink OUI DPCD. And disable ABM update for this case.
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/dc_link.h | 1
ed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4
drivers/gpu/drm/amd/display/dc/dc_types.h | 4 +++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_lin
[Why]
To support PSR2 Source DPCD configuration
[How]
Update the PSR2 Source DPCD settings while the PSR2 enabled
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 23 ++-
.../drm/amd/display/dc/inc/hw/link_encoder.h | 13 ++-
2 files
margin with target line number, change the
margin unit to micro second which indicate the time needed for
programming SU. Then FW set the margin line number base on the
line time and margin time.
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 ++
drivers/gpu/drm
[Why]
The Y-granularity panel parameter indicate the grid
pattern granularity in the Y direction for PSRSU.
[How]
Send the Y-granularity data by PSR_COPY_SETTINGS dmub command.
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4
drivers/gpu/drm/amd/display/dc
[Why & how]
We only support line capture indication as 0 for PSRSU
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
b/drivers/gpu/drm/amd/display/dc/dce/dmub_p
[why & how]
We need to implement the VSC packet rev4 that is required by PSRSU.
Follow the eDP 1.5 spec pg. 257
Signed-off-by: David Zhang
---
.../display/modules/info_packet/info_packet.c | 29 +--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu
[why & how]
Based on PSRSU specification, every selective update frame need to use
two SDP to indicate the frame active range. So we occupy another GSP1
for PSRSU execution.
Signed-off-by: David Zhang
---
.../display/dc/dcn30/dcn30_dio_stream_encoder.c | 15 +++
1 file changed
ursor infor
- setting sink vtotal
- dmub ringbuffer command items
Signed-off-by: David Zhang
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 250 +-
1 file changed, 245 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/dr
update function.
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 54 ++
drivers/gpu/drm/amd/display/dc/dc.h| 3 ++
drivers/gpu/drm/amd/display/dc/dc_stream.h | 5 ++
3 files changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/amd
[why & how]
set psr version as PSR-SU in kernel-FW interface function to ensure
the correct dmub command parameter is fed into FW.
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/displa
David Zhang (16):
drm/amd/display: align dmub cmd header to latest dmub FW to support
PSR-SU
drm/amd/display: feed PSR-SU as psr version to dmub FW
drm/amd/display: combine dirty rectangles in DMUB FW
drm/amd/display: update GSP1 generic info packet for PSRSU
drm/amd/display
[Why]
Allow for PSR SMU optimization and PSR multiple display optimization.
[How]
Add feature flags of PSR smu optimization and PSR multiple display
optimiztaion, and set them during init sequence. By default, flags
are disabled.
Signed-off-by: David Zhang
Reviewed-by: Harry Wentland
Reviewed
[Why]
Allow for PSR SMU optimization and PSR multiple display optimization.
[How]
Add feature flags of PSR smu optimization and PSR multiple display
optimiztaion, and set them during init sequence. By default, flags
are disabled.
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/include
[Why]
Allow for PSR SMU optimization and PSR multiple display optimization.
[How]
Add feature flags of PSR smu optimization and PSR multiple display
optimiztaion, and set them during init sequence. By default, flags
are disabled.
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/include
f-by: David Zhang
Reviewed-by: Harry Wentland
---
include/drm/drm_dp_helper.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 30359e434c3f..ac7b7571ae66 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_help
*** BLURB HERE ***
David Zhang (1):
drm: add PSR2 support and capability definition as per eDP 1.5
include/drm/drm_dp_helper.h | 2 ++
1 file changed, 2 insertions(+)
--
2.25.1
[why & how]
In eDP 1.5 spec, some new DPCD bit fileds are defined for PSR-SU
support.
Signed-off-by: David Zhang
---
include/drm/drm_dp_helper.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 30359e434c3f..ac7b7571
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