drm_file will be used in usermode queues code to
enable better process information in logging and hence
add drm_file part of the userq_mgr struct.
update the drm_file pointer in userq_mgr for each
amdgpu_driver_open_kms.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
Reduce direct handling of edid data by resorting to drm helpers that
deal with this info inside drm_edid infrastructure.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 26 +++
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 24 +
..
Add Linux opaque object to dc_sink for storing edid data cross driver,
drm_edid. Also include the Linux call to free this object, the
drm_edid_free()
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/dc_edid.c | 7 +++
drivers/gpu/drm/amd/display/amdgpu_dm/dc_edid.h | 1 +
From: Rodrigo Siqueira
Since DC is a shared code, this commit introduces a new file to work as
a mid-layer in DC for the edid manipulation.
Signed-off-by: Rodrigo Siqueira
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/Makefile| 1 +
.../gp
From: Rodrigo Siqueira
As part of the effort of stopping using raw edid, this commit move the
copy of the edid in DC to a dedicated function that will allow the usage
of drm_edid in the next steps.
Signed-off-by: Rodrigo Siqueira
Co-developer--by: Melissa Wen
Signed-off-by: Melissa Wen
---
d
We don't need to parse dc_edid to get the display name since it's
already set in drm_eld which in turn had it values updated when updating
connector with the opaque drm_edid.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 10 ++
1 file changed, 6
Hi,
Siqueira and I worked on a solution to reduce the usage of drm_edid_raw
in the AMD display driver, since the current guideline in the DRM
subsystem is to stop handling raw edid data in driver-specific
implementation and use opaque `drm_edid` object with common-code
helpers.
In short, this ser
There is an opaque obj in Linux/DRM to encapsulate edid data as
`drm_edid`. This obj isn't present in other platforms but we need to
pass it through DC when adding sink. To pass this data without
compromise the independence of DC code, make some DC functions accept
edid data as private options.
Si
Pass dc_sink to dm_helpers_parse_edid_caps(), since it already contains
edid info. It's a groundwork to get rid of raw edid stored as dc_edid.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 17 +++--
Make sure the drm_edid container stored in aconnector is freed when
detroying the aconnector.
Fixes: 48edb2a4 ("drm/amd/display: switch amdgpu_dm_connector to use struct
drm_edid")
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++
1 file changed, 2 inserti
drm_edid_connector_update() updates display info, filling ELD with
speaker allocation data in the last step of update_dislay_info(). Our
goal is stopping using raw edid, so we can extract SADB from drm_eld
instead of access raw edid to get audio caps.
Signed-off-by: Melissa Wen
---
.../amd/displ
drm_edid_connector_update() updates display info, filling ELD with audio
info from Short-Audio Descriptors in the last step of
update_dislay_info(). Our goal is stopping using raw edid, so we can
extract SAD from drm_eld instead of access raw edid to get audio caps.
Signed-off-by: Melissa Wen
---
Instead of using driver-specific code, use DRM helpers.
Signed-off-by: Melissa Wen
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 15 +--
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
b/drivers/gpu/d
Since [1], we can use drm_edid_product_id to get debug info from
drm_edid instead of directly parsing EDID.
Link:
https://lore.kernel.org/dri-devel/cover.1712655867.git.jani.nik...@intel.com/
[1]
Signed-off-by: Melissa Wen
---
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c| 16 +
From: Ville Syrjälä
Pass along the format information from the top to .fb_create()
so that we can avoid redundant (and somewhat expensive) lookups
in the drivers.
Done with cocci (with some manual fixups):
@@
identifier func =~ ".*create.*";
identifier dev, file, mode_cmd;
@@
struct drm_framebuf
From: Ville Syrjälä
Decouple drm_get_format_info() from struct drm_mode_fb_cmd2 and just
pass the pixel format+modifier combo in by hand.
We may want to use drm_get_format_info() outside of the normal
addfb paths where we won't have a struct drm_mode_fb_cmd2, and
creating a temporary one just fo
From: Ville Syrjälä
Decouple .get_format_info() from struct drm_mode_fb_cmd2 and just
pass the pixel format+modifier combo in by hand.
We may want to use .get_format_info() outside of the normal
addfb paths where we won't have a struct drm_mode_fb_cmd2, and
creating a temporary one just for this
I should get used to add Alex Deucher's email in CC.
On Mon, Apr 7, 2025 at 10:11 PM Alexandre Demers
wrote:
>
> This series goes from fixing typos in amdgpu and radeon to renaming functions
> in DCE11.0 so it follows the convention of using a DCE/DCN version prefix for
> naming functions.
>
> Al
This will be used to stop/start user queue scheduling for
example when switching between kernel and user queues when
enforce isolation is enabled.
v2: use idx
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 72
since we loop through the queues |= the errors.
Reviewed-by: Sunil Khatri
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
b/drivers/gpu/drm/amd/amdgpu
Enforce isolation serializes access to the GFX IP. User
queues are isolated in the MES scheduler, but we still
need to serialize between kernel queues and user queues.
For enforce isolation, group KGD user queues with KFD user
queues.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/a
Split out the queue map from the mqd create call and split
out the queue unmap from the mqd destroy call. This splits
the queue setup and teardown with the actual enablement
in the firmware.
Reviewed-by: Sunil Khatri
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
Rename to map and umap to better align with what is happening
at the firmware level and remove the extra level of indirection
in the MES userq code.
Reviewed-by: Sunil Khatri
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 10 ++--
drivers/gpu/drm/amd/amdgpu/amdg
Add helpers to unmap and map user queues on suspend and
resume.
Reviewed-by: Sunil Khatri
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 39 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.h | 3 ++
2 files changed, 42 insertions(+)
diff --git
Unmap user queues on suspend and map them on resume.
Reviewed-by: Sunil Khatri
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/
Track this to align with KFD for enforce isolation
handling.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.h
index 381b
Move some userq fence handling code into amdgpu_userq_fence.c.
This matches the other code in that file.
Reviewed-by: Sunil Khatri
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 26 +++
.../gpu/drm/amd/amdgpu/amdgpu_userq_fence.h | 1 +
driver
If userq creation fails, we need to properly unwind and free the
user queue fence driver.
v2: free idr as well (Sunil)
Reviewed-by: Sunil Khatri
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm
On Fri, Apr 11, 2025 at 1:18 PM Khatri, Sunil wrote:
>
> A small comment otherwise it looks great.
> Reviewed-by: Sunil Khatri
>
> On 4/11/2025 12:23 AM, Alex Deucher wrote:
> > Enable users to create queues at different priority levels.
> > The highest level is restricted to drm master.
> >
> >
On Fri, Apr 11, 2025 at 1:40 PM Srinivasan Shanmugam
wrote:
>
> This commit modifies the gfx_v9_0_ring_emit_cleaner_shader function
> to use a switch statement for cleaner shader emission based on the
> specific GFX IP version.
>
> The function now distinguishes between different IP versions, usin
On Fri, Apr 11, 2025 at 12:28 PM Srinivasan Shanmugam
wrote:
>
> This commit introduces the PACKET3_RUN_CLEANER_SHADER_9_0 definition,
> which is a command packet utilized to instruct the GPU to execute the
> cleaner shader for the GFX9.0 graphics architecture.
>
> The cleaner shader is a piece of
On 4/11/2025 7:24 PM, Christian König wrote:
This reverts commit c2cc3648ba517a6c270500b5447d5a1efdad5936. Turned out
that this has some negative consequences for some workloads. Instead check
if the cleaner shader should run directly.
While at it remove amdgpu_vm_need_pipeline_sync(), we also
On Fri, Apr 11, 2025 at 12:38 PM Khatri, Sunil wrote:
>
> Are we replacing the kfx user queue with KGD userqueue names here?
> Also this looks like KFD user queue and KGD userqueue are both treated
> at par ?
Yeah, I could split this into two patches, one to rename the variables
because they are
This commit introduces the PACKET3_RUN_CLEANER_SHADER_9_0 definition,
which is a command packet utilized to instruct the GPU to execute the
cleaner shader for the GFX9.0 graphics architecture.
The cleaner shader is a piece of GPU code that is responsible for
clearing or initializing essential GPU
On Fri, Apr 11, 2025 at 1:26 PM Khatri, Sunil wrote:
>
>
> On 4/11/2025 10:22 PM, Alex Deucher wrote:
> > On Fri, Apr 11, 2025 at 12:17 PM Khatri, Sunil wrote:
> >>
> >> On 4/11/2025 7:42 PM, Alex Deucher wrote:
> >>> This will be used to stop/start user queue scheduling for
> >>> example when sw
This commit modifies the gfx_v9_0_ring_emit_cleaner_shader function
to use a switch statement for cleaner shader emission based on the
specific GFX IP version.
The function now distinguishes between different IP versions, using
PACKET3_RUN_CLEANER_SHADER_9_0 for the versions 9.0.1, 9.1.0,
9.2.1, 9
v2: Simplified logic in second patch (Alex).
Srinivasan Shanmugam (2):
drm/amdgpu: Add PACKET3_RUN_CLEANER_SHADER_9_0 for Cleaner Shader
execution
drm/amdgpu: Enhance Cleaner Shader Handling in GFX v9.0 Architecture
v2
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 +++-
drivers/gpu/d
Same comment here as MES11 that once we have confirmation we might plan
to use same function for all.
Reviewed-by: Sunil Khatri
On 4/11/2025 12:23 AM, Alex Deucher wrote:
Convert driver priority levels to MES11 priority levels.
At the moment they are the same, but they may not always
be.
Sign
On 4/11/2025 10:22 PM, Alex Deucher wrote:
On Fri, Apr 11, 2025 at 12:17 PM Khatri, Sunil wrote:
On 4/11/2025 7:42 PM, Alex Deucher wrote:
This will be used to stop/start user queue scheduling for
example when switching between kernel and user queues when
enforce isolation is enabled.
Sign
Reviewed-by: Sunil Khatri
On 4/11/2025 12:24 AM, Alex Deucher wrote:
Set up TMZ for queues.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/gf
Reviewed-by: Sunil Khatri
On 4/11/2025 12:23 AM, Alex Deucher wrote:
Use this to track the whether we want TMZ for queues.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/
Am 11.04.25 um 16:20 schrieb Alex Deucher:
> Not techincally wrong, but I think a semicolon was
> intended here.
>
> Fixes: 6cc6e61788f7 ("drm/amdgpu: use a dummy owner for sysfs triggered
> cleaner shaders v3")
> Cc: Christian König
> Signed-off-by: Alex Deucher
Reviewed-by: Christian König
Reviewed-by: Sunil Khatri
On 4/11/2025 12:24 AM, Alex Deucher wrote:
Enable users to create secure GFX/compute queues.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/d
Are we replacing the kfx user queue with KGD userqueue names here?
Also this looks like KFD user queue and KGD userqueue are both treated
at par ?
Looks good in general if the above understanding is correct. Some one
with better understanding of isolation should review.
Acked-by: Sunil Khatri
Reviewed-by: Sunil Khatri
On 4/11/2025 12:24 AM, Alex Deucher wrote:
So that we initialize the MQD as a secure queue.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.
Reviewed-by: Sunil Khatri
On 4/11/2025 12:23 AM, Alex Deucher wrote:
Set up TMZ for queues.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gf
Reviewed-by: Sunil Khatri
On 4/11/2025 12:23 AM, Alex Deucher wrote:
If the queues needs to access TMZ surfaces, it must
be set up as secure.
Signed-off-by: Alex Deucher
---
include/uapi/drm/amdgpu_drm.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/uapi/drm/amdgpu_drm.h b/
A small comment otherwise it looks great.
Reviewed-by: Sunil Khatri
On 4/11/2025 12:23 AM, Alex Deucher wrote:
Enable users to create queues at different priority levels.
The highest level is restricted to drm master.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userque
[AMD Official Use Only - AMD Internal Distribution Only]
The series is:
Reviewed-by: Leo Liu
> -Original Message-
> From: Sundararaju, Sathishkumar
> Sent: April 10, 2025 9:01 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Leo ; Zhang, Hawking
> ; Sundararaju, Sathishkumar
>
> Subje
On Fri, Apr 11, 2025 at 12:17 PM Khatri, Sunil wrote:
>
>
> On 4/11/2025 7:42 PM, Alex Deucher wrote:
> > This will be used to stop/start user queue scheduling for
> > example when switching between kernel and user queues when
> > enforce isolation is enabled.
> >
> > Signed-off-by: Alex Deucher
Reviewed-by: Sunil Khatri
On 4/11/2025 12:23 AM, Alex Deucher wrote:
Handle the queue priority set by the user.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/a
Reviewed-by: Sunil Khatri
On 4/11/2025 12:23 AM, Alex Deucher wrote:
So we can track this when we create user queues.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueu
This patch adds recommended SDMA engines with limited XGMI SDMA engines.
It will help improve overall performance for device to device copies
with this optimization.
v2: Update the formatting issues and data type
Signed-off-by: Shane Xiao
Suggested-by: Jonathan Kim
Reviewed-by: Jonathan Kim
--
Do you expect priority level in MES11 12 and probably 13 too ? If they
are same then we should be using the same conversion function for all
versions of MES. For now its fine.
Reviewed-by: Sunil Khatri
On 4/11/2025 12:23 AM, Alex Deucher wrote:
Convert driver priority levels to MES11 priority
Reviewed-by: Sunil Khatri
On 4/11/2025 12:23 AM, Alex Deucher wrote:
Reuse the _pad field for flags.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 4 ++--
include/uapi/drm/amdgpu_drm.h | 5 -
2 files changed, 6 insertions(+), 3 deletio
Reviewed-by: Sunil Khatri
On 4/11/2025 12:23 AM, Alex Deucher wrote:
Allow the user to set a queue priority levels:
0 - normal low - most apps (maps to MES AMD_PRIORITY_LEVEL_NORMAL)
1 - low - background jobs (maps to MES AMD_PRIORITY_LEVEL_LOW)
2 - normal high - apps that need relative high (m
On Fri, Apr 11, 2025 at 12:37 PM Srinivasan Shanmugam
wrote:
>
> This commit modifies the gfx_v9_0_ring_emit_cleaner_shader function
> to use a switch statement for cleaner shader emission based on the
> specific GFX IP version.
>
> The function now distinguishes between different IP versions, usi
Reviewed-by: Sunil Khatri
On 4/10/2025 11:48 PM, Alex Deucher wrote:
This is unused so remove it.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
b/drivers/gpu/drm/amd/
[AMD Official Use Only - AMD Internal Distribution Only]
GFX11 is a dGPU. We don't currently have a way to deal with migration of
encrypted buffers to system ram.
Alex
From: jesse.zh...@amd.com
Sent: Tuesday, April 8, 2025 2:32 AM
To: amd-gfx@lists.freedesktop.
Reviewed-by: Sunil Khatri
On 4/11/2025 6:20 PM, Alex Deucher wrote:
Copy paste typo. Use the flag from the sdma structure.
Fixes: 4310acd4464b ("drm/amdgpu: add ring flag for no user submissions")
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
1 file chang
This commit modifies the gfx_v9_0_ring_emit_cleaner_shader function
to use a switch statement for cleaner shader emission based on the
specific GFX IP version.
The function now distinguishes between different IP versions, using
PACKET3_RUN_CLEANER_SHADER_9_0 for the versions 9.0.1, 9.1.0,
9.2.1, 9
This patch series enhances the management of the cleaner shader within
the AMDGPU driver for GFX v9.0 architecture.
The first patch introduces a new packet definition,
PACKET3_RUN_CLEANER_SHADER_9_0, to ensure proper execution of the
cleaner shader for specific GFX versions.
The second patch ref
This commit introduces the PACKET3_RUN_CLEANER_SHADER_9_0 definition,
which is a command packet utilized to instruct the GPU to execute the
cleaner shader for the GFX9.0 graphics architecture.
The cleaner shader is a piece of GPU code that is responsible for
clearing or initializing essential GPU
On 4/11/2025 7:42 PM, Alex Deucher wrote:
This will be used to stop/start user queue scheduling for
example when switching between kernel and user queues when
enforce isolation is enabled.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm
Reviewed-by: Sunil Khatri
On 4/11/2025 7:42 PM, Alex Deucher wrote:
since we loop through the queues |= the errors.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/a
Reviewed-by: Sunil Khatri
On 4/11/2025 7:42 PM, Alex Deucher wrote:
Unmap user queues on suspend and map them on resume.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/
Reviewed-by: Sunil Khatri
On 4/11/2025 7:42 PM, Alex Deucher wrote:
Add helpers to unmap and map user queues on suspend and
resume.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 39 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.h | 3 ++
LGTM, thanks Alex
Reviewed-by: Sunil Khatri
On 4/11/2025 7:42 PM, Alex Deucher wrote:
If userq creation fails, we need to properly unwind and free the
user queue fence driver.
v2: free idr as well (Sunil)
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 4 +++
On 4/11/2025 7:54 PM, Alex Deucher wrote:
On Fri, Apr 11, 2025 at 9:05 AM Sunil Khatri wrote:
add process and pid information in the userqueue error
logging to make it more useful in resolving the error
by logs.
Sample log:
[ 42.444297] [drm:amdgpu_userqueue_wait_for_signal [amdgpu]] *ERRO
On Fri, Apr 11, 2025 at 4:37 AM jesse.zh...@amd.com wrote:
>
> From: "jesse.zh...@amd.com"
>
> Register stop/start/soft_reset queue functions for SDMA IP versions
> v4.4.2, v5.0 and v5.2.
>
> Suggested-by: Alex Deucher
> Signed-off-by: Jesse Zhang
Might want to split this per IP? Either way:
On Fri, Apr 11, 2025 at 4:30 AM jesse.zh...@amd.com wrote:
>
> From: "jesse.zh...@amd.com"
>
> This patch removes the deprecated SDMA reset callback mechanism, which was
> previously used to register pre-reset and post-reset callbacks for SDMA
> engine resets.
> The callback mechanism has been
On Fri, Apr 11, 2025 at 4:57 AM jesse.zh...@amd.com wrote:
>
> From: "jesse.zh...@amd.com"
>
> This patch introduces a new function `amdgpu_sdma_soft_reset` to handle SDMA
> soft resets directly,
> rather than relying on the DPM interface.
>
> 1. **New `amdgpu_sdma_soft_reset` Function**:
>-
On Fri, Apr 11, 2025 at 4:42 AM jesse.zh...@amd.com wrote:
>
> From: "jesse.zh...@amd.com"
>
> This patch refactors the SDMA v5.x queue reset and stop logic to improve
> code readability, maintainability, and performance. The key changes include:
>
> 1. **Generalized `sdma_v5_x_gfx_stop` Function
On Fri, Apr 11, 2025 at 4:30 AM jesse.zh...@amd.com wrote:
>
> From: "jesse.zh...@amd.com"
>
> Replace old callback mechanism with direct calls to stop/start functions.
>
> Suggested-by: Alex Deucher
> Signed-off-by: Jesse Zhang
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/
On Fri, Apr 11, 2025 at 4:29 AM jesse.zh...@amd.com wrote:
>
> From: "jesse.zh...@amd.com"
>
> This patch introduces new function pointers in the amdgpu_sdma structure
> to handle queue stop, start and soft reset operations. These will replace
> the older callback mechanism.
>
> The new functions
[Public]
> -Original Message-
> From: amd-gfx On Behalf Of Shane
> Xiao
> Sent: Thursday, April 10, 2025 12:40 AM
> To: amd-gfx@lists.freedesktop.org; Kim, Jonathan
> Cc: Xiao, Shane
> Subject: [PATCH] drm/amdkfd: Add rec SDMA engines support with limited XGMI
>
> This patch adds recomm
Unmap user queues on suspend and map them on resume.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_devic
Am 11.04.25 um 17:00 schrieb Srinivasan Shanmugam:
> This change adds a check to ensure that 'bo_va' is not null before
> dereferencing it. If 'bo_va' is null, the function returns early,
> preventing any potential crashes or undefined behavior
>
> Fixes the below:
> drivers/gpu/drm/amd/amdgp
This change adds a check to ensure that 'bo_va' is not null before
dereferencing it. If 'bo_va' is null, the function returns early,
preventing any potential crashes or undefined behavior
Fixes the below:
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c:139
amdgpu_gem_update_bo_mapping()
e
[Public]
Reviewed-by: Kent Russell
> -Original Message-
> From: amd-gfx On Behalf Of Eric Huang
> Sent: Friday, April 11, 2025 9:45 AM
> To: Huang, JinHuiEric ; amd-
> g...@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdkfd: add smi events for process start and end
>
> Ping ...
>
On 4/11/2025 7:50 PM, Alex Deucher wrote:
Not techincally wrong, but I think a semicolon was
intended here.
Fixes: 6cc6e61788f7 ("drm/amdgpu: use a dummy owner for sysfs triggered cleaner
shaders v3")
Cc: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gf
Not techincally wrong, but I think a semicolon was
intended here.
Fixes: 6cc6e61788f7 ("drm/amdgpu: use a dummy owner for sysfs triggered cleaner
shaders v3")
Cc: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
1 file changed, 1 insertion(+), 1 d
Split out the queue map from the mqd create call and split
out the queue unmap from the mqd destroy call. This splits
the queue setup and teardown with the actual enablement
in the firmware.
Reviewed-by: Sunil Khatri
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
On Fri, Apr 11, 2025 at 9:05 AM Sunil Khatri wrote:
>
> add process and pid information in the userqueue error
> logging to make it more useful in resolving the error
> by logs.
>
> Sample log:
> [ 42.444297] [drm:amdgpu_userqueue_wait_for_signal [amdgpu]] *ERROR* Timed
> out waiting for fence
Reviewed-by: Sunil Khatri
On 4/10/2025 11:41 PM, Alex Deucher wrote:
Move some userq fence handling code into amdgpu_userq_fence.c.
This matches the other code in that file.
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 26 +++
.../gpu/drm/
If userq creation fails, we need to properly unwind and free the
user queue fence driver.
v2: free idr as well (Sunil)
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueu
Add helpers to unmap and map user queues on suspend and
resume.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 39 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.h | 3 ++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgp
since we loop through the queues |= the errors.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
index f
Enforce isolation serializes access to the GFX IP. User
queues are isolated in the MES scheduler, but we still
need to serialize between kernel queues and user queues.
For enforce isolation, group KGD user queues with KFD user
queues.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/a
This will be used to stop/start user queue scheduling for
example when switching between kernel and user queues when
enforce isolation is enabled.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 68
Rename to map and umap to better align with what is happening
at the firmware level and remove the extra level of indirection
in the MES userq code.
Reviewed-by: Sunil Khatri
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 10 ++--
drivers/gpu/drm/amd/amdgpu/amdg
Move some userq fence handling code into amdgpu_userq_fence.c.
This matches the other code in that file.
Reviewed-by: Sunil Khatri
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 26 +++
.../gpu/drm/amd/amdgpu/amdgpu_userq_fence.h | 1 +
driver
This reverts commit c2cc3648ba517a6c270500b5447d5a1efdad5936. Turned out
that this has some negative consequences for some workloads. Instead check
if the cleaner shader should run directly.
While at it remove amdgpu_vm_need_pipeline_sync(), we also check again
if the VMID has seen a GPU reset sin
Ping ...
On 2025-04-07 16:52, Eric Huang wrote:
rocm-smi will be able to show the events for KFD process
start/end, it is the implementation of this feature.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdkfd/kfd_process.c| 4
drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 21
On Fri, Apr 11, 2025 at 8:42 AM Lijo Lazar wrote:
>
> Except HDP v5.2 all use a common logic for HDP flush. Use a generic
> function. HDP v5.2 forces NO_KIQ logic, revisit it later.
>
> Signed-off-by: Lijo Lazar
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c | 21 ++
On Fri, Apr 11, 2025 at 4:23 AM jesse.zh...@amd.com wrote:
>
> Fix an array index out of bounds warning in the DMA IP case of
> amdgpu_hw_ip_info() where it was incorrectly checking
> adev->gfx.gfx_ring[i].no_user_submission instead of
> adev->sdma.instance[i].ring.no_user_submission.
>
> The mism
add process and pid information in the userqueue error
logging to make it more useful in resolving the error
by logs.
Sample log:
[ 42.444297] [drm:amdgpu_userqueue_wait_for_signal [amdgpu]] *ERROR* Timed
out waiting for fence f=1c74d978 for comm:Xwayland pid:3427
[ 42.444669] [drm:am
Reviewed-by: Sunil Khatri
On 4/10/2025 11:41 PM, Alex Deucher wrote:
Split out the queue map from the mqd create call and split
out the queue unmap from the mqd destroy call. This splits
the queue setup and teardown with the actual enablement
in the firmware.
Signed-off-by: Alex Deucher
---
On Fri, Apr 11, 2025 at 4:07 AM Emily Deng wrote:
>
> For VF, it doesn't have the permission to clear overflow, clear the bit
> by reset.
>
> Signed-off-by: Emily Deng
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 10 --
> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 1 +
> drivers/gpu/d
Reviewed-by: Sunil Khatri
On 4/10/2025 11:41 PM, Alex Deucher wrote:
Rename to map and umap to better align with what is happening
at the firmware level and remove the extra level of indirection
in the MES userq code.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userque
1 - 100 of 125 matches
Mail list logo
