Hi, Alex,
On Thu, Mar 20, 2025 at 10:16 AM Alex Hung wrote:
>
>
>
> On 3/18/25 05:17, Huacai Chen wrote:
> > Commit 7da55c27e76749b9 ("drm/amd/display: Remove incorrect FP context
> > start") removes the FP context protection of dml2_create(), and it said
> > "All the DC_FP_START/END should be us
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Lazar, Lijo
Sent: Thursday, March 20, 2025 13:04
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Kasiviswanathan, Harish
; Lin, Amb
Am 18.03.25 um 15:54 schrieb Arvind Yadav:
> The display is freezing because the amdgpu_userq_wait_ioctl()
> is waiting for a non-user queue fence(specifically, the PT update fence).
>
> RootCause:
> The resume_work is initiated by both amdgpu_userq_suspend and
> amdgpu_userqueue_ensure_ev_fence at
On 19. 03. 25, 14:31, Alex Deucher wrote:
On Wed, Mar 19, 2025 at 5:44 AM Jiri Slaby (SUSE) wrote:
irq_domain_add_linear() is going away as being obsolete now. Switch to
the preferred irq_domain_create_linear(). That differs in the first
parameter: It takes more generic struct fwnode_handle in
In the case of injecting uncorrected error with background workload,
the deferred error among uncorrected errors need to be specified
by checking the deferred and poison bits of status register.
Signed-off-by: Xiang Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c | 3 +++
drivers/gpu/drm/amd/am
From: "jesse.zh...@amd.com"
This commit updates the VM flush implementation for the SDMA engine.
- Added a new function `sdma_v4_4_2_get_invalidate_req` to construct the
VM_INVALIDATE_ENG0_REQ
register value for the specified VMID and flush type. This function ensures
that all relevant
pag
From: "jesse.zh...@amd.com"
This commit updates the VM flush implementation for the SDMA engine.
- Added a new function `sdma_v4_4_2_get_invalidate_req` to construct the
VM_INVALIDATE_ENG0_REQ
register value for the specified VMID and flush type. This function ensures
that all relevant
pag
From: "jesse.zh...@amd.com"
- Modify the VM invalidation engine allocation logic to handle SDMA page rings.
SDMA page rings now share the VM invalidation engine with SDMA gfx rings
instead of
allocating a separate engine. This change ensures efficient resource
management and
avoids the is
From: Ausef Yousof
[Why&How]
During consecutive full updates its possible for us to do otg pipe
locking/programming before previous pipe updates have latched (resulting
in single frame corruption/black screen).wait_for_outstanding_updates does
a poll for some bits to clear in HW that tell us that
From: "jesse.zh...@amd.com"
Increase the maximum number of rings supported by the AMDGPU driver from 133 to
149.
This change is necessary to enable support for the SDMA page ring.
Signed-off-by: Jesse Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 +-
1 file changed, 1 insertion(+), 1
[AMD Official Use Only - AMD Internal Distribution Only]
Thanks Tohmasz.
I confirmed that this change is not in the latest driver-if file.
However, this is a fw interface provided by firmware team, we can not change it.
That means the interface is different between the smu13 and smu14.
Let me chec
To get the device context, replace pr_ with dev_ functions.
Signed-off-by: Lijo Lazar
---
.../gpu/drm/amd/amdkfd/kfd_int_process_v10.c | 142 --
.../gpu/drm/amd/amdkfd/kfd_int_process_v11.c | 92
.../gpu/drm/amd/amdkfd/kfd_int_process_v9.c | 142 ++--
Enable the cleaner shader for GFX11.5.0/11.5.1 GPUs to provide data
isolation between GPU workloads. The cleaner shader is responsible for
clearing the Local Data Store (LDS), Vector General Purpose Registers
(VGPRs), and Scalar General Purpose Registers (SGPRs), which helps
prevent data leakage an
Please see comments for patch 1.
On 3/18/25 05:17, Huacai Chen wrote:
Similar to dml2_create()/dml2_copy()/dml2_create_copy(), dml2_validate()
should also be protected from its callers because "All the DC_FP_START/END
should be used before call anything from DML2".
So protect dml2_validate() wi
On 3/18/25 05:17, Huacai Chen wrote:
Commit 7da55c27e76749b9 ("drm/amd/display: Remove incorrect FP context
start") removes the FP context protection of dml2_create(), and it said
"All the DC_FP_START/END should be used before call anything from DML2".
However, dml2_create()/dml2_copy()/dml2_
From: Leo Zeng
[WHY]
We want to output visual confirm color based on stream.
[HOW]
If visual confirm is for DMUB, use DMUB to get color.
Otherwise, find plane with highest layer index, output visual confirm color
of pipe that contains plane with highest index.
Reviewed-by: Aric Cyr
Signed-off-
From: Leo Li
[Why]
Depending on when the HW latching event (vupdate) of double-buffered
registers happen relative to the PSR SDP (signals panel psr enter/exit)
deadline, and how bad the Panel clock has drifted since the last ALPM
off event, there can be up to 3 frames of delay between sending th
From: Charlene Liu
[why]
the guard of is_apu not in sync, caused no watermark_c output.
Reviewed-by: Ovidiu Bunea
Signed-off-by: Charlene Liu
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff
On Mon, Mar 17, 2025 at 11:04 AM Alex Deucher wrote:
>
> On Mon, Mar 17, 2025 at 2:38 AM Alexandre Demers
> wrote:
> >
> > Signed-off-by: Alexandre Demers
> > ---
> > drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 338 +++--
> > drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c | 36 +--
On 2025-03-19 03:02, Daisuke Matsuda (Fujitsu) wrote:
On Tue, Mar 18, 2025 5:35 AM Felix Kuehling wrote:
On 2025-03-17 15:07, Deucher, Alexander wrote:
[Public]
-Original Message-
From: Daisuke Matsuda
Sent: Thursday, March 13, 2025 9:18 PM
To: amd-gfx@lists.freedesktop.org; dri-de..
Enable pipes on both MECs for MES.
Fixes: 745f46b6a99f ("drm/amdgpu: enable mes v12 self test")
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
b/drivers/gpu/drm
We shouldn't return after the last section.
We need to update the rest of the CSIB.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 1080
On Wed, Mar 19, 2025 at 12:25 PM Alex Deucher wrote:
>
> Enable pipes on both MECs for MES.
>
Fixes: 745f46b6a99f ("drm/amdgpu: enable mes v12 self test")
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
>
From: Paul Hsieh
[Why]
It makes DSC enable when we commit the stream which need
keep power off.And then it will skip to disable DSC if
pipe reset at this situation as power has been off. It may
cause the DSC unexpected enable on the pipe with the
next new stream which doesn't support DSC.
[HOW]
From: Cruise
[Why]
USB4 BW Allocation response will be handled in HPD IRQ.
No need to handle it in DPIA notification callback.
[How]
Remove DP BW allocation response code in DPIA notification.
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Cruise
Signed-off-by: Aurabindo Pillai
---
drivers
From: Leo Li
[Why]
The `vblank_config.offdelay` field follows the same semantics as the
`drm_vblank_offdelay` parameter. Setting it to 0 will never disable
vblank.
[How]
Set `offdelay` to a positive number.
Fixes: e45b6716de4b ("drm/amd/display: use a more lax vblank enable policy for
DCN35+
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Shaoyun.liu
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Wednesday, March 19, 2025 12:24 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 1/2] drm/amdgpu/mes: optimize c
DC v3.2.326 Summary:
* DML 2.1 resync
* Vblank disable fixes
* Visual confirm debug improvements
* Add command for reading ABM histogram
* Bug fixes & improvements
__
Aric Cyr (2):
drm/amd/display: Create a temporary scratch dc_link
drm/amd/display: DC v3.2.326
Ausef Yousof (1):
From: Charlene Liu
[why]
this dscclk use DCN defined per DPM level will cause a DCFCLK increase.
needs to follow up.
This reverts commit 9932ab57776fa0168b702371ff5e2881c026f353
Reviewed-by: Yihan Zhu
Reviewed-by: Alvin Lee
Signed-off-by: Charlene Liu
Signed-off-by: Aurabindo Pillai
---
dr
From: Yi-Ling Chen
[Why]
For some pixel clock margin sensitive external monitor, we could
not keep original DP ref clock for the ASICs supported SSC DP ref clock.
[How]
>From slicon design team's comment, we have to apply the
adjusted DP ref clock for DP devices. DP 128b (DP2) signals
use DTBCLK
From: Leo Zeng
[WHY]
We want to allow the display manager to override the visual
confirm color in DC when required.
[HOW]
Add new visual confirm mode VISUAL_CONFIRM_EXPLICIT, check mode before
setting visual confirm color.
Reviewed-by: Aric Cyr
Signed-off-by: Leo Zeng
Signed-off-by: Aurabindo
From: Chun-Liang Chang
[Why]
Read the histogram for VariBright validation
[How]
Add dc/dmub functions to read histogram and ACE
Reviewed-by: Jun Lei
Signed-off-by: Chun-Liang Chang
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 2 +
.../gpu/drm/amd/disp
From: Aric Cyr
Summary:
* DML 2.1 resync
* Vblank disable fixes
* Visual confirm debug improvements
* Add command for reading ABM histogram
* Bug fixes & improvements
Signed-off-by: Aric Cyr
Signed-off-by: Aurabindo Pillai
Reviewed-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
On Wed, Mar 19, 2025 at 8:53 AM Tomasz Pakuła
wrote:
>
> On Wed, 19 Mar 2025 at 03:19, Feng, Kenneth wrote:
> >
> > [AMD Official Use Only - AMD Internal Distribution Only]
> >
> > -Original Message-
> > From: Tomasz Pakuła
> > Sent: Sunday, March 16, 2025 4:16 AM
> > To: Deucher, Alexan
Break when we get to the end of the supported pipes
rather than continuing the loop.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
b/drivers/gpu/drm/amd/amdgpu/a
Enable pipes on both MECs for MES.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 920cd1c1eacb6..b8066c0b9014f 1
We shouldn't return after the last section.
We need to update the rest of the CSIB.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 13fb
We shouldn't return after the last section.
We need to update the rest of the CSIB.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index a
We shouldn't return after the last section.
We need to update the rest of the CSIB.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 8181
Sorry missed that one, Acked-by: Christian König
Regards,
Christian.
Am 18.03.25 um 14:15 schrieb Alex Deucher:
> Ping?
>
> On Wed, Mar 12, 2025 at 1:57 PM Alex Deucher
> wrote:
>> This was leftover from MES bring up when we had MES
>> user queues in the kernel. It's no longer used so
>> remo
On 3/18/2025 8:17 PM, Ahmad Rehman wrote:
> For SRIOV, skip the SDMA queue reset and return
> error. The engine/queue reset failure will trigger
> FLR in the sequence.
>
> v2: do not add queue reset support mask for sriov
>
> Signed-off-by: Ahmad Rehman
Reviewed-by: Lijo Lazar
Thanks,
Lijo
On Wed, Mar 19, 2025 at 2:12 AM Liang, Prike wrote:
>
> [Public]
>
> > From: amd-gfx On Behalf Of Alex
> > Deucher
> > Sent: Thursday, March 13, 2025 10:41 PM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Deucher, Alexander ; Khatri, Sunil
> >
> > Subject: [PATCH 04/11] drm/amdgpu/mes: centraliz
On Wed, Mar 19, 2025 at 7:23 AM Dominik Kaszewski
wrote:
>
> Add missing colon in kernel-doc for DC_DEBUG_MASK enum.
>
> Signed-off-by: Dominik Kaszewski
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/include/amd_shared.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --
On Wed, Mar 19, 2025 at 5:44 AM Jiri Slaby (SUSE) wrote:
>
> irq_domain_add_linear() is going away as being obsolete now. Switch to
> the preferred irq_domain_create_linear(). That differs in the first
> parameter: It takes more generic struct fwnode_handle instead of struct
> device_node. Therefo
On Wed, Mar 19, 2025 at 2:42 AM Liang, Prike wrote:
>
> [Public]
>
> > -Original Message-
> > From: amd-gfx On Behalf Of Alex
> > Deucher
> > Sent: Thursday, March 13, 2025 2:57 AM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Deucher, Alexander ; Khatri, Sunil
> >
> > Subject: [PATCH 05
Hi Helen,
On 19/03/25 00:22, Helen Mae Koike Fornazier wrote:
Em sex., 14 de mar. de 2025 às 05:59, Vignesh Raman
escreveu:
LAVA was recently patched [1] with a fix on how parameters are parsed in
`lava-test-case`, so we don't need to repeat quotes to send the
arguments properly to it. Uprev
On Wed, Mar 19, 2025 at 5:03 AM Liang, Prike wrote:
>
> [Public]
>
> > From: amd-gfx On Behalf Of Alex
> > Deucher
> > Sent: Thursday, March 13, 2025 10:42 PM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Deucher, Alexander ; Khatri, Sunil
> >
> > Subject: [PATCH 06/11] drm/amdgpu/mes: make more
On Wed, Mar 19, 2025 at 2:38 AM Kenneth Feng wrote:
>
> This reverts commit b00fb9765ea4b05198d67256118445c6f13f9ddf.
>
> Reason for revert: this causes some tests fail with call trace.
Do you have a copy of the call trace? I can't see how this would be an issue?
Alex
>
> Signed-off-by: Kennet
On Wed, 19 Mar 2025 at 03:19, Feng, Kenneth wrote:
>
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> -Original Message-
> From: Tomasz Pakuła
> Sent: Sunday, March 16, 2025 4:16 AM
> To: Deucher, Alexander ; Feng, Kenneth
> ; Wang, Yang(Kevin)
> Cc: amd-gfx@lists.freedesk
Add missing colon in kernel-doc for DC_DEBUG_MASK enum.
Signed-off-by: Dominik Kaszewski
---
drivers/gpu/drm/amd/include/amd_shared.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
b/drivers/gpu/drm/amd/include/amd_shared.h
index 4c9
>> + *
>> + * Return:
>> + * 0 on success, or an error on failing to expand the array.
>> + */
>> +int drm_sched_job_prealloc_dependency_slots(struct drm_sched_job
>> *job,
>> + unsigned int num_deps)
>> +{
>> +struct dma_fence *fence;
>> +u32 id = 0;
Am 18.03.25 um 13:39 schrieb Danilo Krummrich:
> On Tue, Mar 18, 2025 at 01:03:12PM +0100, Christian König wrote:
>> /**
>> * drm_sched_job_add_dependency - adds the fence as a job dependency
>> * @job: scheduler job to add the dependencies to
>> @@ -878,10 +910,12 @@ int drm_sched_job_add_dep
Em sex., 14 de mar. de 2025 às 05:59, Vignesh Raman
escreveu:
>
> The mediatek display driver fails to probe on mt8173-elm-hana and
> mt8183-kukui-jacuzzi-juniper-sku16 in v6.14-rc4 due to missing PHY
> configurations.
>
> Enable the following PHY drivers for MediaTek platforms:
> - CONFIG_PHY_MTK
On 19. 03. 25, 11:21, Andy Shevchenko wrote:
I am all to support the idea, but in some cases I would think of a bit
more work to be done to get rid of the of_fwnode_handle(np) in favour
of dev_fwnode(dev). Note, this is based on a brief look, I haven't any
example at hand right now.
Aah, that's
On Tue, Mar 18, 2025 5:35 AM Felix Kuehling wrote:
> On 2025-03-17 15:07, Deucher, Alexander wrote:
> > [Public]
> >
> >> -Original Message-
> >> From: Daisuke Matsuda
> >> Sent: Thursday, March 13, 2025 9:18 PM
> >> To: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
> >>
Em sex., 14 de mar. de 2025 às 05:59, Vignesh Raman
escreveu:
>
> LAVA was recently patched [1] with a fix on how parameters are parsed in
> `lava-test-case`, so we don't need to repeat quotes to send the
> arguments properly to it. Uprev mesa to fix this issue.
>
> [1] https://gitlab.com/lava/lav
On Wed, Mar 19, 2025 at 11:30 AM Jiri Slaby (SUSE) wrote:
>
> Hi,
>
> tl;dr if patches are agreed upon, I ask subsys maintainers to take the
> respective ones via their trees (as they are split per subsys), so that
> the IRQ tree can take only the rest. That would minimize churn/conflicts
> during
irq_domain_add_linear() is going away as being obsolete now. Switch to
the preferred irq_domain_create_linear(). That differs in the first
parameter: It takes more generic struct fwnode_handle instead of struct
device_node. Therefore, of_fwnode_handle() is added around the
parameter.
Note some of
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Shashank Sharma
Regards
Shashank
From: Yadav, Arvind
Sent: Tuesday, March 18, 2025 3:54 PM
To: Koenig, Christian; Deucher, Alexander; Khatri, Sunil; Sharma, Shashank
Cc: amd-gfx@lists.freedeskt
On 3/19/2025 10:37 AM, jesse.zh...@amd.com wrote:
> From: "jesse.zh...@amd.com"
>
> This commit updates the VM flush implementation for the SDMA engine.
>
> - Added a new function `sdma_v4_4_2_get_invalidate_req` to construct the
> VM_INVALIDATE_ENG0_REQ
> register value for the specified
On 3/19/2025 10:37 AM, jesse.zh...@amd.com wrote:
> From: "jesse.zh...@amd.com"
>
> - Modify the VM invalidation engine allocation logic to handle SDMA page
> rings.
> SDMA page rings now share the VM invalidation engine with SDMA gfx rings
> instead of
> allocating a separate engine. Th
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