[PATCH 14/16] Revert "drm/amd/display: dml2 soc dscclk use DPM table clk setting"

[Aurabindo Pillai]

From: Charlene Liu <charlene....@amd.com>

[why]
this dscclk use DCN defined per DPM level will cause a DCFCLK increase.
needs to follow up.

This reverts commit 9932ab57776fa0168b702371ff5e2881c026f353

Reviewed-by: Yihan Zhu <yihan....@amd.com>
Reviewed-by: Alvin Lee <alvin.l...@amd.com>
Signed-off-by: Charlene Liu <charlene....@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pil...@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c 
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
index 70c39df62533..2061d43b92e1 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
@@ -590,11 +590,11 @@ void dml2_init_soc_states(struct dml2_context *dml2, 
const struct dc *in_dc,
                        p->out_states->state_array[i].dtbclk_mhz = 
max_dtbclk_mhz;
                        p->out_states->state_array[i].phyclk_mhz = 
max_phyclk_mhz;
 
+                       p->out_states->state_array[i].dscclk_mhz = 
max_dispclk_mhz / 3.0;
                        p->out_states->state_array[i].phyclk_mhz = 
max_phyclk_mhz;
                        p->out_states->state_array[i].dtbclk_mhz = 
max_dtbclk_mhz;
 
                        /* Dependent states. */
-                       p->out_states->state_array[i].dscclk_mhz = 
p->in_states->state_array[i].dscclk_mhz;
                        p->out_states->state_array[i].dram_speed_mts = 
p->in_states->state_array[i].dram_speed_mts;
                        p->out_states->state_array[i].fabricclk_mhz = 
p->in_states->state_array[i].fabricclk_mhz;
                        p->out_states->state_array[i].socclk_mhz = 
p->in_states->state_array[i].socclk_mhz;
-- 
2.49.0